Download 4-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 16-Lead TSSOP AD7924-KGD

Known Good Die
4-Channel, 1 MSPS, 12-Bit ADC with
Sequencer in 16-Lead TSSOP
AD7924-KGD
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AV DD
REFIN
VIN0
T/H
I/P
MUX
VIN2
VIN3
SCLK
DOUT
SEQUENCER
The conversion process and data acquisition are controlled using
CS and the serial clock signal, allowing the device to easily interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and conversion is initiated at this point.
There are no pipeline delays associated with the part.
The AD7924-KGD uses advanced design techniques to achieve
very low power dissipation at maximum throughput rates. At
maximum throughput rates, the AD7924-KGD consumes 2 mA
maximum with 3 V supplies; with 5 V supplies, the current
consumption is 2.7 mA maximum.
Through the configuration of the control register, the analog input
range for the part can be selected as 0 V to REFIN or 0 V to 2 ×
REFIN, with either straight binary or twos complement output
coding. The AD7924-KGD features four single-ended analog
inputs with a channel sequencer to allow a preprogrammed
selection of channels to be converted sequentially.
The conversion time for the AD7924-KGD is determined by the
SCLK frequency, which is also used as the master clock to control
the conversion.
CONTROL LOGIC
DIN
CS
AD7924-KGD
VDRIVE
AGND
GENERAL DESCRIPTION
The AD7924-KGD is a 12-bit, high speed, low power, 4-channel
successive approximation ADCs. The parts operate from a single
2.7 V to 5.25 V power supply and feature throughput rates up to
1 MSPS. The part contains a low noise, wide bandwidth track-andhold amplifier that can handle input frequencies in excess of 8 MHz.
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
VIN1
10106-001
Fast throughput rate: 1 MSPS
Specified for AVDD of 2.7 V to 5.25 V
Low power
6 mW maximum at 1 MSPS with 3 V supplies
13.5 mW maximum at 1 MSPS with 5 V supplies
4 single-ended inputs with sequencer
Wide input bandwidth: 70 dB SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface: SPI/QSPI™/MICROWIRE™/DSP
compatible
Shutdown mode: 0.5 μA maximum
16-lead TSSOP package
Qualified for automotive applications
Known good die (KGD): these die are fully guaranteed to
data sheet specifications.
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
High Throughput with Low Power Consumption.
The AD7924-KGD offers throughput rates up to 1 MSPS.
At the maximum throughput rate with 3 V supplies, the
AD7924-KGD dissipates only 6 mW of power maximum.
Four Single-Ended Inputs with Channel Sequencer.
A consecutive sequence of channels can be selected,
through which the ADC will cycle and convert on.
Single-Supply Operation with VDRIVE Function.
The AD7924-KGD operates from a single 2.7 V to 5.25 V
supply. The VDRIVE function allows the serial interface to
connect directly to 3 V or 5 V processor systems,
independent of VDD.
Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced by increasing
the serial clock speed. The part also features two shutdown
modes to maximize power efficiency at lower throughput
rates. Current consumption is 0.5 μA maximum when in
full shutdown.
No Pipeline Delay.
The part features a standard successive approximation
ADC with accurate control of the sampling instant via
the CS input and once-off conversion control.
Additional application and technical information can be found
in the AD7924 data sheet.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
www.BDTIC.com/ADI/
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
AD7924-KGD
Known Good Die
TABLE OF CONTENTS
Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................6 General Description ......................................................................... 1 ESD Caution...................................................................................6 Functional Block Diagram .............................................................. 1 Pad Configuration and Function Descriptions .............................7 Product Highlights ........................................................................... 1 Outline Dimensions ..........................................................................8 Revision History ............................................................................... 2 Die Specifications and Assembly Recommendations ..............8 Specifications..................................................................................... 3 Ordering Guide .............................................................................8 Timing Specifications .................................................................. 5 REVISION HISTORY
10/11—Revision 0: Initial Version
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Rev. 0 | Page 2 of 8
Known Good Die
AD7924-KGD
SPECIFICATIONS
AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Temperature range is −40°C to +85°C.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion), SINAD
Signal-to-Noise Ratio, SNR
Total Harmonic Distortion, THD
Min
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN1
Max
Unit
−77
−73
−78
dB
dB
dB
dB
dB
dB
70
69
70
Peak Harmonic or Spurious Noise, SFDR
Intermodulation Distortion, IMD
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity, INL
Differential Nonlinearity, DNL
0 V to REFIN Input Range
Offset Error
Offset Error Match
Gain Error
Gain Error Match
0 V to 2 × REFIN Input Range
Typ
−90
−90
10
50
−85
8.2
1.6
dB
dB
ns
ps
dB
MHz
MHz
12
±1
−0.9/+1.5
Bits
LSB
LSB
±8
±0.5
±1.5
±0.5
LSB
LSB
LSB
LSB
Test Conditions/Comments
fIN = 50 kHz sine wave, fSCLK = 20 MHz
@5V
@ 3 V, typically 69.5 dB
@ 5 V, typically −84 dB
@ 3 V, typically −77 dB
@ 5 V, typically −86 dB
fa = 40.1 kHz, fb = 41.5 kHz
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 12 bits
Straight binary output coding
Typically ±0.5 LSB
−REFIN to +REFIN biased about REFIN with
twos complement output coding
0
0
±1.5
±0.5
±8
±0.5
±1
±0.5
LSB
LSB
LSB
LSB
LSB
LSB
REFIN
2 × REFIN
±1
V
V
μA
pF
RANGE bit set to 1
RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
V
μA
kΩ
±1% specified performance
20
2.5
±1
36
0.7 × VDRIVE
0.3 × VDRIVE
±1
10
V
V
μA
pF
Typically ±0.8 LSB
fSAMPLE = 1 MSPS
Typically 10 nA, VIN = 0 V or VDRIVE
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Rev. 0 | Page 3 of 8
AD7924-KGD
Known Good Die
Parameter
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance1
Output Coding
Min
Typ
VDRIVE − 0.2
0.4
±1
10
Straight (natural) binary
Twos complement
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE
IDD
Normal Mode (Static)
Normal Mode (Operational)
Auto Shutdown Mode
Full Shutdown Mode
Power Dissipation
Normal Mode (Operational)
Auto Shutdown Mode (Static)
Full Shutdown Mode
1
Max
2.7
2.7
Unit
Test Conditions/Comments
V
V
μA
pF
ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V
ISINK = 200 μA
CODING bit set to 1
CODING bit set to 0
800
300
300
1
ns
ns
ns
MSPS
5.25
5.25
V
V
16 SCLK cycles with SCLK at 20 MHz
Sine wave input
Full-scale step input
0.5
0.5
μA
mA
mA
μA
μA
μA
Digital inputs = 0 V or VDRIVE
AVDD = 2.7 V to 5.25 V, SCLK on or off
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
fSAMPLE = 250 kSPS
Static
SCLK on or off (20 nA typ)
13.5
6
2.5
1.5
2.5
1.5
mW
mW
μW
μW
μW
μW
AVDD = 5 V, fSCLK = 20 MHz
AVDD = 3 V, fSCLK = 20 MHz
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
AVDD = 3 V
600
2.7
2
960
Sample tested @ 25°C to ensure compliance.
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Rev. 0 | Page 4 of 8
Known Good Die
AD7924-KGD
TIMING SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter 1
fSCLK 2
tCONVERT
tQUIET
AVDD = 3 V
10
20
16 × tSCLK
50
t2
t3 3
t43
t5
t6
t7
t8 4
t9
t10
t11
t12
10
35
40
0.4 × tSCLK
0.4 × tSCLK
10
15/45
10
5
20
1
Limit at TMIN, TMAX
AVDD = 5 V
10
20
16 × tSCLK
50
10
30
40
0.4 × tSCLK
0.4 × tSCLK
10
15/35
10
5
20
1
Unit
kHz min
MHz max
Description
ns min
Minimum quiet time required between the CS rising edge and the start
of the next conversion
CS to SCLK setup time
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
16th SCLK falling edge to CS high
Power-up time from full shutdown/auto shutdown modes
ns min
ns max
ns max
ns min
ns min
ns min
ns min/ns max
ns min
ns min
ns min
μs max
1
Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V (see Figure 2).
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE.
4
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
1.6V
CL
50pF
200µA
IOH
10106-002
TO
OUTPUT
PIN
IOL
Figure 2. Load Circuit for Digital Output Timing Specifications
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Rev. 0 | Page 5 of 8
AD7924-KGD
Known Good Die
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to AGND
VDRIVE to AGND
Analog Input Voltage to AGND
Digital Input Voltage to AGND
Digital Output Voltage to AGND
REFIN to AGND
Input Current to Any Pin Except
Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Lead Temperature, Soldering
Vapor Phase (60 secs)
Infrared (15 secs)
ESD
1
Rating
−0.3 V to +7 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to +7 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
±10 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
215°C
220°C
1.5 kV
Transient currents of up to 100 mA do not cause SCR latch-up.
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Rev. 0 | Page 6 of 8
Known Good Die
AD7924-KGD
PAD CONFIGURATION AND FUNCTION DESCRIPTIONS
23
24
1
22
21
2
3
20
4
19
5
18
6
17
16
7
9
10
11
12
13
14
15
10106-003
8
Figure 3. Pad Configuration
Table 4. Pad Function Descriptions
Pad No.
1
2
3
4A
4B
5
6
7A
7B
8
9
10
11
12
13
14
15
16
17
18
19A
19B
20
21
22
23
24A
24B
X-Axis (μm)
−580.3
−815.4
−815.4
−850.85
−850.85
−854.15
−854.4
−850.45
−850.45
−854.2
−854.2
−712.45
−458.95
−108.95
+200.85
+550.85
+916.2
+916.2
+916.2
+916.2
880.85
880.85
896.05
865.35
865.35
725.35
−191
−291
Y-Axis (μm)
+965.95
+932.75
+677.6
+416
+316
+50.35
−258.7
−546
−646
−877.9
−1070.1
−1070.1
−1054.1
−1054.1
−1054.1
−1054.1
−1021.15
−671.15
−510.75
−160.75
144
244
537.15
885.8
1025.8
1025.8
+997.4
+997.4
Mnemonic
SCLK
DIN
CS
AGND
AGND
AVDD
AVDD
VREF
VREF
NC
AGND
AGND
NC
NC
NC
NC
VIN3
VIN2
VIN1
VIN0
AGND
AGND
DOUT
VDRIVE
VDRIVE
NC
AGND
AGND
Pad Type
Single
Single
Single
Double
Double
Double
Double
Double
Double
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Single
Double
Double
Single
Single
Single
Single
Double
Double
Description
Serial Clock
Data In, Logic Input.
Chip Select.
Analog Ground.
Analog Ground.
Analog Power Supply Input.
Analog Power Supply Input.
Reference Input.
Reference Input.
No Connect. Do not connect to this pin.
Analog Ground.
Analog Ground.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
Analog Input 0.
Analog Input 1.
Analog Input 2.
Analog Input 3.
Analog Ground.
Analog Ground.
Data Output.
Logic Power Supply Input.
Logic Power Supply Input.
No Connect. Do not connect to this pin.
Analog Ground.
Analog Ground.
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Rev. 0 | Page 7 of 8
AD7924-KGD
Known Good Die
OUTLINE DIMENSIONS
0.500
2.300
23
24
1
22
21
2
3
20
4
19
2.620
5
18
6
17
16
7
8
10
11
12
13
14
15
TOP VIEW
(CIRCUIT SIDE)
SIDE VIEW
0.092 × 0.092
09-12-2011-A
9
Figure 4. 24-Pad Bare Die [CHIP]
(C-24-1)
Dimensions shown in millimeters
DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS
Table 5. Die Specifications
Parameter
Chip Size
Scribe Line Width
Die Size
Thickness
Backside
Passivation
Bond Pads (Minimum)
Bond Pad Composition
ESD
Value
2180 (x) × 2450 (y)
120 (x) × 170 (y)
2300 (x) × 2620 (y)
500
Silicon
Nitride
92 × 92
98.5% Al, 1% Si, 0.5% Cu
1.5
Unit
μm
μm
μm
μm
Not applicable
Not applicable
μm
%
kV
Table 6. Assembly Recommendations
Assembly Component
Die Attach
Bonding Method
Bonding Sequence
Recommendation
No special recommendations
Gold ball or aluminum wedge
9 and 10
ORDERING GUIDE
Model
AD7924-KGD-DF
Temperature Range
−40°C to +85°C
Package Description
24-Pad Bare Die [CHIP]
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10106-0-10/11(0)
Package Option
C-24-1
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Rev. 0 | Page 8 of 8