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SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
FEATURES
D Low Total Power Consumption Increases
D
D
D
D
D
D
APPLICATIONS
ADSL Line Card Density (20 dBm on Line)
− 600 mW w/Active Termination (Full Bias)
− 530 mW w/Active Termination (Low Bias)
Low MTPR of –74 dBc (All Bias Conditions)
High Output Current of 500 mA (typ)
Wide Supply Voltage Range of ±5 V to ±15 V
[VCC(H)] and ±3.3 V to ±15 V [VCC(L)]
Wide Output Voltage Swing of 43 Vpp Into
100-Ω Differential Load [VCC(H) = ±12 V]
Multiple Bias Modes Allow Low Quiescent
Power Consumption for Short Line Lengths
− 160-mW/ch Full Bias Mode
− 135-mW/ch Mid Bias Mode
− 110-mW/ch Low Bias Mode
− 75-mW/ch Terminate Only Mode
− 13-mW/ch Shutdown Mode
Low Noise for Increased Receiver Sensitivity
− 3.3 pA/√Hz Noninverting Current Noise
− 9.5 pA/√Hz Inverting Current Noise
− 3.5 nV/√Hz Voltage Noise
D Ideal for Active Termination Full Rate ADSL
DMT applications (20-dBm Line Power)
DESCRIPTION
The THS6132 is a Class-G current feedback differential
line driver ideal for full rate ADSL DMT systems. Its
extremely low power consumption of 600 mW or lower is
ideal for ADSL systems that must achieve high densities
in ADSL central office rack applications. The unique patent
pending architecture of the THS6132 allows the quiescent
current to be much lower than existing line drivers while
still achieving very high linearity. In addition, the multiple
bias settings of the amplifiers allow for even lower power
consumption for line lengths where the full performance of
the amplifier is not required. The output voltage swing has
been vastly improved over first generation Glass-G
amplifiers and allows the use of lower power supply
voltages that help conserve power. For maximum
flexibility, the THS6132 can be configured in classical
Class-AB mode requiring only as few as one power supply.
Typical ADSL CO Line Driver Circuit Utilizing Active Impedance Supporting A 6.3 Crest Factor
+15V
THS6132a
+6V
CODEC
VIN+
12.4 Ω
+
−
1 kΩ
1.33 kΩ
576 Ω
1:1
+20 dBm
Line
Power
1.33 kΩ
100 Ω
1 kΩ
12.4 Ω
−
CODEC
VIN−
+
−6V
− 15 V
THS6132b
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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! "#$ ! %#&'" ($) (#"!
" !%$""! %$ *$ $! $+! !#$! !(( ,-)
(#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!)
Copyright  2002−2003, Texas Instruments Incorporated
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SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage.
ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
CODE
SYMBOL
THS6132VFP
TQFP-32 PowerPAD
VFP−32
THS6132
TA
−40°C to 85°C
Leadless 25-pin 5,mm x
THS6132RGW
5, mm PowerPAD
RGW−25
6132
ORDER NUMBER
TRANSPORT
MEDIA
THS6132VFP
Tube
THS6132VFPR
Tape and reel
THS6132RGWR
Tape and reel
PACKAGE DISSIPATION RATINGS
PACKAGE
ΘJA
ΘJC
TA ≤ 25°C
POWER RATING(1)
TA = 70°C
POWER RATING(1)
TA = 85°C
POWER RATING(1)
VFP−32
29.4°C/W
0.96°C/W
3.57 W
2.04 W
1.53 W
RGW−25
31°C/W
1.7°C/W
3.39 W
1.94 W
1.45 W
(1) Power rating is determined with a junction temperature of 130°C. This is the point where distortion starts to substantially increase. Thermal
management of the final PCB should strive to keep the junction temperature at or below 125_C for best performance.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
THS6132
Supply voltage, VCC(H) and VCC(L) (2)
±16.5 V
Input voltage, VI
±VCC(L)
900 mA
Output current, IO (3)
±2 V
Differential input voltage, VIO
Maximum junction temperature, TJ (see Dissipation Rating Table for more information)
150°C
Operating free−air temperature, TA
−40°C to 85°C
Storage temperature, TStg
65°C to 150°C
Lead temperature, 1,6 mm (1/16−inch) from case for 10 seconds
ESD ratings
300°C
HBM
1 kV
CDM
500 V
MM
200 V
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VCC(H) must always be greater than or equal to VCC(L) for proper operation. Class-AB mode operation occurs when VCC(H) is equal to VCC(L)
and is considered acceptable operation for the THS6132 even though it is not fully specified in this mode of operation.
(3) The THS6132 incorporates a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipating
plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature that could permanently damage
the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package.
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PowerPAD is a trademark of Texas Instruments.
2
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SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
RECOMMENDED OPERATING CONDITIONS
+VCC(H) to −VCC(H)
+VCC(L) to −VCC(L)
Supply voltage
Operating free-air temperature, TA
MIN
NOM
MAX
±VCC(L)
±15
±16
±3.3
±5
±VCC(H)
V
85
°C
−40
UNIT
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, TA = 25°C,VCC(H) = ±15 V, VCC(L) = ±5 V RF = 1.5 kΩ, Gain = +10, Full Bias Mode, RL
= 50 Ω (unless otherwise noted)
NOISE/DISTORTION PERFORMANCE
PARAMETER
HD
Vn
In
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Multitone power ratio
Gain =+11, 163kHz to 1.1MHz DMT,
+20 dBm Line Power, 1:1.1 transformer,
active termination, synthesis factor = 4
−74
dBc
Receive band spill-over
Gain =+11, 25 kHz to 138 kHz with MTPR signal
applied
−95
dBc
Differential load = 100 Ω
−84
Differential load = 25 Ω
−69
Differential load = 100 Ω
−92
Differential load = 25 Ω
−73
Harmonic distortion (Differential
Configuration, f = 1 MHz,
VO(PP) = 2 V, Gain = +10)
Input voltage noise
Input current noise
2nd harmonic
3rd harmonic
f = 10 kHz
+Input
−Input
3.5
3.3
f = 10 kHz
9.5
dBc
dBc
nV/√Hz
pA/√Hz
f = 1 MHz,
RL = 100 Ω,
VO(PP) = 2 V,
Gain = +2
VCC(H) = ±12 V
RL = 100 Ω
RL = 30 Ω
±10.4
±10.8
±9.9
±10.4
VCC(H) = ±15 V
RL = 100 Ω
RL = 50 Ω
±13.3
±13.8
±13
±13.6
Output voltage transition from VCC(L) to
VCC(H) (Point where ICC(L) = ICC(H))
RL = 50 Ω
VCC(L) = ±5 V
VCC(L) = ±6 V
IO
Output current (1)
RL = 10 Ω
VCC(H) = ±12 V
VCC(H) = ±15 V
I(SC)
Short-circuit current (1)
RL = 1 Ω
Open-loop
VCC(H) = ±15 V
Output resistance
Output resistance—terminate mode
f = 1 MHz,
Gain = +10
0.35
Ω
Output resistance—shutdown mode
f = 1 MHz,
Open-loop
5.5
kΩ
Crosstalk
−52
dBc
OUTPUT CHARACTERISTICS
VO
Single−ended output voltage swing
±3.1
±3.9
±500
±400
V
V
V
±500
mA
±750
mA
5
Ω
(1) A heatsink is required to keep the junction temperature below absolute maximum rating when an output is heavily loaded or shorted. See
Absolute Maximum Ratings section for more information.
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3
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SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range, TA = 25°C,VCC(H) = ±15 V, VCC(L) = ±5 V RF = 1.5 kΩ, Gain = +10, Full Bias Mode, RL
= 50 Ω (unless otherwise noted)
POWER SUPPLY
PARAMETER
VCC(x)
TEST CONDITIONS
±VCC(H)
±VCC(L)
Operating range
Quiescent current (each driver)
Full-bias mode
(Bias−1 = 1, Bias−2 = 1,
Bias−3 = X)
(Icc trimmed with VCC(H) = ±15 V,
VCC(L) = ±5 V)
ICC
Quiescent current (each driver)
Variable bias modes,
VCC(L) = ±5 V
Quiescent current (each driver)
Variable bias modes,
VCC(H) = ±15 V
PSRR
Power supply rejection ratio
((∆V
VCC(x) = ±1
1 V)
MIN
TYP
MAX
±VCC(L)
±3
±15
±16.5
±5
5.7
6.4
±VCC(H)
7.5
VCC(L) = ±5 V;
(VCC(H)= ±15 V)
TA = 25°C
TA = full range
VCC(L) = ±6 V;
(VCC(H) = ±15 V)
TA = 25°C
TA = full range
6.7
VCC(H) = ±12 V;
(VCC(L) = ±5 V)
TA = 25°C
TA = full range
3.1
8.1
5.0
5.6
6.8
Low; Bias−1 = 1, Bias−2 = 0, Bias−3 = 0
4.25
4.8
6.0
Terminate; Bias−1 = 0, Bias−2 = 1, Bias−3 = X(1)
Shutdown; Bias−1 = 0, Bias−2 = 0, Bias−3 = X(1)
3.2
3.8
4.5
1
1.3
Mid; Bias−1 = 1, Bias−2 = 0, Bias−3 = 1
2.4
2.7
3.0
Low ; Bias−1 = 1, Bias−2 = 0, Bias−3 = 0
1.9
2.15
2.4
Terminate; Bias−1 = 0, Bias−2 = 1, Bias−3 = X(1)
Shutdown ; Bias−1 = 0, Bias−2 = 0, Bias−3 = X(1)
1.1
1.3
1.5
0.1
0.5
VCC(L) = ±5V
TA = 25°C
TA = full range
−70
−82
VCC(H) = ±15V
TA = 25°C
TA = full range
−70
−68
(1) X is used to denote a logic state of either 1 or 0.
4
3.75
4.25
−82
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mA
mA
2.9
−68
V
mA
TA = 25°C
VCC(H) = ±15 V;
TA = full range
(VCC(L) = ±5 V)
Mid; Bias−1 = 1, Bias−2 = 0, Bias−3 = 1
3.25
UNIT
mA
mA
mA
dB
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SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range, TA = 25°C,VCC(H) = ±15 V, VCC(L) = ±5 V RF = 1.5 kΩ, Gain = +10, Full Bias Mode, RL
= 50 Ω (unless otherwise noted)
DYNAMIC PERFORMANCE
PARAMETER
TEST CONDITIONS
RL = 100 Ω
BW
Single-ended small-signal bandwidth
(−3 dB), VO = 0.1 Vrms
RL = 25 Ω
SR
Single-ended slew-rate(1)
VO = 20 VPP,
MIN
TYP
Gain = +1, RF = 750 Ω
80
Gain = +2, RF = 620 Ω
70
Gain = +5, RF = 500 Ω
60
Gain = +10, RF = 1 kΩ
20
Gain = +1, RF = 750 Ω
60
Gain = +2, RF = 620 Ω
55
Gain = +5, RF = 500 Ω
50
MAX
UNIT
MHz
MHz
Gain = +10, RF = 1 kΩ
17
Gain =+10
300
V/µs
(1) Slew-rate is defined from the 25% to the 75% output levels
DC PERFORMANCE
PARAMETER
TEST CONDITIONS
Input offset voltage
VOS
Differential offset voltage
VCC(L) = ± 5 V, ±6 V
Offset drift
−Input bias current
VCC(L) = ±5 V, ±6 V
IIB
+ Input bias current
ZOL
Open loop transimpedance
TYP
MAX
TA = 25°C
TA = full range
MIN
1
15
TA = 25°C
TA = full range
0.3
TA = full range
TA = 25°C
40
TA = full range
TA = 25°C
20
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mV
8
1
µV/°C
15
20
1.5
TA = full range
RL = 1 kΩ
6
UNIT
15
µA
20
2
MΩ
5
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SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range, TA = 25°C,VCC(H) = ±15 V, VCC(L) = ±5 V RF = 1.5 kΩ, Gain = +10, Full Bias Mode, RL
= 50 Ω (unless otherwise noted)
INPUT CHARACTERISTICS
PARAMETER
VICR
Input common−mode voltage range(1)
REF pin input voltage range
CMRR
Common-mode rejection ratio
RI
Input resistance
CI
Differential Input capacitance
TEST CONDITIONS
VCC(L) = ±5 V
VCC(L) = ±6 V
VCC−(L)= ±5 V
TA = 25°C
TA = full range
MIN
TYP
±2.7
±3.0
UNIT
±2.6
V
±4.0
TA = 25°C
±2.5
VCC(L) = ±6 V
VCC(L) = ±5 V, ±6 V
MAX
V
±3.5
TA = 25°C
TA = full range
60
67
dB
57
+ Input
800
− Input
45
kΩ
Ω
1.2
pF
(1) To conserve as much power as possible, the input stage of the THS6132 is powered from the VCC(L) supplies and is limited by the VCC(L) supply
voltage. For Class-AB operation, connect the VCC(L) supplies to VCC(H).
LOGIC CONTROL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
VIH
VIL
Bias pin voltage for logic 1
Relative to DGND pin voltage
2.0
Bias pin voltage for logic 0
Relative to DGND pin voltage
IIH
IIL
Bias pin current for logic 1
VIH = 5 V, DGND = 0 V
VIL = 0 V, DGND = 0 V
Bias pin current for logic 0
Transition time—logic 0 to logic 1(1)
Transition time—logic 1 to logic 0(1)
TYP
MAX
UNIT
V
0.8
V
−0.1
−0.2
µA
−0.1
−0.2
µA
µs
0.1
µs
0.2
DGND useable range
−VCC(H)
+VCC(H) −5
V
(1) Transition time is defined as the time from when the logic signal is applied to the time when the supply current has reached half its final value.
LOGIC TABLE
BIAS-1
BIAS-2
1
1
BIAS-3
X(1)
Full bias mode
FUNCTION
Amplifiers ON with lowest distortion possible
DESCRIPTION
1
0
1
Mid bias mode
Amplifiers ON with power savings with a reduction in distortion performance
1
0
Low bias mode
Amplifiers ON with enhanced power savings and a reduction of distortion performance
0
1
0
X(1)
Terminate mode
Lowest power state with +Vin pins internally connect to REF pin and output has low impedance
0
0
X(1)
Shutdown mode
Amplifiers OFF and output has high impedance
(1) X is used to denote a logic state of either 1 or 0.
NOTE: The default state for all logic pins is a logic one (1).
6
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SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
+12V
THS6132a
+5V
CODEC
8.66 Ω
+
VIN+
−
1k
953 Ω
Ω
1.33 k
Ω
1.33 k
Ω
1k
1:1.2
Power
100 Ω
Ω
8.66Ω
−
CODEC
+20 dBm
Line
+
VIN−
−5V
THS6132b
−12V
Figure 1. ±12 V Active Termination ADSL CO Line Driver Circuit (Synthesis Factor = 4; CF = 5.6)
PIN ASSIGNMENTS
32 31 30 29 28 27 26 25
24
23
22
21
TM
PowerPAD
20
19
18
17
9 10 11 12 13 14 15 16
NC
OUT1
NC
IN1−
IN2−
NC
OUT2
NC
REF
IN1+
IN2+
DGND
BIAS−1
Power
PAD
TM
OUT1
IN1−
NC
IN2−
OUT2
BIAS−2
BIAS−3
−VCCH
−VCCH
−VCCL
1
2
3
4
5
6
7
8
BIAS−2
BIAS−3
NC
−VCCH
−VCCH
−VCCH
−VCCL
−VCCL
NC
REF
NC
IN1+
IN2+
NC
DGND
BIAS−1
THS6132
Leadless 5X5 PowerPAD
(RGW) PACKAGE
(TOP VIEW)
NC
NC
+VCCH
+VCCH
+VCCL
NC
NC
NC
+VCCH
+VCCH
+VCCH
+VCCL
+VCCL
THS6132
TQFP PowerPAD (VFP) PACKAGE
(TOP VIEW)
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SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Output voltage headroom
vs Output current
2
Common-mode rejection ratio
vs Frequency
3
Crosstalk
vs Frequency
Quiescent current
vs Temperature
Large signal bandwidth
vs Frequency
Noise
vs Frequency
4
5, 6
7 − 10
11
Overdrive recovery
12
Power supply rejection ratio
vs Frequency
13
Small signal frequency response
14, 15, 16
Small signal bandwidth
vs Frequency
Slew rate
vs Output voltage
Closed-loop output impedance
vs Frequency
17 − 28
29
30, 31
Shutdown response
32
Common-mode rejection ratio
vs Common-mode input voltage
33
Input bias current
vs Temperature
34
Input offset voltage
vs Temperature
Current draw distribution
vs Output voltage
Output voltage
vs Temperature
Differential distortion
vs Frequency
39 − 52
Differential distortion
vs Differential output voltage
53 − 63
Single ended distortion
vs Frequency
64, 65
70
0
60
−10
Gain = 2
6
5
4
40
−20
Gain − dB
50
7
Gain = 10
30
Gain = 10
−30
−40
Gain = 2
−50
20
3
−60
2
10
−70
1
0
100
200
300
400
Output Current −mA
Figure 2
8
CROSSTALK
vs
FREQUENCY
Rload = 100 Ω
VCCH ±15V
VCCL = ±5V
Gain = 10
Gain − dB
Output Voltage Headroom − V CC −Vout
10
8
38
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
OUTPUT VOLTAGE HEADROOM
vs
OUTPUT CURRENT
9
35
36, 37
500
600
0
10 k
100 k
1M
10 M
f − Frequency − Hz
Figure 3
100 M
−80
100 k
1M
10 M
f − Frequency − Hz
Figure 4
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100 M
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SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
8
14
5
Low Bias
4
3
Terminate Mode
18
10
12
Low Bias
8
Terminate Mode
6
Shutdown
0
20
40
60
T − Temperature − °C
80
0
−40
100
−20
0
20
40
60
T − Temperature − °C
Figure 5
Gain − dB
12
30
VO = 8 VPP
VO = 4 VPP
24
18
Output Voltage − dB
18
VO = 2 VPP
6
0
−6
−12
VO = 1 VPP
VO = 0.5 VPP
12
6
0
−6
VO = 0.25 VPP
−18
100 k
1M
−12
10 M
100 M
VO = 8 VPP
VO = 4 VPP
100
10
In +
1
1
1k
10 k
f − Frequency − Hz
24
18
VO = 0.5 VPP
VO = 0.25 VPP
100 k
12
6
0
−6
−12
10 M
100 M
1G
VCCH= ±15 V
VCCL= ±5 V
Gain =10
Rf = 1 kΩ
Rl = 100 Ω
VO = 16 VPP
VO = 8 VPP
VO = 4 VPP
VO = 2 VPP
VO = 1 VPP
VO = 0.5 VPP
VO = 0.25 VPP
100 k
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 9
Figure 10
OVERDRIVE RECOVERY
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
80
10
70
0.5
5
0
0
−5
−0.5
−1
−10
−1.5
−15
0.2
0.4
0.6
t − Time − ns
0.8
90
15
VCCH= ±15 V
VCCL= ±5 V
Gain = 10
Rload = 100 Ω
0
1G
−18
1M
1
VI − Input Voltage − V
Vn
100 M
30
1.5
Hz
In −
I n − Current Noise − pA/
Hz
Vn − Voltage Noise − nV/
10 M
LARGE SIGNAL BANDWIDTH
vs
FREQUENCY
f − Frequency − Hz
100
Figure 11
1M
Figure 7
VO = 1 VPP
−18
100 k
1G
NOISE
vs
FREQUENCY
100
VO = 0.25 VPP
f − Frequency − Hz
VO = 2 VPP
Figure 8
10
VO = 0.5 VPP
−18
100 k
100
VCCH= ±15 V
VCCL= ±5 V
Gain =10
Rf = 1 kΩ
Rl = 25 Ω
VO = 16 VPP
f − Frequency − Hz
10
VO = 1 VPP
0
LARGE SIGNAL BANDWIDTH
vs
FREQUENCY
VCCH= ±15 V
VCCL= ±5 V
Gain = 5
Rf = 1 kΩ
Rl = 100 Ω
VO = 16 VPP
VO = 2 VPP
6
Figure 6
LARGE SIGNAL BANDWIDTH
vs
FREQUENCY
30
80
Output Voltage − dB
−20
1
V − Input Voltage − V
PSRR − dB
−40
VO = 4 VPP
−12
Shutdown
0
VO = 8 VPP
−6
4
2
1
24
24
12
VCCH= ±15 V
VCCL= ±5 V
Gain = 5
Rf = 1 kΩ
Rl = 25 Ω
VO = 16 VPP
Full Bias
Mid Bias
Quiescent Current − mA
Mid Bias
6
2
VCCH = ±15V
VCCL = ±5V
Full Bias
Gain − dB
7
Quiescent Current − mA
30
16
VCCH = ±15V
VCCL = ±5V
LARGE SIGNAL BANDWIDTH
vs
FREQUENCY
QUIESCENT CURRENT
vs
TEMPERATURE
QUIESCENT CURRENT
vs
TEMPERATURE
60
50
±VCCH
±VCCL
40
30
20
10
0
1k
10 k
Figure 12
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100 k
1M
10 M
100 M
f − Frequency − Hz
Figure 13
9
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SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
SMALL SIGNAL FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE
2
2
1
0
0
Mid Bias
−1
−1
Full Bias
−3
VCCH= ±15 V
VCCL= ±5 V
Gain =1
VO = 0.1 Vrms
Rf = 750 Ω
Rl = 25 Ω
−4
−5
−6
−7
100 k
−2
−3
VCCH= ±15 V
VCCL= ±5 V
Gain =1
VO = 0.1 Vrms
Rf = 750 Ω
Rl = 100 Ω
−5
−6
1M
10 M
f − Frequency − Hz
−7
100 k
100 M
1M
−7
100 k
100 M
8
7
Mid Bias
7
6
−4
−5
−6
−7
100 k
2
1
0
1M
10 M
−1
100 k
100 M
VCCH= ±15 V
VCCL= ±5 V
Gain =2
VO = 0.1 Vrms
Rf = 620 Ω
Rl = 100 Ω
Figure 17
100 M
13
12
12
Gain − dB
RF = 2 kΩ
11
RF = 1 kΩ
VCCH= ±15 V
VCCL= ±5 V
Gain =5
VO = 0.1 Vrms
Rl = 25 Ω
Full Bias
7
1M
10 M
f − Frequency − Hz
Figure 20
100 M
6
100 k
100 M
15
RF = 500 Ω
14
13
12
RF = 2 kΩ
RF = 1 kΩ
10
8
1M
10 M
f − Frequency − Hz
SMALL SIGNAL BANDWIDTH
vs
FREQUENCY
11
9
VCCH= ±15 V
VCCL= ±15 V
Gain =2
VO = 0.1 Vrms
Rf = 620 Ω
Rl = 25 Ω
Figure 19
RF = 500 Ω
14
13
6
100 k
0
−1
100 k
15
RF = 500 Ω
14
7
1
SMALL SIGNAL BANDWIDTH
vs
FREQUENCY
15
8
3
Figure 18
SMALL SIGNAL BANDWIDTH
vs
FREQUENCY
10
4
2
1M
10 M
f − Frequency − Hz
f − Frequency − Hz
9
Gain − dB
Gain − dB
4
3
Full Bias
5
Full Bias
5
VCCH= ±15 V
VCCL= ±15 V
Gain =1
VO = 0.1 Vrms
Rf = 750 Ω
Rl = 25 Ω
Low Bias
Low Bias
6
Full Bias
100 M
SMALL SIGNAL BANDWIDTH
vs
FREQUENCY
Mid Bias
Low Bias
10 M
Figure 16
8
−3
1M
f − Frequency − Hz
SMALL SIGNAL BANDWIDTH
vs
FREQUENCY
−2
Gain − dB
10 M
VCCH= ±15 V
VCCL= ±15 V
Gain =1
VO = 0.1 Vrms
Rf = 750 Ω
Rl = 25 Ω
f − Frequency − Hz
0
10
−3
−6
SMALL SIGNAL BANDWIDTH
vs
FREQUENCY
−1
Full Bias
−5
Figure 15
Mid Bias
Mid Bias
−2
−4
Figure 14
1
Low Bias
1
Full Bias
−4
2
Gain − dB
Mid Bias
Gain − dB
Gain − dB
−2
Gain − dB
0
−1
2
Low Bias
Low Bias
Gain − dB
1
VCCH= ±15 V
VCCL= ±5 V
Gain =5
VO = 0.1 Vrms
Rl = 25 Ω
Mid Bias
1M
10 M
f − Frequency − Hz
Figure 21
10
9
8
7
100 M
RF = 2 kΩ
11
6
100 k
RF = 1 kΩ
VCCH= ±15 V
VCCL= ±5 V
Gain =5
VO = 0.1 Vrms
Rl = 25 Ω
Low Bias
1M
10 M
f − Frequency − Hz
Figure 22
www.BDTIC.com/TI
100 M
www.ti.com
SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
SMALL SIGNAL BANDWIDTH
vs
FREQUENCY
SMALL SIGNAL BANDWIDTH
vs
FREQUENCY
15
15
RF = 500 Ω
14
SMALL SIGNAL BANDWIDTH
vs
FREQUENCY
13
23
RF = 500 Ω
14
20
13
17
12
11
RF = 1 kΩ
VCCH= ±15 V
VCCL= ±5 V
Gain =5
VO = 0.1 Vrms
Rl = 100 Ω
Full Bias
9
8
7
6
100 k
11
RF = 1 kΩ
10
VCCH= ±15 V
VCCL= ±5 V
Gain =5
VO = 0.1 Vrms
Rl = 100 Ω
Low Bias
9
8
7
1M
10 M
f − Frequency − Hz
6
100 k
100 M
20
20
17
17
14
14
Gain − dB
11
2
8
Full Bias
5
Mid Bias
2
Low Bias
1M
10 M
f − Frequency − Hz
100 M
17
VCCH = ±15 V
VCCL = ±5 V
Gain = −10
VO = 0.1 Vrms
Rf = 1 kΩ
RL= 100 Ω
14
Full Bias
11
8
Mid Bias
5
2
Low Bias
1M
10 M
f − Frequency − Hz
−SR
200
VCCH = ±15V
VCCL = ±5V
Gain = 5
Rload = 100 Ω
100
50
0
0
5
10
15
VO − Output Voltage − VPP
Figure 29
20
Full Bias
Mid Bias
Low Bias
100 k
1M
10 M
f − Frequency − Hz
100 M
Figure 28
10000
300
150
100 M
CLOSED LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
+SR
250
VCCH= ±15 V
VCCL= ±5 V
Gain =−10
VO = 0.1 Vrms
Rf = 1 kΩ
RL= 25 Ω
−1
100 k
Closed-Loop Output Impedance − Ω
350
100 M
20
Figure 27
400
Low Bias
1M
10 M
f − Frequency − Hz
23
Figure 26
SLEW RATE
vs
OUTPUT VOLTAGE
Mid Bias
SMALL SIGNAL BANDWIDTH
vs
FREQUENCY
−1
100 k
Full Bias
Figure 25
11
−1
Slew-Rate − V/ µ s
−1
100 k
100 M
CLOSED LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
10000
Shutdown
1000
100
Gain = 2
10
Terminate
Low Bias
1
Full Bias
0.1
0.01
100 k
1M
10 M
f − Frequency − Hz
100 M
Closed-Loop Output Impedance − Ω
Gain − dB
23
5
2
SMALL SIGNAL BANDWIDTH
vs
FREQUENCY
23
VCCH= ±15 V
VCCL= ±5 V
Gain =10
VO = 0.1 Vrms
Rf = 1 kΩ
RL= 100 Ω
VCCH= ±15 V
VCCL= ±5 V
Gain =10
VO = 0.1 Vrms
Rf = 1 kΩ
RL= 25 Ω
8
Figure 24
SMALL SIGNAL BANDWIDTH
vs
FREQUENCY
8
11
5
1M
10 M
f − Frequency − Hz
Figure 23
14
Gain − dB
10
RF = 2 kΩ
Gain − dB
RF = 2 kΩ
Gain − dB
Gain − dB
12
Shutdown
1000
100
Terminate
Gain = 10
10
Low Bias
1
Full Bias
0.1
0.01
100 k
Figure 30
www.BDTIC.com/TI
1M
10 M
100 M
f − Frequency − Hz
Figure 31
11
www.ti.com
SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
SHUTDOWN RESPONSE
2
VCCH = ±15V
VCCL = ±5V
Gain = 5
VIN = 1 Vdc
Rload = 100 Ω
0
60
85°C
25°C
50
40
30
20
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
−3
−1
lib+
−2
−0.6
−0.8
Vio − Channel B
−1.2
−20
0
20
40
60
T − Temperature − °C
80
60
VCCL= ±7.5 V
VCCL= ±5 V
40
20
VCCL= ±6 V
1
2
3
4
5
Output Voltage − VRMS
6
7
−30
−40
Distortion − dBc
12
VCCH= ±12 V, Rl = 100 Ω
VCCL= ±7.5 V
40
VCCH= ±15 V
Rload = 25 Ω
Gain = 10
f = 1 MHz
20
1
2
3
4
5
Output Voltage − VRMS
−50
VCCH= ±12 V, Rl = 30 Ω
0
20
40
60
T − Temperature − °C
−20
Gain =10
Full Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 100 Ω
−30
−40
HD3
−70
HD2
100
−110
100 k
−50
Gain =10
Mid Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 100 Ω
HD3
−60
−70
−80
HD2
−90
VCCH= ±15 V
VCCL= ±5 V
−100
80
7
DIFFERENTIAL DISTORTION
vs
FREQUENCY
−60
−80
6
Figure 37
−90
10.5
Figure 38
VCCL= ±6 V
60
0
−20
−20
VCCL= ±5 V
80
DIFFERENTIAL DISTORTION
vs
FREQUENCY
VCCH= ±15 V, Rl = 50 Ω
100
0
0
VCCH= ±15 V, Rl = 100 Ω
80
CURRENT DRAW DISTRIBUTION
vs
OUTPUT VOLTAGE
Figure 36
12.5
9.5
−40
0
20
40
60
T − Temperature − °C
Figure 34
0
100
14.5
10
−20
100
80
OUTPUT VOLTAGE
vs
TEMPERATURE
11
−40
4
VCCH= ±15 V
Rload = 25 Ω
Gain = 10
f = 1 MHz
Figure 35
11.5
3
− Current Draw Distribution − %
Vio − Channel A
−0.4
13
2
I CCH
I CCL − Current Draw Distribution − %
−0.2
13.5
1
100
VCCH = ±15V
VCCL = ±5V
0
14
0
CURRENT DRAW DISTRIBUTION
vs
OUTPUT VOLTAGE
0.2
−1.4
−40
−1
Figure 33
INPUT OFFSET VOLTAGE
vs
TEMPERATURE
−1
−2
Common-Mode Input Voltage − ±VCCL
Figure 32
Input Offset Voltage − mV
−0.5
VCCH = ±15V
VCCL = ±5V
−4
1
t − Time − ns
Output Voltage − |V|
0
0
0
VCCH = ±15V
VCCL = ±5V
−1.5
10
−1
12
Input Bias Current − µ A
Output Voltage
lib−
70
Distortion − dBc
V− Voltage _ V
4
1
−40°C
Common-Mode Rejection Ratio − dB
5
V−SHDN
0.5
80
6
3
INPUT BIAS CURRENT
vs
TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
COMMON-MODE INPUT VOLTAGE
1M
10 M
f − Frequency − Hz
Figure 39
VCCH= ±15 V
VCCL= ±5 V
−100
100 M
−110
100 k
1M
10 M
f − Frequency − Hz
Figure 40
www.BDTIC.com/TI
100 M
www.ti.com
SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
DIFFERENTIAL DISTORTION
vs
FREQUENCY
DIFFERENTIAL DISTORTION
vs
FREQUENCY
−20
Gain =10
Low Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 100 Ω
−40
−40
HD3
−60
−70
HD2
−80
−50
HD2
−80
−90
VCCH= ±15 V
VCCL= ±5 V
−110
100 k
1M
10 M
−110
100 k
100 M
1M
10 M
−60
Figure 42
DIFFERENTIAL DISTORTION
vs
FREQUENCY
DIFFERENTIAL DISTORTION
vs
FREQUENCY
−20
−80
−110
100 k
100 M
HD3
−40
−60
HD2
−70
−80
−90
−50
VCCH= ±15 V
VCCL= ±5 V
−110
100 k
1M
10 M
DIFFERENTIAL DISTORTION
vs
FREQUENCY
VCCH= ±15 V
VCCL= ±5 V
10 M
Figure 45
−30
−40
−80
−50
VCCH= ±15 V
VCCL= ±5 V
10 M
f − Frequency − Hz
Figure 47
HD2
Gain =5
Full Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 100 Ω
10 M
100 M
DIFFERENTIAL DISTORTION
vs
FREQUENCY
−20
−30
−40
HD3
−80
HD2
1M
10 M
f − Frequency − Hz
−50
Gain =5
Full Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 25 Ω
HD3
−60
−70
HD2
−80
−90
VCCH= ±15 V
VCCL= ±15 V
−100
100 M
1M
Figure 46
−70
−110
100 k
VCCH= ±15 V
VCCL= ±5 V
f − Frequency − Hz
−90
1M
−80
−110
100 k
100 M
−60
HD2
−90
−100
−70
−100
−20
−70
HD3
−60
DIFFERENTIAL DISTORTION
vs
FREQUENCY
−60
−110
100 k
1M
Figure 44
HD3
Gain =5
Mid Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 100 Ω
−90
f − Frequency − Hz
Gain =5
Low Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 100 Ω
−50
HD2
f − Frequency − Hz
Distortion − dBc
−50
HD3
−80
−110
100 k
−20
−40
−40
−70
DIFFERENTIAL DISTORTION
vs
FREQUENCY
−30
−30
−100
100 M
100 M
Figure 43
−60
−90
−100
10 M
f − Frequency − Hz
Distortion − dBc
−50
1M
−20
Gain =5
Full Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 100 Ω
−30
Distortion − dBc
−40
VCCH= ±15 V
VCCL= ±5 V
−100
−20
Gain =10
Low Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 25 Ω
−30
HD2
−70
f − Frequency − Hz
Figure 41
HD3
−90
VCCH= ±15 V
VCCL= ±5 V
−100
f − Frequency − Hz
Distortion − dBc
−50
−90
−100
Distortion − dBc
−40
−60
−70
Gain =10
Mid Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 25 Ω
−30
HD3
Distortion − dBc
Distortion − dBc
−50
−20
Gain =10
Full Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 25 Ω
−30
Distortion − dBc
−30
Distortion − dBc
−20
DIFFERENTIAL DISTORTION
vs
FREQUENCY
VCCH ±15 V
VCCL= ±5 V
−100
100 M
−110
100 k
Figure 48
www.BDTIC.com/TI
1M
10 M
100 M
f − Frequency − Hz
Figure 49
13
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SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
DIFFERENTIAL DISTORTION
vs
FREQUENCY
DIFFERENTIAL DISTORTION
vs
FREQUENCY
−20
−20
−50
HD3
−40
−60
−70
−50
Distortion − dBc
HD2
−80
HD2
−80
−90
−90
VCCH = ±15 V
VCCL = ±5 V
−100
−110
100 k
1M
10 M
−110
100 k
100 M
1M
−55
−65
HD2
−75
−80
DIFFERENTIAL DISTORTION
vs
DIFFERENTIAL OUTPUT VOLTAGE
VCCH = ±15 V
VCCL = ±5 V
−60
−70
HD2
−75
−90
7
9
11
13
15
−75
HD3
3
5
7
9
11
13
1
15
Figure 54
DIFFERENTIAL DISTORTION
vs
DIFFERENTIAL OUTPUT VOLTAGE
VCCH = ±15 V
VCCL = ±5 V
Distortion − dBc
−75
HD2
−85
−90
HD3
VCCH = ±15 V
VCCL = ±5 V
HD2
−85
−90
HD3
Figure 56
40
15
−80
HD2
−85
−90
HD3
−100
−105
−105
5
10 15 20 25 30 35
Differential Output Voltage − VPP
13
−95
−100
−105
11
VCCH = ±15 V
VCCL = ±5 V
Gain =5
Low Bias
Rf = 1 kΩ
RL= 100 Ω
f = 1 MHz
−70
−75
−80
−95
−100
9
−65
Gain =5
Mid Bias
Rf = 1 kΩ
RL= 100 Ω
f = 1 MHz
−70
−80
7
DIFFERENTIAL DISTORTION
vs
DIFFERENTIAL OUTPUT VOLTAGE
−65
Gain =5
Full Bias
Rf = 1 kΩ
RL= 100 Ω
f = 1 MHz
5
Figure 55
DIFFERENTIAL DISTORTION
vs
DIFFERENTIAL OUTPUT VOLTAGE
−65
3
Differential Output Voltage − VPP
Differential Output Voltage − VPP
Figure 53
0
HD2
−90
1
Differential Output Voltage − VPP
−95
−70
−85
−90
−75
−65
−80
−85
−70
VCCH = ±15 V
VCCL = ±5 V
HD3
−85
5
Gain =5
Low Bias
Rf = 1 kΩ
RL= 25 Ω
f = 1 MHz
−55
−80
3
100 M
Figure 52
−65
HD3
1
1M
10 M
f − Frequency − Hz
−50
Gain =5
Mid Bias
Rf = 1 kΩ
RL= 25 Ω
f = 1 MHz
−60
−70
VCCH = ±15 V
VCCL = ±15 V
−110
100 k
100 M
Distortion − dBc
VCCH = ±15 V
VCCL = ±5 V
Distortion − dBc
Distortion − dBc
10 M
−50
−60
HD2
−80
−100
DIFFERENTIAL DISTORTION
vs
DIFFERENTIAL OUTPUT VOLTAGE
−50
−55
−70
Figure 51
DIFFERENTIAL DISTORTION
vs
DIFFERENTIAL OUTPUT VOLTAGE
HD3
−60
f − Frequency − Hz
Figure 50
Gain =5
Full Bias
Rf = 1 kΩ
RL= 25 Ω
f = 1 MHz
−50
−90
VCCH = ±15 V
VCCL = ±5 V
−100
f − Frequency − Hz
Distortion − dBc
−40
−60
−70
Gain =5
Full Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 25 Ω
−30
HD3
Distortion − dBc
Distortion − dBc
−40
−20
Gain =5
Low Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 25 Ω
−30
Distortion − dBc
Gain =5
Mid Bias
VO = 2 VPP
Rf = 1 kΩ
RL= 25 Ω
−30
14
DIFFERENTIAL DISTORTION
vs
FREQUENCY
0
5
10 15 20 25 30 35
Differential Output Voltage − VPP
Figure 57
40
0
10
20
30
Differential Output Voltage − VPP
Figure 58
www.BDTIC.com/TI
40
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SLLS543A − SEPTEMBER 2002 − REVISED FEBRUARY 2003
DIFFERENTIAL DISTORTION
vs
DIFFERENTIAL OUTPUT VOLTAGE
DIFFERENTIAL DISTORTION
vs
DIFFERENTIAL OUTPUT VOLTAGE
−50
−75
−60
Gain =10
Full Bias
Rf = 1 kΩ
RL= 25 Ω
f = 1 MHz
−55
−60
Distortion − dBc
−70
HD2
−80
−85
−90
−95
VCCH = ±15 V
VCCL = ±5V
−70
HD2
−65
−70
−75
−80
HD3
0
10
20
30
Differential Output Voltage − VPP
−85
−90
HD3
−95
1
40
3
5
7
9
11
13
15
−100
0
−20
−75
Gain =10
Low Bias
Rf = 1 kΩ
RL= 100 Ω
f = 1 MHz
−65
−70
Distortion − dBc
−70
HD2
−80
−85
−90
−75
VCCH = ±15 V
VCCL = ±5 V
−30
−40
HD2
−80
−85
HD3
−50
Gain =5
Full Bias
Rf = 1 kΩ
RL= 25 Ω
VO = 2VPP
−70
HD2
−80
−90
−90
−95
−100
−100
−100
10
20
30
0
40
10
20
30
40
−110
100 k
Differential Output Voltage − VPP
Differential Output Voltage − VPP
Figure 63
Figure 62
−20
VCCH = ±15 V
VCCL = ±5V
1M
10 M
f − Frequency − Hz
100 M
Figure 64
SINGLE ENDED DISTORTION
vs
FREQUENCY
−30
−40
Distortion − dBc
0
HD3
−60
HD3
−95
40
SINGLE ENDED DISTORTION
vs
FREQUENCY
−60
VCCH = ±15 V
VCCL = ±5V
30
Figure 61
DIFFERENTIAL DISTORTION
vs
DIFFERENTIAL OUTPUT VOLTAGE
−60
20
Differential Output Voltage − VPP
Figure 60
DIFFERENTIAL DISTORTION
vs
DIFFERENTIAL OUTPUT VOLTAGE
−65
10
Differential Output Voltage − VPP
Figure 59
Gain =10
Mid Bias
Rf = 1 kΩ
RL= 100 Ω
f = 1 MHz
HD2
−80
HD3
−90
−105
VCCH = ±15 V
VCCL = ±5V
−75
−85
−100
Gain =10
Full Bias
Rf = 1 kΩ
RL= 100 Ω
f = 1 MHz
−65
Distortion − dBc
Distortion − dBc
VCCH = ±15 V
VCCL = ±15V
Gain =5
Full Bias
Rf = 1 kΩ
RL= 100 Ω
f = 1 MHz
Distortion − dBc
−65
Distortion − dBc
DIFFERENTIAL DISTORTION
vs
DIFFERENTIAL OUTPUT VOLTAGE
−50
Gain =5
Full Bias
Rf = 1 kΩ
RL= 100 Ω
VO = 2VPP
−60
−70
−80
−90
−100
−110
100 k
HD3
HD2
VCCH = ±15 V
VCCL = ±5V
1M
10 M
f − Frequency − Hz
100 M
Figure 65
www.BDTIC.com/TI
15
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
THS6132RGWR
ACTIVE
VQFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS6132RGWRG4
ACTIVE
VQFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS6132VFP
ACTIVE
HLQFP
VFP
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS6132VFPG4
ACTIVE
HLQFP
VFP
32
TBD
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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www.BDTIC.com/TI
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Dec-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
THS6132RGWR
Package Package Pins
Type Drawing
VQFN
RGW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
5.3
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.5
8.0
www.BDTIC.com/TI
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Dec-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS6132RGWR
VQFN
RGW
20
3000
340.5
333.0
20.6
www.BDTIC.com/TI
Pack Materials-Page 2
www.BDTIC.com/TI
www.BDTIC.com/TI
www.BDTIC.com/TI
www.BDTIC.com/TI
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