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Quad, 12-Bit DAC
Voltage Output with Readback
DAC8412/DAC8413
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VLOGIC
DATA
I/O
12
I/O
PORT
DGND
A0
A1
CONTROL
LOGIC
R/W
CS
APPLICATIONS
Automatic test equipment
Digitally controlled calibration
Servo controls
Process control equipment
VDD
VREFH
INPUT
REG A
OUTPUT
REG A
DAC A
VOUTA
INPUT
REG B
OUTPUT
REG B
DAC B
VOUTB
INPUT
REG C
OUTPUT
REG C
DAC C
VOUTC
INPUT
REG D
OUTPUT
REG D
DAC D
VOUTD
RESET
LDAC
00274-001
+5 V to ±15 V operation
Unipolar or bipolar operation
True voltage output
Double-buffered inputs
Reset to minimum (DAC8413) or center scale (DAC8412)
Fast bus access time
Readback
VREFL VSS
Figure 1.
GENERAL DESCRIPTION
The DAC8412/DAC8413 are quad, 12-bit voltage output
DACs with readback capability. Built using a complementary
BiCMOS process, these monolithic DACs offer the user very
high package density.
They can be operated from a wide variety of supply and reference
voltages with supplies ranging from single +5 V to ±15 V, and
references from +2.5 V to ±10 V. Power dissipation is less than
330 mW with ±15 V supplies and only 60 mW with a +5 V supply.
Output voltage swing is set by the two reference inputs VREFH
and VREFL. By setting the VREFL input to 0 V and VREFH to a
positive voltage, the DAC provides a unipolar positive output
range. A similar configuration with VREFH at 0 V and VREFL at a
negative voltage provides a unipolar negative output range.
Bipolar outputs are configured by connecting both VREFH and
VREFL to nonzero voltages. This method of setting output voltage
range has advantages over other bipolar offsetting methods
because it is not dependent on internal and external resistors
with different temperature coefficients.
For MIL-STD-883 applications, contact your local Analog
Devices, Inc. sales office for the DAC8412/DAC8413/883 data
sheet, which specifies operation over the −55°C to +125°C
temperature range. All 883 parts are also available on Standard
Military Drawings 5962-91 76401MXA through 76404M3A.
The DAC8412/DAC8413 are available in 28-lead plastic DIP,
28-lead ceramic DIP, 28-lead PLCC, and 28-lead LCC packages.
+125°C
+25°C
0.250
0.125
0
–55°C
–0.125
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = –55°C, +25°C, +125°C
–0.250
–0.375
–0.500
0
512
1024
1536
2046
2548
2560
DIGITAL INPUT CODE (Decimal)
3072
4096
00274-002
An active low RESET loads all DAC output registers to midscale
for the DAC8412 and zero scale for the DAC8413.
0.375
LINEARITY ERROR (LSB)
Digital controls allow the user to load or read back data from any
DAC, load any DAC, and transfer data to all DACs at one time.
0.500
Figure 2. INL vs. Code Over Temperature
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved.
DAC8412/DAC8413
TABLE OF CONTENTS
Features .............................................................................................. 1
Introduction ................................................................................ 14
Applications ....................................................................................... 1
DACs ............................................................................................ 14
Functional Block Diagram .............................................................. 1
Glitch ............................................................................................ 14
General Description ......................................................................... 1
Reference Inputs ......................................................................... 14
Revision History ............................................................................... 2
Digital I/O ................................................................................... 14
Specifications..................................................................................... 3
Coding ......................................................................................... 14
Electrical Characteristics ............................................................. 3
Supplies ........................................................................................ 15
Absolute Maximum Ratings............................................................ 7
Amplifiers .................................................................................... 15
Thermal Resistance ...................................................................... 7
Reference Configurations.......................................................... 16
ESD Caution .................................................................................. 7
Single +5 V Supply Operation .................................................. 17
Pin Configuration and Function Descriptions ............................. 8
Outline Dimensions ....................................................................... 18
Typical Performance Characteristics ............................................. 9
Ordering Guide .......................................................................... 20
Theory of Operation ...................................................................... 14
REVISION HISTORY
9/09—Rev. E to Rev. F
Updated Figure Numbering .............................................. Universal
Removed Figure 7 ............................................................................. 6
Changes to Ordering Guide .......................................................... 20
6/07—Rev. D to Rev. E
Updated Format .................................................................. Universal
Added CERDIP Package .................................................... Universal
Changes to Specifications Section .................................................. 3
Changes to Absolute Maximum Ratings Section ......................... 7
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 20
3/00—Rev. C to Rev. D
Rev. F | Page 2 of 20
DAC8412/DAC8413
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = +15.0 V, VSS = −15.0 V, VLOGIC = +5.0 V, VREFH = +10.0 V, VREFL = −10.0 V,−40°C ≤ TA ≤ +85°C, unless otherwise noted. 1
Table 1.
Parameter
ACCURACY
Integral Nonlinearity Error
Differential Nonlinearity Error
Min-Scale Error
Full-Scale Error
Min-Scale Temperature Coefficient
Full-Scale Temperature Coefficient
Linearity Matching
REFERENCE
Positive Reference Input Voltage Range 2
Negative Reference Input Voltage Range2
Reference High Input Current
Reference Low Input Current
Large Signal Bandwidth
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
Slew Rate
Analog Crosstalk
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Output High Voltage
Logic Output Low Voltage
Logic Input Current
Input Capacitance
Digital Feedthrough 3
LOGIC TIMING CHARACTERISTICS3, 4
Chip Select Write Pulse Width
Write Setup
Write Hold
Address Setup
Address Hold
Load Setup
Load Hold
Write Data Setup
Write Data Hold
Load Data Pulse Width
Reset Pulse Width
Chip Select Read Pulse Width
Read Data Hold
Read Data Setup
Data to High-Z
Chip Select to Data
Symbol
Conditions
INL
E grade
F grade
Monotonic over temperature
RL = 2 kΩ
RL = 2 kΩ
RL = 2 kΩ
RL = 2 kΩ
Adjacent DAC Matching
DNL
VZSE
VFSE
TCVZSE
TCVFSE
Min
IOUT
tS
SR
RL = 2 kΩ, CL = 100 pF
To 0.01%, 10 V step, RL = 1 kΩ
10% to 90%
–5
VINH
VINL
VOH
VOL
IIN
CIN
TA = 25°C
TA = 25°C
IOH = 0.4 mA
IOL = −1.6 mA
2.4
Rev. F | Page 3 of 20
±0.5
±1
LSB
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB
+1.5
2
160
VDD − 2.5
VREFH − 2.5
+2.75
2.75
V
V
mA
mA
kHz
+5
mA
μs
V/μs
dB
10
2.2
72
0.8
2.4
0.4
1
8
5
VREFH = 2.5 V, VREFL = 0 V
tRCS = 130 ns
tRCS = 130 ns
CL = 10 pF
CL = 100 pF
±0.25
15
20
±1
−3 dB, VREFH = 0 V to 10 V p-p
tWCS = 80 ns
tWCS = 80 ns
Unit
±2
±2
VREFL + 2.5
−10
−2.75
0
tWCS = 80 ns
tWCS = 80 ns
Max
−1
IREFH
IREFL
BW
tWCS
tWS
tWH
tAS
tAH
tLS
tLH
tWDS
tWDH
tLDW
tRESET
tRCS
tRDH
tRDS
tDZ
tCSD
Typ
80
0
0
0
0
70
30
20
0
170
140
130
0
0
200
160
V
V
V
V
μA
pF
nV-sec
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DAC8412/DAC8413
Parameter
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
Symbol
Conditions
PSS
IDD
ISS
PDISS
14.25 V ≤ VDD ≤ 15.75 V
VREFH = 2.5 V
Min
Typ
−10
8.5
−6.5
Max
Unit
150
12
ppm/V
mA
mA
mW
330
1
All supplies can be varied ±5%, and operation is guaranteed. Device is tested with nominal supplies.
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
All parameters are guaranteed by design.
4
All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
3
VDD = VLOGIC = +5.0 V ± 5%, VSS = 0.0 V, VREFH = +2.5 V, VREFL = 0.0 V, VSS = –5.0 V ± 5%, VREFL = −2.5 V, −40°C ≤ TA ≤ +85°C,
unless otherwise noted. 1
Table 2.
Parameter
ACCURACY
Integral Nonlinearity Error
Symbol
Conditions
INL
E grade
F grade
VSS = 0.0 V, E grade 2
VSS = 0.0 V, F grade2
Monotonic over temperature
VSS = −5.0 V
VSS = −5.0 V
VSS = 0.0 V
VSS = 0.0 V
Min
Differential Nonlinearity Error
Min-Scale Error
Full-Scale Error
Min-Scale Error
Full-Scale Error
Min-Scale Temperature Coefficient
Full-Scale Temperature Coefficient
Linearity Matching
REFERENCE
Positive Reference Input Voltage Range 3
Negative Reference Input Voltage Range
DNL
VZSE
VFSE
VZSE
VFSE
TCVZSE
TCVFSE
Reference High Input Current
Large Signal Bandwidth
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
Slew Rate
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Output High Voltage
Logic Output Low Voltage
Logic Input Current
Input Capacitance
LOGIC TIMING CHARACTERISTICS 4, 5
Chip Select Write Pulse Width
Write Setup
Write Hold
Address Setup
Address Hold
Load Setup
Load Hold
IREFH
BW
VSS = 0.0 V
VSS = −5.0 V
Code 0x000
−3 dB, VREFH = 0 V to 2.5 V p-p
IOUT
tS
SR
RL = 2 kΩ, CL = 100 pF
To 0.01%, 2.5 V step, RL = 1 kΩ
10% to 90%
–1.25
VINH
VINL
VOH
VOL
IIN
CIN
TA = 25°C
TA = 25°C
IOH = 0.4 mA
IOL = −1.6 mA
2.4
Max
Units
±0.5
±1
±2
±2
±4
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
LSB
–1
±4
±4
±8
±8
100
100
±1
Adjacent DAC matching
tWCS
tWS
tWH
tAS
tAH
tLS
tLH
Typ
VREFL + 2.5
0
–2.5
–1.0
Rev. F | Page 4 of 20
V
V
V
mA
kHz
+1.25
mA
μs
V/μs
450
7
2.2
0.8
2.4
0.45
1
8
tWCS = 150 ns
tWCS = 150 ns
VDD − 2.5
VREFH − 2.5
VREFH − 2.5
+1.0
150
0
0
0
0
70
50
V
V
V
V
μA
pF
ns
ns
ns
ns
ns
ns
ns
DAC8412/DAC8413
Parameter
Write Data Setup
Write Data Hold
Load Data Pulse Width
Reset Pulse Width
Chip Select Read Pulse Width
Read Data Hold
Read Data Setup
Data to High-Z
Chip Select to Data
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
Symbol
tWDS
tWDH
tLDW
tRESET
tRCS
tRDH
tRDS
tDZ
tCSD
PSS
IDD
ISS
PDISS
Conditions
tWCS = 150 ns
tWCS = 150 ns
Min
20
0
180
150
170
20
0
tRCS = 170 ns
tRCS = 170 ns
CL = 10 pF
CL = 100 pF
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
320
100
7
VSS = −5.0 V
VSS = 0 V
VSS = −5.0 V
ppm/V
mA
mA
mW
mW
12
−10
60
110
1
All supplies can be varied ±5%, and operation is guaranteed. Device is tested with VDD = 4.75 V.
For single-supply operation only (VREFL = 0.0 V, VSS = 0.0 V). Due to internal offset errors, INL and DNL are measured beginning at 0x005.
3
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
4
All parameters are guaranteed by design.
5
All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
tWCS
CS
tWS
tWH
tAS
tAH
tLS
tLH
R/W
tRDS
A0/A1
CS
tRDH
tRCS
R/W
tAS
tLDW
LDAC
tAH
tWDS
A0/A1
tWDH
DATA IN
DATA VALID
HIGH-Z
tCSD
tRESET
00274-003
HIGH-Z
RESET
Figure 4. Data Write (Input and Output Registers) Timing
Figure 3. Data Output (Read Timing)
Rev. F | Page 5 of 20
00274-004
tDZ
DATA
OUT
DAC8412/DAC8413
80ns
80ns
CS
CS
tWH
tWS
R/W
R/W
tAS
ADDRESS
ONE
tAS
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
ADDRESS
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
tLS
tLH
tLS
LDAC
tLH
DATA1
VALID
tWDH
DATA2
VALID
DATA3
VALID
DATA4
VALID
00274-005
LDAC
tWDS
DATA IN
ADDRESS
ONE
tLDW
tWDS
DATA IN
Figure 5. Single-Buffer Mode
DATA1
VALID
DATA2
VALID
DATA3
VALID
Figure 6. Double-Buffer Mode
Rev. F | Page 6 of 20
DATA4
VALID
tWDH
00274-006
ADDRESS
tWH
tWS
DAC8412/DAC8413
ABSOLUTE MAXIMUM RATINGS
TA = +25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 3.
θJA is specified for the worst-case mounting conditions, that is, a
device in socket.
Parameter
VSS to VDD
VSS to VLOGIC
VLOGIC to DGND
VSS to VREFL
VREFH to VDD
VREFH to VREFL
Current into Any VSS pin
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature Range
EP, FP, FPC
AT, BT, BTC
Junction Temperature
Storage Temperature Range
Power Dissipation Package
Lead Temperature
Soldering
Rating
−0.3 V, +33.0 V
−0.3 V, +33.0 V
−0.3 V, +7.0 V
−0.3 V, +VSS − 2.0 V
+2.0 V, +33.0 V
+2.0 V, VSS − VDD
±15 mA
−0.3 V, VLOGIC + 0.3 V
−0.3 V, +7.0 V
Table 4. Thermal Resistance
Package Type
28-Lead Plastic DIP (PDIP)
28-Terminal Ceramic Leadless Chip Carrier (LLC)
28-Lead Plastic Leaded Chip Carrier (PLLC)
28-Lead Ceramic Dual In-Line Package (CERDIP)
ESD CAUTION
−40°C to +85°C
−55°C to +125°C
150°C
−65°C to +150°C
1000 mW
JEDEC Industry Standard
J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. F | Page 7 of 20
θJA
48
70
63
51
θJC
22
28
25
9
Unit
°C/W
°C/W
°C/W
°C/W
DAC8412/DAC8413
R/W
DB2 10
19
DB11 (MSB)
DB3 11
18
DB10
DB4 12
17
DB9
DB5 13
16
DB8
DB6 14
15
DB7
DB1
7
DAC8412/
DAC8413
8
9
Figure 7. PDIP/CERDIP
14
15
16
17
18
DB7
DB8
DB9
DB10
13
DB6
00274-008
DB3 11
12
VDD
24
VLOGIC
23
CS
LDAC 7
A0
DB0 (LSB) 8
22
TOP VIEW
(Not to Scale)
DB2 10
25
21
A1
20
R/W
19
DB11 (MSB)
Figure 8. PLCC
VOUTD
VREFH
PIN 1
INDENTFIER
VOUTC
VOUTB
1
VREFL
VOUTA
2
28 27 26
DGND 5
25 VDD
RESET 6
24 VLOGIC
DAC8412/
DAC8413
23 CS
22 A0
TOP VIEW
(Not to Scale)
DB1 9
21 A1
DB2 10
20 R/W
DB3 11
19 DB11 (MSB)
12 13 14 15 16 17 18
00274-010
20
3
DB10
DB1 9
4
DB9
DB0 (LSB)
26
DB8
TOP VIEW 22 A0
DB0 (LSB) 8 (Not to Scale) 21 A1
27
DB7
LDAC
LDAC 7
28
DB6
CS
1
DB5
23
5
2
DB4
RESET 6
DGND
RESET 6
VSS
VLOGIC
DAC8412/
DAC8413
3
DB5
24
DGND 5
4
DB4
VDD
00274-009
25
VOUTD
VOUTD
VSS 4
VOUTC
26
VREFL
VOUTC
VOUTA 3
VREFH
VREFL
27
VOUTB
28
VOUTA
VREFH 1
VOUTB 2
VSS
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 9. LCC
Table 5. Pin Function Descriptions
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Mnemonic
VREFH
VOUTB
VOUTA
VSS
DGND
RESET
LDAC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
R/W
A1
A0
CS
VLOGIC
VDD
VOUTD
VOUTC
VREFL
Description
High-Side DAC Reference Input.
DAC B Output.
DAC A Output.
Lower Rail Power Supply.
Digital Ground.
Reset Input and Output Registers to all 0s, Enabled at Active Low.
Load Data to DAC, Enabled at Active Low.
Data Bit 0, LSB.
Data Bit 1.
Data Bit 2.
Data Bit 3.
Data Bit 4.
Data Bit 5.
Data Bit 6.
Data Bit 7.
Data Bit 8.
Data Bit 9.
Data Bit 10.
Data Bit 11, MSB.
Active Low to Write Data to DAC. Active high to readback previous data at data bit pins with VLOGIC connected to 5 V.
Address Bit 1.
Address Bit 0.
Chip Select, Enabled at Active Low.
Voltage Supply for Readback Function. Can be open circuit if not used.
Upper Rail Power Supply.
DAC D Output.
DAC C Output.
Low-Side DAC Reference Input.
Rev. F | Page 8 of 20
DAC8412/DAC8413
–1
6
7
8
9
10
VREFH (V)
11
1
0
–1
–2
12
1
MAXIMUM LINEARITY ERROR (LSB)
0
VDD = 5V
VSS = 0V
VREFL = 0V
TA = 25°C
2
VREFH (V)
0.3
0.2
3
6
8
10
12
VREFH (V)
Figure 14. INL vs.VREFH
Figure 11. INL vs. VREFH
0.4
0.3
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
X+3σ
0.1
ZERO-SCALE ERROR (LSB)
0.2
0
X+3σ
–0.2
X
–0.4
X
–0.1
X–3σ
–0.3
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
–0.5
0
200
400
600
800
T = HOURS OF OPERATION AT 125°C
1000
–0.7
Figure 12. Full-Scale Error vs. Time Accelerated by Burn-in
0
200
400
600
800
T = HOURS OF OPERATION AT 125°C
1000
Figure 15. Zero-Scale Error vs. Time Accelerated by Burn-In
Rev. F | Page 9 of 20
00274-016
X–3σ
–0.6
00274-015
FULL-SCALE ERROR (LSB)
VDD = +15V
VSS = –15V
VREFL = 0V
TA = 25°C
0.1
00274-014
MAXIMUM LINEARITY ERROR (LSB)
1
1
3
Figure 13. DNL vs. VREFH
Figure 10. DNL vs. VREFH
–1
2
VREFH (V)
00274-012
0
VDD = 5V
VSS = 0V
VREFL = 0V
TA = 25°C
2
00274-013
1
MAXIMUM LINEARITY ERROR (LSB)
VDD = +15V
VSS = –15V
VREFL = –10V
TA = 25°C
00274-011
MAXIMUM LINEARITY ERROR (LSB)
TYPICAL PERFORMANCE CHARACTERISTICS
DAC8412/DAC8413
1.00
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
0
–0.2
VDD = 5V
VSS = 0V
VREFH = 2.5V
TA = 25°C
0.75
LINEARITY ERROR (LSB)
FULL-SCALE ERROR (LSB)
0.2
DAC A
DAC D
DAC B
–0.4
DAC C
0.50
0.25
0
–0.25
–0.50
0
75
TEMPERATURE (°C)
150
–1.00
Figure 16. Full-Scale Error vs. Temperature
1024
1536
2048 2560
3072
DIGITAL INPUT CODE (Decimal)
3584
4096
13
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
0
VDD = +15V
VSS = –15V
VREFL = –10V
10
–0.2
IDD (mA)
DAC A
DAC C
DAC D
150
4
00274-018
0
75
TEMPERATURE (°C)
7
3
5
9
13
VREFH (V)
Figure 17. Zero-Scale Error vs. Temperature
Figure 20. IDD vs. VREFH (All DACs High)
0.37500
0.500
VREFH = 10V
VREFL = 0V
TA = 25°C
0.375
LINEARITY ERROR (LSB)
0.18750
0.08375
0
–0.09375
–0.18750
–0.23125
0.250
0.125
0
–0.125
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = –55°C, +25°C, +125°C
–0.250
0
512
1024
1536
2048
2560
3072
DIGITAL INPUT CODE (Decimal)
3584
4096
00274-019
–0.375
Figure 18. Channel-to-Channel Matching (VSUPPLY = ±15 V)
–0.500
0
512
1024
1536
2048
2560
3072
DIGITAL INPUT CODE (Decimal)
Figure 21. INL vs. Code
Rev. F | Page 10 of 20
3584
4096
00274-022
0.26125
–0.37500
1
00274-021
7
DAC B
–0.4
–0.6
–75
LINEARITY ERROR (LSB)
512
Figure 19. Channel-to-Channel Matching (VSUPPLY = +5 V/GND)
0.2
ZERO-SCALE ERROR (LSB)
0
00274-020
–0.6
–75
00274-017
–0.75
DAC8412/DAC8413
10V
1V/DIV
EA
1V/DIV
EA
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = 25°C
0V
–580ns
1µs/DIV
TRIG'D
9.42µs
00274-026
TRIG'D
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = 25°C
0V
–580ns
1µs/DIV
Figure 22. Positive Slew Rate
9.42µs
00274-027
10V
Figure 25. Negative Slew Rate
15.5mV
2.0
VDD = +15V
VSS = –15V
VREFH = +10V
1.5 VREFL = –10V
TA = 25°C
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = 25°C
0
INPUT
–5V
IVREFH (mA)
2mV/DIV
5V/DIV
TRIG'D
1.0
0.5
18.04µs
–0.5
0
511
1023
1535
2047
2559
3071
DIGITAL INPUT CODE (Decimal)
100
1.0
32.5mV
5V
INPUT
0
0.8
0.6
INL (LSB)
1 LSB ERROR BAND
5V/DIV
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = 25°C
2µs/DIV
18.04µs
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = 25°C
0.4
0.2
0
00274-024
TRIG'D
–17.5mV
–1.96µs
4095
Figure 26. IVREFH vs. Code
Figure 23. Settling Time (Negative)
5mV/DIV
3583
00274-023
2µs/DIV
00274-028
–4.5mV
–1.96µs
00274-025
0
–0.2
0.01
0.1
1
LOAD RESISTANCE (kΩ)
10
Figure 27. INL vs. Load Resistance
Figure 24. Settling Time (Positive)
Rev. F | Page 11 of 20
DAC8412/DAC8413
12
100
8
6
4
2
0.1
1
LOAD RESISTANCE (kΩ)
10
100
–PSRR
60
+PSRR:
VDD = +15V ±1Vp
VSS = –15V
40
–PSRR:
VDD = +15V
VSS = –15V ±1V
VREFH = +10V
ALL DATA 0
20
0
10
00274-029
0
0.01
+PSRR
80
100
Figure 28. Output Swing vs. Load Resistance
1k
10k
FREQUENCY (Hz)
100k
1M
00274-032
FULL-SCALE VOLTAGE (V)
10
POWER SUPPLY REJECTION RATIO (dB)
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = 25°C
Figure 31. PSRR vs. Frequency
10
1
NOISE DENSITY (µV)
–10
–30
VDD = +15V
VSS = –15V
VREFH = 0 ±100mV
VREFL = –10V
DATA BITS = +5V
200mV p-p
0
10
100
0.10
0.01
1k
10k
FREQUENCY (Hz)
100k
1M
10M
0.001
1
10
40
IDD
30
6
20
VDD = +15V
VSS = –15V
1k
10k
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = 25°C
DATA = 0x000
+ISC
10
IOUT (mA)
2
–2
0
–10
ISS
–20
–ISC
–10
–75
0
75
TEMPERATURE (°C)
150
–40
–25
Figure 30. Power Supply Current vs. Temperature
–20
–15
–10
–5
0
5
VOUT (V)
Figure 33. IOUT vs. VOUT
Rev. F | Page 12 of 20
10
15
20
25
00274-034
–30
00274-031
POWER SUPPLY CURRENT (mA)
100
NOISE FREQUENCY (Hz)
Figure 32. Noise Density vs. Noise Frequency
Figure 29. Small Signal Response
–6
10
00274-033
–50
00274-030
GAIN (dB)
0
–70
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = 25°C
DAC8412/DAC8413
10µs
CH1 MEAN
66.19µV
4µs
1V
GLITCH AT DAC OUTPUT
1
2
M 200µs
A CH1
12.9mV
DEGLITCHER OUTPUT
1V
CH2
Figure 34. Broadband Noise
Figure 36. Glitch and Deglitched Results
25
20
15
+ISC
5
0
–5
–10
–15
–ISC
–20
–25
–6
–4
–2
0
VOUT (V)
2
4
6
00274-036
IOUT (mA)
10
VDD = +15V
VSS = 0V
VREFH = +10V
VREFL = 0V
TA = 25°C
DATA = 0x800
Figure 35. IOUT vs. VOUT
Rev. F | Page 13 of 20
1.86V
00274-037
20µV/DIV
1
00274-035
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = 25°C
DAC8412/DAC8413
THEORY OF OPERATION
INTRODUCTION
REFERENCE INPUTS
The DAC8412/DAC8413 are quad, voltage output, 12-bit parallel
input DACs featuring a 12-bit data bus with readback capability.
The only differences between the DAC8412/DAC8413 are the
reset functions. The DAC8412 resets to midscale (Code 0x800),
and the DAC8413 resets to minimum scale (Code 0x000).
All four DACs share common reference high (VREFH) and reference
low (VREFL) inputs. The voltages applied to these reference inputs set
the output high and low voltage limits of all four of the DACs.
Each reference input has voltage restrictions with respect to the
other reference and to the power supplies. The VREFL can be set at
any voltage between VSS and VREFH − 2.5 V, and VREFH can be set to
any value between +VDD − 2.5 V and VREFL + 2.5 V. Note that
because of these restrictions, the DAC8412 references cannot be
inverted (that is, VREFL cannot be greater than VREFH).
The ability to operate from a single 5 V supply is a unique
feature of these DACs.
Operation of the DAC8412/DAC8413 can be viewed by
dividing the system into three separate functional groups: the
digital I/O and logic, the digital-to-analog converters, and the
output amplifiers.
DACS
Each DAC is a voltage switched, high impedance (R = 50 kΩ),
R-2R ladder configuration. Each 2R resistor is driven by a pair
of switches that connect the resistor to either VREFH or VREFL.
GLITCH
Worst-case glitch occurs at the transition between Half-Scale
Digital Code 1000 0000 0000 to half-scale minus 1 LSB, 0111
1111 1111. It can be measured at about 2 V μs (see Figure 36).
For demanding applications such as waveform generation or
precision instrumentation control, a deglitcher circuit can be
implemented with a standard sample-and-hold circuit (see
Figure 37). When CS is enabled by synchronizing the hold
period to be longer than the glitch tradition, the output voltage
can be smoothed with minimum disturbance. A quad
sample-and-hold amplifier, SMP04, has been used to illustrate
the deglitching result (see Figure 36).
DACOUT
DACOUT 1
S/H
DACOUT
CS
S/H
H
S
H
Figure 37. Data Output (Read Timing)
It is recommended that the reference inputs be bypassed with
0.2 μF capacitors when operating with ±10 V references. This
limits the reference bandwidth.
DIGITAL I/O
See Table 6 for the digital control logic truth table. Digital I/O
consists of a 12-bit bidirectional data bus, two registers select
inputs, A0 and A1, a R/W input, a RESET input, a chip select (CS),
and a load DAC (LDAC) input. Control of the DACs and bus
direction is determined by these inputs as shown in Table 6. Digital
data bits are labeled with the MSB defined as Data Bit 11 and the
LSB as Data Bit 0. All digital pins are TTL/CMOS compatible.
See Figure 38 for a simplified I/O logic diagram. The register
select inputs A0 and A1 select individual DAC registers A
(Binary Code 00) through D (Binary Code 11). Decoding of the
registers is enabled by the CS input. When CS is high, no
decoding takes place, and neither the writing nor the reading of
the input registers is enabled. The loading of the second bank of
registers is controlled by the asynchronous LDAC input. By
taking LDAC low while CS is enabled, all output registers can
be updated simultaneously. Note that the tLDW required pulse
width for updating all DACs is a minimum of 170 ns.
The R/W input, when enabled by CS, controls the writing to
and reading from the input register.
S
00274-038
DACOUT 1
It is important to note that the DAC8412 VREFH input both sinks
and sources current. In addition, the input current of both VREFH
and VREFL are code-dependent. Many references have limited
current-sinking capability and must be buffered with an
amplifier to drive VREFH. The VREFL has no such special
requirements.
CODING
Both DAC8412/DAC8413 use binary coding. The output
voltage can be calculated by
VOUT = VREFL +
(VREFH − VREFL ) × N
4096
where N is the digital code in decimal.
Rev. F | Page 14 of 20
DAC8412/DAC8413
RESET
The RESET function can be used either at power-up or at any
time during DAC operation. The RESET function is independent
of CS. This pin is active low and sets the DAC output registers
to either center code for the DAC8412, or zero code for the
DAC8413. The reset-to-center code is most useful when the
DAC is configured for bipolar references and an output of 0 V
after reset is desired.
SUPPLIES
Supplies required are VSS, VDD, and VLOGIC. The VSS supply can
be set between −15 V and 0 V. VDD is the positive supply; its
operating range is between 5 V and 15 V.
VLOGIC is the digital output supply voltage for the readback
function. It is normally connected to +5 V. This pin is a logic
reference input only. It does not supply current to the device. If
the readback function is not being used, VLOGIC can be left opencircuit. While VLOGIC does not supply current to the DAC8412, it
does supply currents to the digital outputs when readback is used.
AMPLIFIERS
Unlike many voltage output DACs, the DAC8412 features buffered
voltage outputs. Each output is capable of both sourcing and
sinking 5 mA at ±10 V, eliminating the need for external
amplifiers when driving 500 pF or smaller capacitive load in
most applications. These amplifiers are short-circuit protected.
Table 6. DAC8412/DAC8413 Logic Table
A1
L
L
H
H
L
L
H
H
L
L
H
H
X
X
X
X
1
A0
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
R/W
CS
RS
LDAC
L
L
L
L
L
L
L
L
H
H
H
H
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
X
X
Input Register
Output Register
Write
Write
Write
Write
Write
Write
Write
Write
Write
Hold
Write
Hold
Write
Hold
Write
Hold
Read
Hold
Read
Hold
Read
Hold
Read
Hold
Hold
Update all output registers
Hold
Hold
All registers reset to midscale/zero-scale 1
All registers latched to midscale/zero-scale1
Mode
Transparent
Transparent
Transparent
Transparent
Write input
Write input
Write input
Write input
Read input
Read input
Read input
Read input
Hold
DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = logic low; H = logic high; X = don’t care. Input and output registers are transparent when asserted.
Rev. F | Page 15 of 20
DAC
A
B
C
D
A
B
C
D
A
B
C
D
All
All
All
All
DAC8412/DAC8413
VREFH
RDDACA
CS
DAC A
VOUTA
WRDB2
WRDB3
A0
RDDACB
A1
WRDACB WRDB5
INPUT
OUTPUT
REGISTER WRDB6 REGISTER
RDDACC
WRDB7
DAC B
WRDB4
WRDACC
R/W
VSS
WRDB0
WRDB1
WRDACA
VDD
VOUTB
DAC C
VOUTC
WRDB8
WRDB9
RDDACD
WRDB10
DAC D
WRDB11
VOUTD
WRDACD
DB11..DB0
VLOGIC
VREFL
LDAC
RESET
READOUTBAR
READBACKDATAIN_DB11
READBACKDATAIN_DB10
READBACK
DATAOUT_DB11
00274-039
READOUT
DGND
Figure 38. Simplified I/O Logic Diagram
+15V
REFERENCE CONFIGURATIONS
39kΩ
GAIN
100kΩ
0.2µF
REF10
TRIM
OR
10kΩ
VREFL
+10V OPERATION
DAC8413
–15V
VREFL
VSS
Figure 40. Symmetrical Bipolar Operation
0.1µF
//10µF
VSS
Figure 39. Unipolar +10 V Operation
0.1µF
//10µF
–15V
±5 OR ±10V OPERATION
VDD
DAC8412
OR
DAC8413
1µF
00274-040
OP400
OUTPUT
DAC8412
6.2Ω
+15V
VREFH
VDD
VREFH
0.2µF
AD688 FOR ±10V
AD588 FOR ±5V
0.2µF
+
INPUT
6.2Ω
BALANCE
100kΩ
Output voltage ranges can be configured as either unipolar or
bipolar, and within these choices, a wide variety of options
exists. The unipolar configuration can be either positive or
negative voltage output, and the bipolar configuration can be
either symmetrical or nonsymmetrical.
+15V
+15V
00274-041
Careful attention to grounding is important for accurate
operation of the DAC8412. This is not because the DAC8412 is
more sensitive than other 12-bit DACs, but because with four
outputs and two references, there is greater potential for ground
loops. Because the DAC8412 has no analog ground, the ground
must be specified with respect to the reference.
Figure 40 (symmetrical bipolar operation) shows the DAC8412
configured for ±10 V operation. See the AD688 data sheet for a
full explanation of reference operation. Adjustments may not be
required for many applications since the AD688 is a very high
accuracy reference. However, if additional adjustments are
required, adjust the DAC8412 full scale first. Begin by loading
the digital full-scale code (0xFFF), and then adjust the gain
adjust potentiometer to attain a DAC output voltage of 9.9976 V.
Then, adjust the balance adjust to set the center-scale output
voltage to 0.000 V.
Rev. F | Page 16 of 20
DAC8412/DAC8413
The 0.2 μF bypass capacitors shown at the reference inputs in
Figure 40 should be used whenever ±10 V references are used.
Applications with single references or references to ±5 V may
not require the 0.2 μF bypassing. The 6.2 Ω resistor in series
with the output of the reference amplifier keeps the amplifier
from oscillating with the capacitive load. This 6.2 Ω resistor has
been found to be large enough to stabilize this circuit. Larger
resistor values are acceptable, provided that the drop across the
resistor does not exceed VBE. Assuming a minimum VBE of 0.6 V
and a maximum current of 2.75 mA, then the resistor should be
under 200 Ω for the loading of a single DAC8412.
Using two separate references is not recommended. Having two
references can cause different drifts with time and temperature;
whereas with a single reference, most drifts track.
Figure 41 shows the DAC8412 configured for –10 V to 0 V
operation. A REF08 with a –10 V output is connected directly
to VREFL for the reference voltage.
SINGLE +5 V SUPPLY OPERATION
For operation with a 5 V supply, the reference voltage should be
set between 1.0 V and 2.5 V for optimum linearity. Figure 42
shows a REF43 used to supply a 2.5 V reference voltage. The
headroom of the reference and DAC are both sufficient to support
a 5 V supply with ±5% tolerance. VDD and VLOGIC should be
connected to the same supply. Separate bypassing to each pin
should also be used.
Unipolar positive full-scale operation can usually be set with a
reference with the correct output voltage. This is preferable to
using a reference and dividing down to the required value. For a
10 V full-scale output, the circuit can be configured as shown in
Figure 41. In this configuration, the full-scale value is set first by
adjusting the 10 kΩ resistor for a full-scale output of 9.9976 V.
5V
10µF
0.01µF
INPUT
VREFH
OUTPUT
REF43
TRIM
GND
0.2µF
10kΩ
VREFL
0.1µF
//10µF
DAC8413
VREFH
OUTPUT
DAC8412
OR
0.2µF
0.01µF
VREFL
ZERO TO 2.5V OPERATION
SINGLE 5V SUPPLY
VDD
Figure 42. +5 V Single-Supply Operation
0.1µF
//10µF
DAC8413
VSS
ZERO TO –10V OPERATION
–15V
00274-042
10µF
Figure 41. Unipolar –10 V Operation
Rev. F | Page 17 of 20
00274-043
VSS
TRIM
REF08
DAC8412
OR
10kΩ
GND
VDD
DAC8412/DAC8413
OUTLINE DIMENSIONS
0.300 (7.62)
REF
0.075
(1.91)
REF
0.020 (0.51)
MIN
19
26
18
0.458 (11.63)
SQ
0.442 (11.23)
0.458
(11.63)
MAX
SQ
0.028 (0.71)
0.022 (0.56)
25
0.05 (1.27)
BOTTON
VIEW
28
1
0.15 (3.81)
REF
0.075 (1.91)
REF
12
11
4
5
0.095 (2.41)
0.075 (1.90)
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
022106-A
0.100 (2.54)
0.064 (1.63)
Figure 43. 28-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-28-1)
Dimensions shown in inches and (millimeters)
1.565 (39.75)
1.380 (35.05)
28
15
0.580 (14.73)
0.485 (12.31)
1
14
0.625 (15.88)
0.600 (15.24)
0.100 (2.54)
BSC
0.250 (6.35)
MAX
0.195 (4.95)
0.125 (3.17)
0.015 (0.38)
GAUGE
PLANE
0.015
(0.38)
MIN
0.200 (5.08)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.014 (0.36)
0.005 (0.13)
MIN
0.700 (17.78)
MAX
0.015 (0.38)
0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MS-011
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS.
Figure 44. 28-Lead Plastic Dual In-Line Package [PDIP]
Wide Body
(N-28-2)
Dimensions shown in inches and (millimeters)
Rev. F | Page 18 of 20
071006-A
0.070 (1.78)
0.050 (1.27)
DAC8412/DAC8413
0.180 (4.57)
0.165 (4.19)
0.048 (1.22)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
4
0.048 (1.22)
0.042 (1.07)
5
PIN 1
IDENTIFIER
26
25
0.021 (0.53)
0.013 (0.33)
0.050
(1.27)
BSC
TOP VIEW
(PINS DOWN)
11
12
0.020 (0.51)
MIN
0.032 (0.81)
0.026 (0.66)
19
18
0.456 (11.582)
SQ
0.450 (11.430)
0.120 (3.04)
0.090 (2.29)
0.495 (12.57)
SQ
0.485 (12.32)
0.430 (10.92)
0.390 (9.91)
BOTTOM
VIEW
(PINS UP)
0.045 (1.14)
R
0.025 (0.64)
042508-A
COMPLIANT TO JEDEC STANDARDS MO-047-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 45. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28)
Dimensions shown in inches and (millimeters)
0.005 (0.13)
MIN
0.100 (2.54)
MAX
28
15
0.610 (15.49)
0.500 (12.70)
1
14
PIN 1
1.490 (37.85) MAX
0.620 (15.75)
0.590 (14.99)
0.015 (0.38)
MIN
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.026 (0.66)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78) SEATING
0.030 (0.76) PLANE
15°
0°
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 46. 28-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-28-2)
Dimensions shown in inches and (millimeters)
Rev. F | Page 19 of 20
0.018 (0.46)
0.008 (0.20)
030106-A
0.225(5.72)
MAX
DAC8412/DAC8413
ORDERING GUIDE
Model
DAC8412AT/883C
DAC8412BT/883C
DAC8412BTC/883C
DAC8412EP 1
DAC8412EPZ1, 2
DAC8412FP1
DAC8412FPC1
DAC8412FPC-REEL1
DAC8412FPCZ1, 2
DAC8412FPCZ-REEL1, 2
DAC8412FPZ1, 2
DAC8413AT/883C
DAC8413BT/883C
DAC8413BTC/883C
DAC8413EP1
DAC8413EPZ1, 2
DAC8413FP1
DAC8413FPC1
DAC8413FPC-REEL1
DAC8413FPCZ1, 2
DAC8413FPC-REEL1
DAC8413FPZ1, 2
1
2
Temperature Range
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
INL
±0.75
±1.5
±1.5
±0.5
±0.5
±1
±1
±1
±1
±1
±1
±0.75
±1.5
±1.5
±0.5
±0.5
±1
±1
±1
±1
±1
±1
Package Description
28-Lead Ceramic Dual In-Line Package [CERDIP]
28-Lead Ceramic Dual In-Line Package [CERDIP]
28-Terminal Ceramic Leadless Chip Carrier [LCC]
28-Lead Plastic Dual In-Line Package [PDIP]
28-Lead Plastic Dual In-Line Package [PDIP]
28-Lead Plastic Dual In-Line Package [PDIP]
28-Lead Plastic Leaded Chip Carrier [PLCC]
28-Lead Plastic Leaded Chip Carrier [PLCC]
28-Lead Plastic Leaded Chip Carrier [PLCC]
28-Lead Plastic Leaded Chip Carrier [PLCC]
28-Lead Plastic Dual In-Line Package [PDIP]
28-Lead Ceramic Dual In-Line Package [CERDIP]
28-Lead Ceramic Dual In-Line Package [CERDIP]
28-Terminal Ceramic Leadless Chip Carrier [LCC]
28-Lead Plastic Dual In-Line Package [PDIP]
28-Lead Plastic Dual In-Line Package [PDIP]
28-Lead Plastic Dual In-Line Package [PDIP]
28-Lead Plastic Leaded Chip Carrier [PLCC]
28-Lead Plastic Leaded Chip Carrier [PLCC]
28-Lead Plastic Leaded Chip Carrier [PLCC]
28-Lead Plastic Dual In-Line Package [PDIP]
28-Lead Plastic Dual In-Line Package [PDIP]
If burn-in is required, these models are available in CERDIP. Contact sales.
Z = RoHS Compliant Part.
©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00274-0-9/09(F)
Rev. F | Page 20 of 20
Package Option
Q-28-2
Q-28-2
E-28-1
N-28-2
N-28-2
N-28-2
P-28
P-28
P-28
P-28
N-28-2
Q-28-2
Q-28-2
E-28-1
N-28-2
N-28-2
N-28-2
P-28
P-28
P-28
N-28-2
N-28-2