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8-Bit, 125 MSPS, Dual TxDAC+
Digital-to-Analog Converter
AD9709
FUNCTIONAL BLOCK DIAGRAM
8-bit dual transmit digital-to-analog converter (DAC)
125 MSPS update rate
Excellent SFDR to Nyquist @ 5 MHz output: 66 dBc
Excellent gain and offset matching: 0.1%
Fully independent or single-resistor gain control
Dual port or interleaved data
On-chip 1.2 V reference
Single 5 V or 3.3 V supply operation
Power dissipation: 380 mW @ 5 V
Power-down mode: 50 mW @ 5 V
48-lead LQFP
DVDD1/ DCOM1/
DVDD2 DCOM2 AVDD
1
LATCH
PORT1
WRT1/IQWRT
WRT2/IQSEL
ACOM
DIGITAL
INTERFACE
MODE
APPLICATIONS
1
DAC
IOUTA1
IOUTB1
REFERENCE
REFIO
FSADJ1
FSADJ2
GAINCTRL
BIAS
GENERATOR
SLEEP
AD9709
2
LATCH
PORT2
CLK1
2
DAC
IOUTA2
IOUTB2
CLK2/IQ RESET
00606-001
FEATURES
Figure 1.
Communications
Base stations
Digital synthesis
Quadrature modulation
3D ultrasound
GENERAL DESCRIPTION
1
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The AD9709 is a dual-port, high speed, 2-channel, 8-bit CMOS
DAC. It integrates two high quality 8-bit TxDAC+® cores, a voltage
reference, and digital interface circuitry into a small 48-lead LQFP
package. The AD9709 offers exceptional ac and dc performance
while supporting update rates of up to 125 MSPS.
The AD9709 has been optimized for processing I and Q data in
communications applications. The digital interface consists of two
double-buffered latches as well as control logic. Separate write
inputs allow data to be written to the two DAC ports independent
of one another. Separate clocks control the update rate of the DACs.
A mode control pin allows the AD9709 to interface to two separate
data ports, or to a single interleaved high speed data port. In interleaving mode, the input data stream is demuxed into its original
I and Q data and then latched. The I and Q data is then converted
by the two DACs and updated at half the input data rate.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set
independently using two external resistors, or IOUTFS for both
DACs can be set by using a single external resistor. See the Gain
Control Mode section for important date code information on
this feature.
The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce
1
glitch energy and to maximize dynamic accuracy. Each DAC
provides differential current output, thus supporting singleended or differential applications. Both DACs can be
simultaneously updated and provide a nominal full-scale
current of 20 mA. The full-scale currents between each DAC
are matched to within 0.1%.
The AD9709 is manufactured on an advanced low-cost CMOS
process. It operates from a single supply of 3.3 V or 5 V and
consumes 380 mW of power.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
The AD9709 is a member of a pin-compatible family of
dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution.
Dual 8-Bit, 125 MSPS DACs. A pair of high performance
DACs optimized for low distortion performance provide
for flexible transmission of I and Q information.
Matching. Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.
Low Power. Complete CMOS dual DAC function operates
at 380 mW from a 3.3 V or 5 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
On-Chip Voltage Reference. The AD9709 includes a 1.20 V
temperature-compensated band gap voltage reference.
Dual 8-Bit Inputs. The AD9709 features a flexible dualport interface, allowing dual or interleaved input data.
Patent pending.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2008 Analog Devices, Inc. All rights reserved.
AD9709
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Outputs .......................................................................... 14
Applications....................................................................................... 1
Digital Inputs .............................................................................. 15
Functional Block Diagram .............................................................. 1
DAC Timing................................................................................ 15
General Description ......................................................................... 1
Sleep Mode Operation............................................................... 18
Product Highlights ........................................................................... 1
Power Dissipation....................................................................... 18
Revision History ............................................................................... 2
Applying the AD9709 .................................................................... 19
Specifications..................................................................................... 3
Output Configurations .............................................................. 19
DC Specifications ......................................................................... 3
Differential Coupling Using a Transformer............................ 19
Dynamic Specifications ............................................................... 4
Differential Coupling Using an Op Amp................................ 19
Digital Specifications ................................................................... 5
Single-Ended, Unbuffered Voltage Output............................. 20
Absolute Maximum Ratings............................................................ 6
Single-Ended, Buffered Voltage Output Configuration........ 20
Thermal Resistance ...................................................................... 6
Power and Grounding Considerations.................................... 20
ESD Caution.................................................................................. 6
Applications..................................................................................... 22
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Quadrature Amplitude Modulation (QAM)
Using the AD9709 ...................................................................... 22
Terminology .................................................................................... 11
CDMA ......................................................................................... 23
Theory of Operation ...................................................................... 12
Evaluation Board ............................................................................ 24
Functional Description.............................................................. 12
General Description................................................................... 24
Reference Operation .................................................................. 13
Schematics................................................................................... 24
Gain Control Mode .................................................................... 13
Evaluation Board Layout........................................................... 27
Setting the Full-Scale Current................................................... 13
Outline Dimensions ....................................................................... 30
DAC Transfer Function ............................................................. 14
Ordering Guide............................................................................... 30
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REVISION HISTORY
1/08—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changed Single Supply Operation to 5 V or 3.3 V ........Universal
Changes to Figure 1.......................................................................... 1
Added Timing Diagram Section .................................................... 5
Changes to Figure 3 and Table 6..................................................... 7
Change to Figure 12 ......................................................................... 9
Changes to Figure 18 to Figure 20................................................ 10
Changes to Functional Description Section ............................... 13
Changes to Reference Operation Section.................................... 13
Changes to Figure 23 and Figure 24............................................. 13
Changes to Gain Control Mode Section...................................... 13
Replaced Reference Control Amplifier Section with Setting
the Full-Scale Current Section................................................. 13
Changes to DAC Transfer Function Section............................... 14
Changes to Interleaved Mode Timing Section ........................... 16
Added Figure 28 ............................................................................. 16
Changes to Power and Grounding Considerations Section ..... 20
Changes to Figure 44...................................................................... 22
Deleted Figure 43............................................................................ 17
Changes to CDMA Section ........................................................... 23
Changes to Figure 45 Caption ...................................................... 23
Changes to Figure 46...................................................................... 24
Changes to Figure 48...................................................................... 26
Updated Outline Dimensions....................................................... 30
Changes to Ordering Guide .......................................................... 30
5/00—Revision 0: Initial Version
Rev. A | Page 2 of 32
AD9709
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY 1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUT
Offset Error
Gain Error Without Internal Reference
Gain Error with Internal Reference
Gain Match
TA = 25°C
TMIN to TMAX
TMIN to TMAX
Full-Scale Output Current 2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current 3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small-Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift Without Internal Reference
Gain Drift with Internal Reference
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD1, DVDD2
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD) 4
Digital Supply Current (IDVDD) 5
Supply Current Sleep Mode (IAVDD)
Power Dissipation4 (5 V, IOUTFS = 20 mA)
Power Dissipation5 (5 V, IOUTFS = 20 mA)
Power Dissipation 6 (5 V, IOUTFS = 20 mA)
Power Supply Rejection Ratio 7 —AVDD
Power Supply Rejection Ratio7—DVDD1, DVDD2
OPERATING RANGE
Min
8
Typ
Max
Unit
Bits
−0.5
−0.5
±0.1
±0.1
+0.5
+0.5
LSB
LSB
−0.02
−2
−5
±0.25
+1
+0.02
+2
+5
% of FSR
% of FSR
% of FSR
+0.3
+1.6
+0.14
20.0
+1.25
% of FSR
% of FSR
dB
mA
V
kΩ
pF
1.26
V
nA
−0.3
−1.6
−0.14
2.0
−1.0
±0.1
100
5
1.14
1.20
100
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0.1
1.25
3
2.7
1
0.5
V
MΩ
MHz
0
±50
±100
±50
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
5
5
71
5
8
380
420
450
−0.4
−0.025
−40
1
5.5
5.5
75
7
15
12
410
450
+0.4
+0.025
+85
Measured at IOUTA, driving a virtual ground.
Nominal full-scale current, IOUTFS, is 32 times the IREF current.
An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4
Measured at fCLK = 25 MSPS and fOUT = 1.0 MHz.
5
Measured at fCLK = 100 MSPS and fOUT = 1 MHz.
6
Measured as unbuffered voltage output with IOUTFS = 20 mA and RLOAD = 50 Ω at IOUTA and IOUTB, fCLK = 100 MSPS, and fOUT = 40 MHz.
7
±10% power supply variation.
2
3
B
Rev. A | Page 3 of 32
V
V
mA
mA
mA
mA
mW
mW
mW
% of FSR/V
% of FSR/V
°C
AD9709
DYNAMIC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, differential transformer-coupled output, 50 Ω
doubly terminated, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLK)
Output Settling Time (tST) to 0.1% 1
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (90% to 10%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLK = 100 MSPS, fOUT = 1.00 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
fCLK = 65 MSPS, fOUT = 1.00 MHz
fCLK = 65 MSPS, fOUT = 2.51 MHz
fCLK = 65 MSPS, fOUT = 5.02 MHz
fCLK = 65 MSPS, fOUT = 14.02 MHz
fCLK = 65 MSPS, fOUT = 25 MHz
fCLK = 125 MSPS, fOUT = 25 MHz
fCLK = 125 MSPS, fOUT = 40 MHz
Signal to Noise and Distortion Ratio
fCLK = 50 MHz, fOUT = 1 MHz
Total Harmonic Distortion
fCLK = 100 MSPS, fOUT = 1.00 MHz
fCLK = 50 MSPS, fOUT = 2.00 MHz
fCLK = 125 MSPS, fOUT = 4.00 MHz
fCLK = 125 MSPS, fOUT = 10.00 MHz
Multitone Power Ratio (Eight Tones at 110 kHz Spacing)
fCLK = 65 MSPS, fOUT = 2.00 MHz to 2.99 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
Channel Isolation
fCLK = 125 MSPS, fOUT = 10 MHz
fCLK = 125 MSPS, fOUT = 40 MHz
Min
Typ
Max
125
63
35
1
5
2.5
2.5
50
30
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
68
62
56
50
68
68
66
60
50
63
55
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
50
dB
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1
−67
−63
−63
−63
Measured single-ended into 50 Ω load.
Rev. A | Page 4 of 32
Unit
−63
dBc
dBc
dBc
dBc
58
51
46
41
dBc
dBc
dBc
dBc
85
77
dBc
dBc
AD9709
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter
DIGITAL INPUTS
Logic 1 Voltage @ DVDD1 = DVDD2 = 5 V
Logic 1 Voltage @ DVDD1 = DVDD2 = 3.3 V
Logic 0 Voltage @ DVDD1 = DVDD2 = 5 V
Logic 0 Voltage @ DVDD1 = DVDD2 = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulse Width (tLPW, tCPW)
Min
Typ
3.5
2.1
5
3
0
Max
1.3
0.9
+10
+10
0
−10
−10
5
2.0
1.5
3.5
Timing Diagram
See Table 3 and the DAC Timing section for more information about the timing specifications.
tS
tH
DATA IN
(WRT2) (WRT1/IQWRT)
tLPW
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(CLK2) (CLK1/IQCLK)
tPD
Figure 2. Timing for Dual and Interleaved Modes
Rev. A | Page 5 of 32
00606-002
tCPW
IOUTA
OR
IOUTB
Unit
V
V
V
V
μA
μA
pF
ns
ns
ns
AD9709
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
AVDD
DVDD1, DVDD2
ACOM
AVDD
MODE, CLK1/IQCLK,
CLK2/IQRESET,
WRT1/IQWRT,
WRT2/IQSEL
Digital Inputs
IOUTA1/IOUTA2,
IOUTB1/IOUTB2
REFIO, FSADJ1,
FSADJ2
GAINCTRL, SLEEP
Junction Temperature
Storage Temperature
Range
Lead Temperature
(10 sec)
With
Respect To
ACOM
DCOM1/DCOM2
DCOM1/DCOM2
DVDD1/DVDD2
DCOM1/DCOM2
THERMAL RESISTANCE
Rating
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +0.3 V
−6.5 V to +6.5 V
−0.3 V to DVDD1/
DVDD2 + 0.3 V
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type
48-Lead LQFP
θJA
91
ESD CAUTION
DCOM1/DCOM2
ACOM
−0.3 V to DVDD1/
DVDD2 + 0.3 V
−1.0 V to AVDD + 0.3 V
ACOM
−0.3 V to AVDD + 0.3 V
ACOM
−0.3 V to AVDD + 0.3 V
150°C
−65°C to +150°C
300°C
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Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 6 of 32
Unit
°C/W
AD9709
48 47 46 45 44 43 42
DB7P1 (MSB) 1
SLEEP
ACOM
IOUTA2
IOUTB2
FSADJ2
GAINCTRL
REFIO
FSADJ1
IOUTB1
IOUTA1
AVDD
MODE
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
41 40 39 38 37
36
NC
35
NC
DB5P1 3
34
NC
DB4P1
4
33
NC
DB3P1
5
32
NC
DB2P1
6
31
NC
DB1P1
7
30
DB0P2 (LSB)
DB0P1
8
29
DB1P2
NC 9
28
DB2P2
NC 10
27
DB3P2
NC 11
26
DB4P2
NC 12
25
DB5P2
DB6P1
PIN 1
INDICATOR
2
AD9709
TOP VIEW
(Not to Scale)
00606-003
DB6P2
DB7P2 (MSB)
DVDD2
DCOM2
WRT2/IQSEL
CLK2/IQRESET
CLK1/IQCLK
WRT1/IQWRT
DVDD1
DCOM1
NC
NC = NO CONNECT
NC
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3.
Table 6. Pin Function Descriptions
Pin No.
1 to 8
9 to 14, 31 to 36
15, 21
16, 22
17
18
19
20
23 to 30
37
38
39, 40
41
42
43
44
45, 46
47
48
Mnemonic
DB7P1 to DB0P1
NC
DCOM1, DCOM2
DVDD1, DVDD2
WRT1/IQWRT
CLK1/IQCLK
CLK2/IQRESET
WRT2/IQSEL
DB7P2 to DB0P2
SLEEP
ACOM
IOUTA2, IOUTB2
FSADJ2
GAINCTRL
REFIO
FSADJ1
IOUTB1, IOUTA1
AVDD
MODE
Description
Data Bit Pins (Port 1)
No Connection
Digital Common
Digital Supply Voltage
Input Write Signal for Port 1 (IQWRT in Interleaving Mode)
Clock Input for DAC1 (IQCLK in Interleaving Mode)
Clock Input for DAC2 (IQRESET in Interleaving Mode)
Input Write Signal for Port 2 (IQSEL in Interleaving Mode)
Data Bit Pins (Port 2)
Power-Down Control Input
Analog Common
Port 2 Differential DAC Current Outputs
Full-Scale Current Output Adjust for DAC2
Master/Slave Resistor Control Mode.
Reference Input/Output
Full-Scale Current Output Adjust for DAC1
Port 1 Differential DAC Current Outputs
Analog Supply Voltage
Mode Select (1 = dual port, 0 = interleaved)
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Rev. A | Page 7 of 32
AD9709
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.3 V or 5 V, DVDD = 3.3 V, IOUTFS = 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to Nyquist,
unless otherwise noted.
75
75
fCLK = 25MSPS
70
70
0dBFS
65
fCLK = 5MSPS
SFDR (dBc)
SFDR (dBc)
65
60
fCLK = 65MSPS
55
–6dBFS
60
55
–12dBFS
fCLK = 125MSPS
100
fOUT (MHz)
45
0
5
10
35
60
70
35
70
0dBFS
0dBFS
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65
SFDR (dBc)
65
–6dBFS
60
–12dBFS
55
–6dBFS
60
–12dBFS
55
50
50
0.5
1.0
1.5
2.0
2.5
45
00606-006
0
fOUT (MHz)
0
10
20
30
40
50
fOUT (MHz)
Figure 5. SFDR vs. fOUT @ 5 MSPS
Figure 8. SFDR vs. fOUT @ 125 MSPS
75
75
70
70
IOUTFS = 20mA
0dBFS
65
SFDR (dBc)
65
–6dBFS
60
55
60
IOUTFS = 10mA
55
–12dBFS
IOUTFS = 5mA
50
50
0
2
4
6
8
fOUT (MHz)
10
12
00606-007
SFDR (dBc)
30
75
70
45
25
Figure 7. SFDR vs. fOUT @ 65 MSPS
75
SFDR (dBc)
20
fOUT (MHz)
Figure 4. SFDR vs. fOUT @ 0 dBFS
45
15
00606-008
10
00606-009
1
00606-005
45
0.1
00606-010
50
50
45
0
5
10
15
20
25
30
fOUT (MHz)
Figure 9. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS
Figure 6. SFDR vs. fOUT @ 25 MSPS
Rev. A | Page 8 of 32
AD9709
75
70
5MSPS/0.46MHz
70
10MSPS/0.91MHz
60
SINAD (dBc)
60
25MSPS/2.27MHz
65MSPS/5.91MHz
55
50
50
45
IOUTFS = 5mA
125MSPS/11.37MHz
–22
–19
–16
–13
–10
–7
IOUTFS = 10mA
–4
–1
2
AOUT (dBFS)
40
00606-011
40
–25
0
20
40
Figure 10. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/11
80
100
120
140
Figure 13. SINAD vs. fCLK and IOUTFS @ fOUT = 5 MHz and 0 dBFS
75
0.06
0.04
70
5MSPS/1.0MHz
0.02
INL (LSBs)
65
60
10MSPS/2.0MHz
0
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125MSPS/5.0MHz
55
50
–0.02
–0.04
–0.06
65MSPS/13.0MHz
45
25MSPS/5.0MHz
–15
–10
–5
0
AOUT (dBFS)
–0.10
00606-012
–20
0
32
64
96
128
160
192
224
256
00606-015
–0.08
40
–25
CODE
Figure 11. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/5
Figure 14. Typical INL
75
0.07
0.06
70
0.965MHz/1.035MHz @ 7MSPS
0.05
DNL (LSBs)
65
60
55
0.04
0.03
0.02
16.9MHz/19.1MHz @ 125MSPS
50
0.01
8.8MHz/9.8MHz @ 65MSPS
45
0
3.3MHz/3.4MHz @ 25MSPS
40
–25
–20
–15
–10
–5
AOUT (dBFS)
0
00606-013
SFDR (dBc)
60
fCLK (MSPS)
00606-014
45
SFDR (dBc)
IOUTFS = 20mA
55
Figure 12. Dual-Tone SFDR vs. AOUT @ fOUT = fCLK/7
–0.01
0
50
100
150
CODE
Figure 15. Typical DNL
Rev. A | Page 9 of 32
200
250
00606-016
SFDR (dBc)
65
65
AD9709
75
0
–10
70
fOUT = 10MHz
–30
fOUT = 25MHz
60
SFDR (dBm)
SFDR (dBc)
65
–20
fOUT = 40MHz
55
–40
–50
–60
fOUT = 60MHz
–70
50
–10
10
30
50
70
90
TEMPERATURE (°C)
–90
0
20
30
40
50
60
60
FREQUENCY (MHz)
Figure 16. SFDR vs. Temperature @ fCLK = 125 MSPS, 0 dBFS
0.05
10
00606-020
–30
00606-021
45
–50
00606-017
–80
Figure 19. Dual-Tone SFDR @ fCLK = 125 MSPS
0
1.0
GAIN ERROR
–20
0.5
OFFSET ERROR
–30
SFDR (dBm)
GAIN ERROR (%FS)
0.03
–40
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0
0
–0.03
–0.5
–50
–60
–70
–80
–20
0
20
40
60
–1.0
80
00606-018
–0.05
–40
TEMPERATURE (°C)
Figure 17. Gain and Offset Error vs. Temperature @ fCLK = 125 MSPS
–10
–20
–30
–40
–50
–60
–70
–80
0
10
20
30
40
50
FREQUENCY (MHz)
60
00606-019
–90
–100
–90
0
10
20
30
40
50
FREQUENCY (MHz)
Figure 20. Four-Tone SFDR @ fCLK = 125 MSPS
0
SFDR (dBm)
OFFSET ERROR (%FS)
–10
Figure 18. Single-Tone SFDR @ fCLK = 125 MSPS
Rev. A | Page 10 of 32
AD9709
TERMINOLOGY
Linearity Error (Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full-scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
Offset error is the deviation of the output current from the ideal of
zero. For IOUTA, 0 mA output is expected when the inputs are all 0s.
For IOUTB, 0 mA output is expected when all inputs are set to 1s.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For offset
and gain drift, the drift is reported in part per million (ppm) of
full-scale range (FSR) per degree Celsius. For reference drift, the
drift is reported in ppm per degree Celsius (pm/°C).
Power Supply Rejection (PSR)
PSR is the maximum change in the full-scale output as the
supplies are varied from nominal to minimum and maximum
specified voltages.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band about its final value,
measured from the start of the output transition.
B
Gain Error
Gain error is the difference between the actual and ideal output
spans. The actual span is determined by the output when all
inputs are set to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The output compliance range is the range of allowable voltage at
the output of a current-output DAC. Operation beyond the
maximum compliance limits may cause either output stage
saturation or breakdown resulting in nonlinear performance.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in picovolts per second (pV-s).
Spurious-Free Dynamic Range
The difference, in decibels (dB), between the rms amplitude of
the output signal and the peak spurious signal over the specified
bandwidth.
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Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Rev. A | Page 11 of 32
AD9709
THEORY OF OPERATION
5V
CLK1/IQCLK CLK2/IQRESET
AVDD
RSET1
2kΩ
REFIO
PMOS
CURRENT
SOURCE
ARRAY
FSADJ2
PMOS
CURRENT
SOURCE
ARRAY
0.1µF
RSET 2
2kΩ
GAINCTRL
DVDD1/DVDD2
DCOM1/DCOM2
RETIMED CLOCK OUTPUT*
IOUTA1
WRT1/
IQWRT
50Ω
SEGMENTED
LSB
SWITCHES FOR SWITCH IOUTB1
DAC1
DAC1
LATCH
DAC2
LATCH
TO HP3589A
OR EQUIVALENT
SPECTRUM/
NETWORK
ANALYZER
50Ω
IOUTA2
SEGMENTED
LSB
SWITCHES FOR SWITCH IOUTB2
DAC2
MODE
MULTIPLEXING LOGIC
1.2V REF
Mini-Circuits
T1-1T
AD9709
CLK
DIVIDER
CHANNEL 1 LATCH
CHANNEL 2 LATCH
PORT 1
PORT 2
50Ω
DVDD1/
DCOM1/ DVDD2
DCOM2 ACOM
5V
WRT2/
IQSEL
DIGITAL
DATA
LECROY 9210
PULSE
GENERATOR
*AWG2021 CLOCK RETIMED SUCH THAT
DIGITAL DATA TRANSITIONS ON FALLING
EDGE OF 50% DUTY CYCLE CLOCK.
TEKTRONIX
AWG2021
WITH OPTION 4
00606-004
FSADJ1
SLEEP
Figure 21. Basic AC Characterization Test Setup for AD9709, Testing Port 1 in Dual Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2
5V
CLK1/IQCLK
CLK2/IQRESET
AVDD
IREF 1
0.1µF
RSET 2
2kΩ
FSADJ1
REFIO
SLEEP
PMOS
CURRENT
SOURCE
ARRAY
VDIFF = VOUTA – VOUTB
CLK
DIVIDER
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FSADJ2
IREF 2
1.2V REF
PMOS
CURRENT
SOURCE
ARRAY
AD9709
DAC1
LATCH
DAC2
LATCH
WRT1/
IQWRT
IOUTA2
SEGMENTED
LSB
SWITCHES FOR
IOUTB2
SWITCH
DAC2
DVDD1/
DVDD2
MULTIPLEXING LOGIC
CHANNEL 1 LATCH
GAINCTRL
VOUT1A
IOUTA1
SEGMENTED
LSB
SWITCHES FOR
I
SWITCH OUTB1
DAC1
VOUT2A
VOUT2B
5V
RL2B
50Ω
RL1B
50Ω
RL1A
50Ω
RL2A
50Ω
ACOM
DCOM1/
DCOM2
CHANNEL 2 LATCH
PORT 1
PORT 2
DIGITAL DATA INPUTS
VOUT1B
WRT2/
IQSEL
MODE
00606-022
RSET 1
2kΩ
Figure 22. Simplified Block Diagram
FUNCTIONAL DESCRIPTION
All of these current sources are switched to one of the two
output nodes (that is, IOUTA or IOUTB) via the PMOS differential
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching of complementary drive signals to the inputs of the
differential current switches.
B
Figure 22 shows a simplified block diagram of the AD9709. The
AD9709 consists of two DACs, each one with its own independent
digital control logic and full-scale output current control. Each
DAC contains a PMOS current source array capable of providing
up to 20 mA of full-scale current (IOUTFS).
The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources instead of an R-2R
ladder enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the high output impedance
of each DAC (that is, >100 kΩ).
The analog and digital sections of the AD9709 have separate
power supply inputs (that is, AVDD and DVDD1/DVDD2) that
can operate independently over a 3.3 V to 5 V range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V band gap
voltage reference, and two reference control amplifiers.
Rev. A | Page 12 of 32
AD9709
The full-scale output current of each DAC is regulated by
separate reference control amplifiers and can be set from 2 mA
to 20 mA via an external network connected to the full-scale
adjust (FSADJ) pin. The external network in combination with
both the reference control amplifier and voltage reference
(VREFIO) sets the reference current (IREF), which is replicated to
the segmented current sources with the proper scaling factor.
The full-scale current (IOUTFS) is 32 × IREF.
GAIN CONTROL MODE
The AD9709 allows the gain of each channel to be set
independently by connecting one RSET resistor to FSADJ1 and
another RSET resistor to FSADJ2. To add flexibility and reduce
system cost, a single RSET resistor can be used to set the gain of
both channels simultaneously.
REFERENCE OPERATION
The AD9709 contains an internal 1.20 V band gap reference.
This can easily be overridden by a low noise external reference
with no effect on performance. REFIO serves as either an input
or output depending on whether the internal or an external
reference is used. To use the internal reference, simply decouple
the REFIO pin to ACOM with a 0.1 μF capacitor. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used elsewhere in the circuit, an external buffer
amplifier with an input bias current of less than 100 nA should
be used. An example of the use of the internal reference is
shown in Figure 23.
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
GAINCTRL
REFERENCE
SECTION
REFIO
0.1µF
RSET
FSADJ1/
FSADJ2
I REF =
ACOM
22nF
Figure 23. Internal Reference Configuration
An external reference can be applied to REFIO as shown in
Figure 24. The external reference can provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 μF
compensation capacitor is not required because the internal
reference is overridden and the relatively high input impedance
of REFIO minimizes any loading of the external reference.
GAINCTRL
1.2V
REF
REFIO
EXTERNAL
REFERENCE
256Ω
IREF
RSET
FSADJ1/
FSADJ2
AVDD
AD9709
REFERENCE
SECTION
CURRENT
SOURCE
ARRAY
22nF
Figure 24. External Reference Configuration
ACOM
00606-024
AVDD
SETTING THE FULL-SCALE CURRENT
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256Ω
IREF
CURRENT
SOURCE
ARRAY
00606-023
ADDITIONAL
EXTERNAL
LOAD
Note that only parts with a date code of 9930 or later have the
master/slave gain control function. For parts with a date code
before 9930, Pin 42 must be connected to AGND, and the part
operates in the two-resistor, independent gain control mode.
Both of the DACs in the AD9709 contain a control amplifier
that is used to regulate the full-scale output current (IOUTFS). The
control amplifier is configured as a V-I converter, as shown in
Figure 23, so that its current output (IREF) is determined by the ratio
of the VREFIO and an external resistor, RSET.
AVDD
AD9709
1.2V
REF
When GAINCTRL is low (that is, connected to analog ground),
the independent channel gain control mode using two resistors
is enabled. In this mode, individual RSET resistors should be
connected to FSADJ1 and FSADJ2. When GAINCTRL is high
(that is, connected to AVDD), the master/slave channel gain
control mode using one network is enabled. In this mode, a
single network is connected to FSADJ1, and the FSADJ2 pin
must be left unconnected.
VREFIO
RSET
The DAC full-scale current, IOUTFS, is an output current 32 times
larger than the reference current, IREF.
I OUTFS = 32 × I REF
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS from 2 mA to 20 mA by setting IREF between 62.5 μA and
625 μA. The wide adjustment range of IOUTFS provides several
benefits. The first relates directly to the power dissipation of
the AD9709, which is proportional to IOUTFS (refer to the Power
Dissipation section). The second relates to the 20 dB adjustment,
which is useful for system gain control purposes.
It should be noted that when the RSET resistors are 2 kΩ or less,
the 22 nF capacitor and 256 Ω resistor shown in Figure 23 and
Figure 24 are not required and the reference current can be set
by the RSET resistors alone. For RSET values greater than 2 kΩ, the
22 nF capacitor and 256 Ω resistor networks are required to
ensure the stability of the reference control amplifier(s).
Regardless of the value of RSET, however, if the RSET resistor is
located more than ~10 cm away from the pin, use of the 22 nF
capacitor and 256 Ω resistor is recommended.
Rev. A | Page 13 of 32
AD9709
DAC TRANSFER FUNCTION
Both DACs in the AD9709 provide complementary current outputs, IOUTA and IOUTB. IOUTA provides a near full-scale current
output, IOUTFS, when all bits are high (that is, DAC CODE = 256)
while IOUTB, the complementary output, provides no current.
The current output appearing at IOUTA and IOUTB is a function of
both the input code and IOUTFS and can be expressed as
B
IOUTA = (DAC CODE/256) × IOUTFS
(1)
IOUTB = (255 − DAC CODE)/256 × IOUTFS
(2)
where DAC CODE = 0 to 255 (that is, decimal representation).
IOUTFS is a function of the reference current (IREF), which is
nominally set by a reference voltage (VREFIO) and an external
resistor (RSET). It can be expressed as
IOUTFS = 32 × IREF
(3)
where
IREF = VREFIO/RSET
(4)
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTA and IOUTB
should be connected directly to matching resistive loads, RLOAD,
that are tied to the analog common, ACOM. Note that RLOAD
can represent the equivalent load resistance seen by IOUTA or
IOUTB, as would be the case in a doubly terminated 50 Ω or 75 Ω
cable. The single-ended voltage output appearing at the IOUTA
and IOUTB nodes is
B
B
VOUTA = IOUTA × RLOAD
differential amplifier configuration. The ac performance of the
AD9709 is optimum and specified using a differential
transformer-coupled output in which the voltage swing at IOUTA
and IOUTB is limited to ±0.5 V. If a single-ended unipolar output
is desirable, IOUTA should be selected.
B
The distortion and noise performance of the AD9709 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can be
significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed
waveform increases. This is due to the first-order cancellation of
various dynamic common-mode distortion mechanisms, digital
feedthrough, and noise.
B
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (that is, assuming no
source termination). Because the output currents of IOUTA and
IOUTB are complementary, they become additive when processed
differentially. A properly selected transformer allows the AD9709
to provide the required power and voltage levels to different loads.
B
The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS
device. As a result, maintaining IOUTA and/or IOUTB at a virtual
ground via an I-V op amp configuration results in the optimum
dc linearity. Note that the INL/DNL specifications for the
AD9709 are measured with IOUTA maintained at a virtual ground
via an op amp.
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VOUTB = IOUTB × RLOAD
(5)
(6)
B
B
Note the full-scale value of VOUTA and VOUTB must not exceed the
specified output compliance range to maintain the specified
distortion and linearity performance.
VDIFF = (IOUTA − IOUTB) × RLOAD
(7)
Equation 7 highlights some of the advantages of operating the
AD9709 differentially. First, the differential operation helps cancel
common-mode error sources associated with IOUTA and IOUTB,
such as noise, distortion, and dc offsets. Second, the differential
code-dependent current and subsequent voltage, VDIFF, is twice
the value of the single-ended voltage output (that is, VOUTA or
VOUTB), thus providing twice the signal power to the load.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a
breakdown of the output stage and affect the reliability of the
AD9709.
Note that the gain drift temperature performance for a singleended (VOUTA and VOUTB) or differential output (VDIFF) of the
AD9709 can be enhanced by selecting temperature tracking
resistors for RLOAD and RSET due to their ratiometric relationship.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. When IOUTFS is decreased
from 20 mA to 2 mA, the positive output compliance range
degrades slightly from its nominal 1.25 V to 1.00 V. The optimum
distortion performance for a single-ended or differential output
is achieved when the maximum full-scale signal at IOUTA and IOUTB
does not exceed 0.5 V. Applications requiring the AD9709 output
(that is, VOUTA and/or VOUTB) to extend its output compliance range
should size RLOAD accordingly. Operation beyond this compliance
range adversely affects the linearity performance of the AD9709
and subsequently degrade its distortion performance.
B
B
ANALOG OUTPUTS
The complementary current outputs, IOUTA and IOUTB, in each
DAC can be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, VOUTA and VOUTB, via a load
resistor, RLOAD, as described in Equation 5 through Equation 7.
The differential voltage, VDIFF, existing between VOUTA and VOUTB
can be converted to a single-ended voltage via a transformer or
B
B
Rev. A | Page 14 of 32
AD9709
The digital interface is implemented using an edge-triggered
master slave latch. The DAC outputs are updated following
either the rising edge or every other rising edge of the clock,
depending on whether dual or interleaved mode is used. The
DAC outputs are designed to support a clock rate as high as
125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
DAC TIMING
tH
DATA IN
WRT1/WRT2
tLPW
CLK1/CLK2
tCPW
IOUTA
OR
IOUTB
tPD
Figure 26. Dual Port Mode Timing
DATA IN
D1
D2
D3
D4
D5
WRT1/WRT2
CLK1/CLK2
IOUTA
OR
IOUTB
XX
D1
D2
D3
D4
Figure 27. Dual Mode Timing
Interleaved Mode Timing
PORT 1
INPUT
LATCH
When the MODE pin is at Logic 0, the AD9709 operates in
interleaved mode (refer to Figure 25). In addition, WRT1
functions as IQWRT, CLK1 functions as IQCLK, WRT2
functions as IQSEL, and CLK2 functions as IQRESET.
DAC1
LATCH
DAC1
IQCLK
IQRESET
÷2
DEINTERLEAVED
DATA OUT
DAC2
LATCH
00606-027
PORT 2
INPUT
LATCH
IQWRT
IQSEL
tS
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The AD9709 can operate in two timing modes, dual and
interleaved, which are described in the following sections. The
block diagram in Figure 25 represents the latch architecture in
the interleaved timing mode.
INTERLEAVED
DATA IN, PORT 1
Timing specifications for dual port mode are given in Figure 26
and Figure 27.
00606-025
The digital inputs of the AD9709 consist of two independent
channels. For the dual port mode, each DAC has its own
dedicated 8-bit data port: WRT line and CLK line. In the
interleaved timing mode, the function of the digital control pins
changes as described in the Interleaved Mode Timing section.
The 8-bit parallel data inputs follow straight binary coding
where DB7P1 and DB7P2 are the most significant bits (MSBs)
and DB0P1 and DB0P2 are the least significant bits (LSBs).
IOUTA produces a full-scale output current when all data bits are
at Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
The rising edge of CLK should occur before or simultaneously
with the rising edge of WRT. If the rising edge of CLK occurs
after the rising edge of WRT, a minimum delay of 2 ns should
be maintained from rising edge of WRT to rising edge of CLK.
00606-026
DIGITAL INPUTS
DAC2
Figure 25. Latch Structure in Interleaved Mode
Dual Port Mode Timing
When the MODE pin is at Logic 1, the AD9709 operates in dual
port mode (refer to Figure 21). The AD9709 functions as two
distinct DACs. Each DAC has its own completely independent
digital input and control lines.
The AD9709 features a double-buffered data path. Data enters the
device through the channel input latches. This data is then transferred to the DAC latch in each signal path. After the data is loaded
into the DAC latch, the analog output settles to its new value.
For general consideration, the WRT lines control the channel
input latches, and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.
Data enters the device on the rising edge of IQWRT. The
logic level of IQSEL steers the data to either Channel Latch 1
(IQSEL = 1) or to Channel Latch 2 (IQSEL = 0). For proper
operation, IQSEL should only change state when IQWRT and
IQCLK are low.
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the next rising edge on IQCLK updates both DAC
latches with the data present at their inputs. In the interleaved
mode, IQCLK is divided by 2 internally. Following this first
rising edge, the DAC latches are only updated on every other
rising edge of IQCLK. In this way, IQRESET can be used to
synchronize the routing of the data to the DACs.
Similar to the order of CLK and WRT in dual port mode,
IQCLK should occur before or simultaneously with IQWRT.
Timing specifications for interleaved mode are shown in Figure 28
and Figure 30.
The digital inputs are CMOS compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive supply
(DVDDx) or
Rev. A | Page 15 of 32
VTHRESHOLD = DVDDx/2 (±20%)
AD9709
tS
tH
INTERLEAVED
DATA
xx
D1
D2
D3
D4
D5
IQSEL
DATA IN
500 ps
IQWRT
IQSEL
IQRESET
tH*
tLPW
DAC OUTPUT
PORT 1
IQCLK
IOUTA
OR
IOUTB
00606-056
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.
Figure 28. 5 V or 3.3 V Interleaved Mode Timing
At 5 V it is permissible to drive IQWRT and IQCLK together as
shown in Figure 29, but at 3.3 V the interleaved data transfer is
not reliable.
tS
tH
The internal digital circuitry of the AD9709 is capable of operating
at a digital supply of 3.3 V or 5 V. As a result, the digital inputs
can also accommodate TTL levels when DVDD1/DVDD2 is set to
accommodate the maximum high level voltage (VOH(MAX)) of the
TTL drivers. A DVDD1/DVDD2 of 3.3 V typically ensures proper
compatibility with most TTL logic families. Figure 31 shows the
equivalent digital input circuit for the data and clock inputs.
The sleep mode input is similar with the exception that it
contains an active pull-down circuit, thus ensuring that the
AD9709 remains enabled if this input is left disconnected.
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DVDD1
DIGITAL
INPUT
00606-030
IQSEL
tH*
Figure 31. Equivalent Digital Input
tLPW
IQCLK
tPD
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.
Figure 29. 5 V Only Interleaved Mode Timing
00606-028
IOUTA
OR
IOUTB
D4
D2
Figure 30. Interleaved Mode Timing
tPD
DATA IN
D3
D1
xx
DAC OUTPUT
PORT 2
500 ps
IQWRT
xx
00606-029
IQWRT
IQCLK
Because the AD9709 is capable of being clocked up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9709
with reduced logic swings and a corresponding digital supply
(DVDD1/DVDD2) results in the lowest data feedthrough and
on-chip digital noise. The drivers of the digital data interface
circuitry should be specified to meet the minimum setup and
hold times of the AD9709 as well as its required minimum and
maximum input logic level thresholds.
Rev. A | Page 16 of 32
AD9709
Note that the clock input can also be driven via a sine wave, which
is centered around the digital threshold (that is, DVDDx/2) and
meets the minimum and maximum logic threshold. This typically
results in a slight degradation in the phase noise, which becomes
more noticeable at higher sampling rates and output frequencies.
In addition, at higher sampling rates, the 20% tolerance of the
digital logic threshold should be considered because it affects
the effective clock duty cycle and, subsequently, cut into the
required data setup and hold times.
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9709 is rising-edge triggered and
therefore exhibits SNR sensitivity when the data transition is
close to this edge. In general, the goal when applying the AD9709 is
to make the data transition close to the falling clock edge. This
becomes more important as the sample rate increases. Figure 32
shows the relationship of SNR to clock/data placement.
60
50
40
30
20
10
0
–4
–3
–2
–1
0
1
2
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE (ns)
3
4
00606-031
The external clock driver circuitry provides the AD9709 with a
low-jitter clock input meeting the minimum and maximum logic
levels while providing fast edges. Fast clock edges help minimize
jitter manifesting itself as phase noise on a reconstructed waveform.
Therefore, the clock input should be driven by the fastest logic
family suitable for the application.
Input Clock and Data Timing Relationship
SNR (dBc)
Digital signal paths should be kept short, and run lengths should be
matched to avoid propagation delay mismatch. The insertion of
a low value (that is, 20 Ω to 100 Ω) resistor network between
the AD9709 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to digital feedthrough. For longer board traces and
high data update rates, stripline techniques with proper
impedance and termination resistors should be considered to
maintain “clean” digital inputs.
Figure 32. SNR vs. Clock Placement @ fOUT = 20 MHz and fCLK = 125 MSPS
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Rev. A | Page 17 of 32
AD9709
SLEEP MODE OPERATION
80
The AD9709 has a power-down function that turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 3.3 V to 5 V and
temperature range. This mode can be activated by applying a
Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold
is equal to 0.5 × AVDD. This digital input also contains an active
pull-down circuit that ensures the AD9709 remains enabled if
this input is left disconnected. The AD9709 requires less than
50 ns to power down and approximately 5 μs to power back up.
70
IAVDD (mA)
60
50
40
30
20
5
10
15
20
25
0.4
0.5
00606-033
•
•
•
•
0
0.5
00606-034
10
The power dissipation, PD, of the AD9709 is dependent on several
factors, including
00606-032
POWER DISSIPATION
IOUTFS (mA)
Figure 33. IAVDD vs. IOUTFS
the power supply voltages (AVDD and DVDD1/DVDD2)
the full-scale current output (IOUTFS)
the update rate (fCLK)
the reconstructed digital input waveform
35
30
125MSPS
25
100MSPS
IDVDD (mA)
The power dissipation is directly proportional to the analog
supply current, IAVDD, and the digital supply current, IDVDD. IAVDD
is directly proportional to IOUTFS, as shown in Figure 33, and is
insensitive to fCLK.
Conversely, IDVDD is dependent on the digital input waveform,
fCLK, and digital supply (DVDD1/DVDD2). Figure 34 and
Figure 35 show IDVDD as a function of full-scale sine wave output
ratios (fOUT/fCLK) for various update rates with DVDD1 =
DVDD2 = 5 V and DVDD1 = DVDD2 = 3.3 V, respectively.
Note how IDVDD is reduced by more than a factor of 2 when
DVDD1/DVDD2 is reduced from 5 V to 3.3 V.
20
65MSPS
15
10
25MSPS
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5
5MSPS
0
0
0.1
0.2
0.3
RATIO (fOUT/fCLK)
Figure 34. IDVDD vs. Ratio @ DVDD1 = DVDD2 = 5 V
18
125MSPS
16
14
100MSPS
IDVDD (mA)
12
10
65MSPS
8
6
25MSPS
4
5MSPS
2
0
0
0.1
0.2
0.3
0.4
RATIO (fOUT/fCLK)
Figure 35. IDVDD vs. Ratio @ DVDD1 = DVDD2 = 3.3 V
Rev. A | Page 18 of 32
AD9709
APPLYING THE AD9709
The following sections illustrate some typical output configurations for the AD9709. Unless otherwise noted, it is assumed that
IOUTFS is set to a nominal 20 mA. For applications requiring the
optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
can consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the
optimum high frequency performance and is recommended for
any application allowing for ac coupling. The differential op
amp configuration is suitable for applications requiring dc
coupling, bipolar output, signal gain, and/or level shifting,
within the bandwidth of the chosen op amp.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage results
if IOUTA and/or IOUTB is connected to an appropriately sized load
resistor, RLOAD, referred to ACOM. This configuration may be
more suitable for a single-supply system requiring a dc-coupled,
ground-referred output voltage. Alternatively, an amplifier can
be configured as an I-V converter, thus converting IOUTA or IOUTB
into a negative unipolar voltage. This configuration provides the
best dc linearity because IOUTA or IOUTB is maintained at a virtual
ground. Note that IOUTA provides slightly better performance
than IOUTB.
B
output compliance range of the AD9709. A differential resistor,
RDIFF, can be inserted in applications where the output of the
transformer is connected to the load, RLOAD, via a passive
reconstruction filter or cable. RDIFF is determined by the
transformer’s impedance ratio and provides the proper source
termination that results in a low VSWR. Note that approximately
half the signal power will be dissipated across RDIFF.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used as shown in Figure 37 to perform a
differential-to-single-ended conversion. The AD9709 is configured
with two equal load resistors, RLOAD, of 25 Ω each. The differential
voltage developed across IOUTA and IOUTB is converted to a singleended signal via the differential op amp configuration. An optional
capacitor can be installed across IOUTA and IOUTB, forming a real pole
in a low-pass filter. The addition of this capacitor also enhances the
op amp’s distortion performance by preventing the DAC’s highslewing output from overloading the op amp’s input.
B
500Ω
AD9709
225Ω
IOUTA
B
COPT
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DIFFERENTIAL COUPLING USING A
TRANSFORMER
500Ω
25Ω
RLOAD
OPTIONAL
RDIFF
The differential circuit shown in Figure 38 provides the
necessary level shifting required in a single-supply system. In
this case, AVDD, which is the positive analog supply for both
the AD9709 and the op amp, is used to level shift the differential
output of the AD9709 to midsupply (that is, AVDD/2). The
AD8041 is a suitable op amp for this application.
500Ω
AD9709
00606-035
IOUTB
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential
op amp circuit using the AD8047 is configured to provide some
additional signal gain. The op amp must operate from a dual
supply because its output is approximately ±1.0 V. A high speed
amplifier capable of preserving the differential performance of
the AD9709 while meeting other system level objectives (that is,
cost and power) should be selected. The op amp’s differential
gain, gain setting resistor values, and full-scale output swing
capabilities should be considered when optimizing this circuit.
225Ω
IOUTA
Figure 36. Differential Output Using a Transformer
225Ω
IOUTB
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages appearing
at IOUTA and IOUTB (that is, VOUTA and VOUTB) swing symmetrically
around ACOM and should be maintained with the specified
AD8041
COPT
25Ω
1kΩ
25Ω
AVDD
500Ω
B
Rev. A | Page 19 of 32
Figure 38. Single-Supply DC Differential Coupled Circuit
00606-037
Mini-Circuits
T1-1T
IOUTA
25Ω
Figure 37. DC Differential Coupling Using an Op Amp
An RF transformer can be used as shown in Figure 36 to perform
a differential-to-single-ended signal conversion. A differentially
coupled transformer output provides the optimum distortion
performance for output signals whose spectral content lies within
the pass band of the transformer. An RF transformer such as the
Mini-Circuits® T1-1T provides excellent rejection of commonmode distortion (that is, even-order harmonics) and noise over
a wide frequency range. It also provides electrical isolation and
the ability to deliver twice the power to the load. Transformers
with different impedance ratios can also be used for impedance
matching purposes. Note that the transformer provides ac
coupling only.
AD9709
AD8047
225Ω
IOUTB
B
00606-036
OUTPUT CONFIGURATIONS
AD9709
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 39 shows the AD9709 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly terminated
50 Ω cable, because the nominal full-scale current, IOUTFS, of 20 mA
flows through the equivalent RLOAD of 25 Ω. In this case, RLOAD
represents the equivalent load resistance seen by IOUTA or IOUTB.
The unused output (IOUTA or IOUTB) can be connected directly to
ACOM or via a matching RLOAD. Different values of IOUTFS and
RLOAD can be selected as long as the positive compliance range is
adhered to. One additional consideration in this mode is the
INL (see the Analog Outputs section). For optimum INL
performance, the single-ended, buffered voltage output
configuration is suggested.
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figure 49 to Figure 54 illustrate the recommended
printed circuit board ground, power, and signal plane layouts
that are implemented on the AD9709 evaluation board.
B
B
AD9709
IOUTFS = 20mA
VOUTA = 0V TO 0.5V
IOUTA
50Ω
50Ω
00606-038
IOUTB
25Ω
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum from tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9709 AVDD supply over this frequency range is shown in
Figure 41.
90
Figure 39. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
PSRR (dB)
85
Figure 40 shows a buffered single-ended output configuration
in which the U1 op amp performs an I-V conversion on the
AD9709 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, thus minimizing the nonlinear output
impedance effect on the INL performance of the DAC, as
discussed in the Analog Outputs section. Although this singleended configuration typically provides the best dc linearity
performance, its ac distortion performance at higher DAC
update rates may be limited by the slewing capabilities of U1.
U1 provides a negative unipolar output voltage, and its fullscale output voltage is simply the product of RFB and IOUTFS. The
full-scale output should be set within U1’s voltage output swing
capabilities by scaling IOUTFS and/or RFB. An improvement in ac
distortion performance may result with a reduced IOUTFS because
the signal current U1 has to sink will be subsequently reduced.
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B
COPT
RFB
200Ω
AD9709
IOUTFS = 10mA
IOUTA
U1
200Ω
00606-039
VOUT = IOUTFS × RFB
IOUTB
Figure 40. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS
Power Supply Rejection
Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
80
70
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
FREQUENCY (MHz)
00606-040
75
Figure 41. AVDD Power Supply Rejection Ratio vs. Frequency
Note that the data in Figure 41 is given in terms of current out
vs. voltage in. Noise on the analog power supply has the effect
of modulating the internal current sources and therefore the
output current. The voltage noise on AVDD, therefore, is added
in a nonlinear manner to the desired IOUT. PSRR is very code
dependent, thus producing mixing effects that can modulate
low frequency power supply noise to higher frequencies. Worstcase PSRR for either one of the differential DAC outputs occurs
when the full-scale current is directed toward that output. As a
result, the PSRR measurement in Figure 41 represents a worstcase condition in which the digital inputs remain static and the
full-scale output current of 20 mA is directed to the DAC
output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity’s
sake, all of this noise is concentrated at 250 kHz (that is, ignore
harmonics). To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC full-scale
Rev. A | Page 20 of 32
AD9709
Proper grounding and decoupling should be a primary
objective in any high speed, high resolution system. The
AD9709 features separate analog and digital supply and ground
pins to optimize the management of analog and digital ground
currents in a system. In general, decouple the analog supply
(AVDD) to the analog common (ACOM) as close to the chip as
physically possible. Similarly, decouple DVDD1/DVDD2, the
digital supply (DVDD1/DVDD2) to the digital common
(DCOM1/DCOM2) as close to the chip as possible.
For applications that require a single 5 V or 3.3 V supply for
both the analog and digital supplies, a clean analog supply can
be generated using the circuit shown in Figure 42. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low-ESR
type electrolytic and tantalum capacitors.
FERRITE
BEADS
ELECTROLYTIC
TTL/CMOS
LOGIC
CIRCUITS
10µF
TO
22µF
AVDD
0.1µF
ACOM
TANTALUM
5V
POWER SUPPLY
Figure 42. Differential LC Filter for Single 5 V and 3.3 V Applications
www.BDTIC.com/ADI
Rev. A | Page 21 of 32
100µF
CERAMIC
00606-041
current, IOUTFS, one must determine the PSRR in decibels using
Figure 41 at 250 kHz. To calculate the PSRR for a given RLOAD,
such that the units of PSRR are converted from A/V to V/V,
adjust the curve in Figure 41 by the scaling factor 20 × log(RLOAD).
For instance, if RLOAD is 50 Ω, the PSRR is reduced by 34 dB
(that is, the PSRR of the DAC at 250 kHz, which is 85 dB in
Figure 41, becomes 51 dB VOUT/VIN).
AD9709
APPLICATIONS
and phase between the two baseband channels. A quadrature
mixer modulates the I and Q components with the in-phase and
quadrature carrier frequencies and then sums the two outputs
to provide the QAM signal.
QAM is one of the most widely used digital modulation
schemes in digital communications systems. This modulation
technique can be found in FDM as well as spread spectrum
(that is, CDMA) based systems. A QAM signal is a carrier
frequency that is modulated in both amplitude (that is, AM
modulation) and phase (that is, PM modulation). It can be
generated by independently modulating two carriers of
identical frequency but with a 90° phase difference. This results
in an in-phase (I) carrier component and a quadrature (Q)
carrier component at a 90° phase shift with respect to the
I component. The I and Q components are then summed to
provide a QAM signal at the specified carrier frequency.
8
DAC
DSP
OR
ASIC
0°
CARRIER
FREQUENCY
8
90°
TO
MIXER
Σ
DAC
NYQUIST
FILTERS
00606-044
QUADRATURE AMPLITUDE MODULATION (QAM)
USING THE AD9709
QUADRATURE
MODULATOR
Figure 43. Typical Analog QAM Architecture
In this implementation, it is much more difficult to maintain
proper gain and phase matching between the I and Q channels.
The circuit implementation shown in Figure 44 helps improve
the matching between the I and Q channels, and it shows a path
for upconversion using the AD8346 quadrature modulator. The
AD9709 provides both I and Q DACs with a common reference
that will improve the gain matching and stability. RCAL can be
used to compensate for any mismatch in gain between the two
channels. The mismatch may be attributed to the mismatch
between RSET1 and RSET2, the effective load resistance of each
channel, and/or the voltage offset of the control amplifier in each
DAC. The differential voltage outputs of both DACs in the
AD9709 are fed into the respective differential inputs of the
AD8346 via matching networks.
A common and traditional implementation of a QAM
modulator is shown in Figure 43. The modulation is performed
in the analog domain in which two DACs are used to generate
the baseband I and Q components. Each component is then
typically applied to a Nyquist filter before being applied to a
quadrature mixer. The matching Nyquist filters shape and limit
each component’s spectral envelope while minimizing intersymbol
interference. The DAC is typically updated at the QAM symbol
rate, or at a multiple of the QAM symbol rate if an interpolating
filter precedes the DAC. The use of an interpolating filter typically
eases the implementation and complexity of the analog filter,
which can be a significant contributor to mismatches in gain
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AVDD
ROHDE & SCHWARZ
FSEA30B
OR EQUIVALENT
SPECTRUM ANALYZER
0.1µF
ACOM AVDD
PORT Q
CLK1/IQCLK
RL
LA
IOUTA
I DAC
LATCH
I
DAC
CB
CA
RL LA
IOUTA
RL LA RL
Q
DAC
CA
IOUTB
WRT2/IQSEL
LA
RA
BBIP
VOUT
RB
RA
256Ω
22nF
MODE
FSADJ1
256Ω
2kΩ
20kΩ
22nF
FSADJ2
2kΩ
20kΩ
NOTES
1. DAC FULL-SCALE OUTPUT CURRENT = IOUTFS.
2. RA, RB, AND RL ARE THIN FILM RESISTOR NETWORKS
WITH 0.1% MATCHING, 1% ACCURACY AVAILABLE
FROM OHMTEK ORNXXXXD SERIES OR EQUIVALENT.
+
BBQP
RB
RB
LOIP
RA
PHASE
SPLITTER
LOIN
CFILTER
BBQN
RL
VDIFF = 1.82V p-p
SLEEP
VPBF
RL
CB
RL
RA
RB
BBIN
IOUTB
AD9709
Q DAC
LATCH
RL
DIFFERENTIAL
RLC FILTER
RL = 200Ω
0.1µF
RA = 2500Ω
RB = 500Ω
RP = 200Ω
CA = 280pF
CB = 45pF
LA = 10µH
IOUTFS = 11mA
AVDD = 5.0V
VCM = 1.2V
AD8346
REFIO
ROHDE & SCHWARZ
SIGNAL GENERATOR
AVDD
AD976x
RB
0 TO IOUTFS
Figure 44. Baseband QAM Implementation Using an AD9709 and AD8346
Rev. A | Page 22 of 32
RL
VDAC
RA
AD8346
VMOD
00606-045
WRT1/IQWRT
DIGITAL INTERFACE
TEKTRONIX
AWG2021
WITH
OPTION 4
PORT I
DCOM1/ DVDD1/
DCOM2 DVDD2
AD9709
out-of-band is often referred to as adjacent channel power (ACP).
This is a regulatory issue due to the possibility of interference
with other signals being transmitted by air. Regulatory bodies
define a spectral mask outside of the transmit band, and the ACP
must fall under this mask. If distortion in the transmit path causes
the ACP to be above the spectral mask, filtering or different
component selection is needed to meet the mask requirements.
Figure 45 displays the results of using the application circuit shown
in Figure 44 to reconstruct a wideband CDMA (W-CDMA) test
vector using a bandwidth of 8 MHz that is centered at 2.4 GHz
and sampled at 65 MHz. The IF frequency at the DAC output is
15.625 MHz. The adjacent channel power ratio (ACPR) for the
given test vector is measured at greater than 54 dB.
CDMA
–30
Code division multiple access (CDMA) is an air transmit/receive
scheme where the signal in the transmit path is modulated with a
pseudorandom digital code (sometimes referred to as the spreading
code). The effect of this is to spread the transmitted signal across
a wide spectrum. Similar to a discrete multitone (DMT) waveform, a CDMA waveform containing multiple subscribers can
be characterized as having a high peak to average ratio (that is,
crest factor), thus demanding highly linear components in the
transmit signal path. The bandwidth of the spectrum is defined
by the CDMA standard being used, and in operation it is
implemented by using a spreading code with particular
characteristics.
–40
–50
–60
==
(dB)
–70
–80
–90
–100
–110
c11
c11
cu1
–120
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Distortion in the transmit path can lead to power being transmitted
out of the defined band. The ratio of power transmitted in-band to
Rev. A | Page 23 of 32
C0
–130
CENTER 2.4GHz
3MHz
FREQUENCY
cu1
C0
SPAN 30MHz
Figure 45. CDMA Signal, 8 MHz Chip Rate Sampled at 65 MSPS,
Recreated at 2.4 GHz, Adjacent Channel Power > 54 dB
00606-046
I and Q digital data can be fed into the AD9709 in two ways. In
dual port mode, the digital I information drives one input port,
and the digital Q information drives the other input port. If no
interpolation filter precedes the DAC, the symbol rate is the rate
at which the system clock drives the CLK and WRT pins on the
AD9709. In interleaved mode, the digital input stream at Port 1
contains the I and the Q information in alternating digital words.
Using IQSEL and IQRESET, the AD9709 can be synchronized
to the I and Q data streams. The internal timing of the AD9709
routes the selected I and Q data to the correct DAC output. In
interleaved mode, if no interpolation filter precedes the AD9709,
the symbol rate is half that of the system clock driving the digital
data stream and the IQWRT and IQCLK pins on the AD9709.
AD9709
EVALUATION BOARD
transformer coupled, resistor terminated, and single-ended and
differential outputs. The digital inputs can be used in dual port
or interleaved mode and are designed to be driven from various
word generators, with the on-board option to add a resistor
network for proper load termination. When operating the
AD9709, best performance is obtained when running the digital
supply (DVDD1/DVDD2) at 3.3 V and the analog supply
(AVDD) at 5 V.
GENERAL DESCRIPTION
The AD9709-EB is an evaluation board for the AD9709 8-bit
dual DAC. Careful attention to layout and circuit design,
combined with a prototyping area, allow the user to easily and
effectively evaluate the AD9709 in any application where high
resolution, high speed conversion is required.
This board allows the user flexibility to operate the AD9709 in
various configurations. Possible output configurations include
SCHEMATICS
DVDDIN
B3
L1
DVDD
BEAD
BAN-JACK
AVDDIN
1
C9
10µF
2 25V
B2
BLK
TP37
BAN-JACK
BLK
TP38
BAN-JACK
BLK
TP39
TP43
BLK
DVDD
L2
AVDD
BEAD
1
B4
C10
10µF
25V
2
BLK
TP40
BAN-JACK
DGND
WHT
TP29
2
1
3
A B
JP16
JP5
A 2B
2
2
1
DVDD
WHT
TP31
JP4
A 2B
1
I
DGND; 3, 4, 5
WHT
TP32
1
DGND; 3, 4, 5
1
2
1
R1
50Ω
2
1
R2
50Ω
2
R3
50Ω
1
2
JP1
I
J
1
AGND
10
U1
Q
5
11
13
CLK
2
DVDD
K
CLR
15
3
C
JP3
A2 B
C8
0.01µF
3
PRE
3
C
I
2
A B
JP2
3
1
C7
0.1µF
PRE
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1
DGND; 3, 4, 5
WRT2 S4
IQSEL
1
4
WHT
TP30
CLK2 S3
RESET
BLK
TP42
JP6
DCLKIN2
DGND; 3, 4, 5
CLK1 S2
IQCLK
BLK
TP41
TP44
BLK
JP9
DCLKIN1
WRT1 S1
IQWRT
RED
TP11
Q
6
12
J
9
Q
U2
CLK
7
Q
K
CLR
74HC112
14
DGND; 8
DVDD; 16
74HC112
DGND; 8
DVDD; 16
A B
DVDD
1
3
2
JP7
/2 CLOCK DIVIDER
3
WRT1
C
R4
50Ω
CLK1
CLK2
WHT
TP33
WRT2
SLEEP
1
2
SLEEP
R13
50Ω
RP16
R1
22Ω
RCOM
1
2
INP1
R2
22Ω
3
INP2
R3
22Ω
4
INP3
R4
22Ω
5
INP4
R5
22Ω
6
R6
22Ω
7
INP5
INP6
R7
22Ω
8
INP7
R8
22Ω
9
R9
22Ω
RP9
R1
22Ω
RCOM
10
1
INP8
2
R2
22Ω
3
R3
22Ω
4
R4
22Ω
5
R5
22Ω
6
R6
22Ω
7
R7
22Ω
8
INP9 INP10 INP11 INP12 INP13 INP14
R8
22Ω
9
R1
22Ω
1
2
R2
22Ω
3
R3
22Ω
4
R4
22Ω
5
R5
22Ω
6
R6
22Ω
7
R7
22Ω
8
R8
22Ω
9
R9
22Ω
10
10
INCK1
RP10
RCOM
R9
22Ω
RP15
R1
22Ω
RCOM
1
INP23 INP24 INP25 INP26 INP27 INP28 INP29 INP30
2
R2
22Ω
3
R3
22Ω
4
R4
22Ω
5
R5
22Ω
6
R6
22Ω
7
INP31 INP32 INP33 INP34 INP35 INP36
Figure 46. Power Decoupling and Clocks on AD9709 Evaluation Board
Rev. A | Page 24 of 32
R7
22Ω
8
R8
22Ω
9
INCK2
R9
22Ω
10
00606-047
RED
TP10
B1
AD9709
RP3
RP1
RCOM R1
R9
22Ω
P1
P1 1
4
P1
P1 3
6
P1
P1 5
8
P1
P1 7
10
P1
P1 9
12
P1
P1 11
14
P1
P1 13
16
P1
P1 15
18
P1
P1 17
20
P1
P1 19
22
P1
P1 21
24
P1
P1 23
26
P1
P1 25
28
P1
P1 27
30
P1
P1 29
32
P1
P1 31
34
P1
P1 33
36
P1
P1 35
38
P1
P1 37
40
P1
P1 39
INP2
INP3
INP4
INP5
INP6
INP7
INP8
INP9
INP10
INP11
INP12
INP13
INP14
1
16
RP5, 10Ω
3
14
RP5, 10Ω
5
12
RP5, 10Ω
7
10
RP6, 10Ω
1
16
RP6, 10Ω
3
14
RP6, 10Ω
5
12
2
DUTP2
15
DUTP3
RP5, 10Ω
4
DUTP4
13
DUTP5
RP5, 10Ω
6
DUTP6
11
DUTP7
RP5, 10Ω
8
DUTP8
9
DUTP9
RP6, 10Ω
2
DUTP10
15
DUTP11
RP6, 10Ω
4
DUTP12
13
DUTP13
RP6, 10Ω
DUTP14
11
RP6, 10Ω
INCK1
8
DCLKIN1
9
RP2
R9
P2 1
P2 3
6
P2
P2 5
8
P2
P2 7
10
P2
P2 9
12
P2
P2 11
14
P2
P2 13
16
P2
P2 15
18
P2
P2 17
20
P2
P2 19
22
P2
P2 21
24
P2
P2 23
26
P2
P2 25
28
P2
P2 27
30
P2
P2 29
32
P2
P2 31
34
P2
P2 33
36
P2
P2 35
38
P2
P2 37
40
P2
P2 39
INP24
INP25
INP26
INP27
INP28
INP29
INP30
INP31
INP32
INP33
INP34
INP35
INP36
RP12
RCOM R1
22Ω
1
16
RP7, 10Ω
3
14
RP7, 10Ω
5
12
RP7, 10Ω
7
10
RP8, 10Ω
1
16
RP8, 10Ω
3
14
RP8, 10Ω
5
12
2 3 4 5 6 7 8 9 10
DVDD
RP7, 10Ω
R9
33Ω
1
2 3 4 5 6 7 8 9 10
1
2
15
DUTP30
9
DUTP31
DUTP32
15
DUTP33
DUTP34
13
DUTP35
RP8, 10Ω
DUTP36
11
RP8, 10Ω
8
DUTP24
DUTP29
RP8, 10Ω
4
DUTP23
DUTP28
RP8, 10Ω
2
2 3 4 5 6 7 8 9 10
DUTP27
11
RP7, 10Ω
8
1
DUTP26
13
RP7, 10Ω
6
R9
33Ω
DUTP25
RP7, 10Ω
4
2 3 4 5 6 7 8 9 10
RCOM R1
DVDD
RP7, 10Ω
6
INCK2
R9
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1
P2
RP14
RCOM R1
22Ω
P2
2 3 4 5 6 7 8 9 10
1
DUTP1
RCOM R1
4
2 3 4 5 6 7 8 9 10
1
R9
33Ω
DVDD
RP4
2
RCOM R1
RP5, 10Ω
6
INP23
R9
33Ω
2 3 4 5 6 7 8 9 10
1
RP11
RCOM R1
DCLKIN2
9
SPARES
RP5, 10Ω
7
10
RP8, 10Ω
7
10
Figure 47. Digital Input Signal Conditioning
Rev. A | Page 25 of 32
00606-048
2
DVDD
RP5, 10Ω
R9
22Ω
2 3 4 5 6 7 8 9 10
1
INP1
RP13
RCOM R1
AD9709
BL1
TP34
WHT
1
C1
2 VAL
1
C2
2 0.01µF
ACOM
JP15
DVDD
C3
0.1µF
2
AVDD
1
2
1
NC = 5
3
2
R11
VAL
3
A B
1
DUTP1
1
DB7P1 (MSB)
MODE 48
DUTP2
2
DB6P1
AVDD 47
DUTP3
3
DB5P1
IOUTA1 46
DUTP4
4
DB4P1
IOUTB1 45
DUTP5
5
DB3P1
DUTP6
6
DB2P1
REFIO 43
DUTP7
7
DB1P1
GAINCTRL 42
DUTP8
DUTP9
DUTP10
2
1:1
DB0P1
9
NC
IOUTB2 40
10 NC
IOUTA2 39
6
BL2
3
A B
1
2
C4 2
10pF 1
2
R6
50Ω
C5 2
10pF 1
TP45
WHT
R9
1.92kΩ
1
1
2
C17
22nF
1
2
R10
1.92kΩ
C15 2
11 NC
DUTP12
12 NC
SLEEP 37
DUTP13
13 NC
NC 36
DUTP36
DUTP14
14 NC
NC 35
DUTP35
15 DCOM1
NC 34
DUTP34
16 DVDD1
NC 33
DUTP33
17 WRT1/IQWRT
NC 32
DUTP32
ACOM 38
SLEEP
CLK1
18 CLK1/IQCLK
NC 31
DUTP31
CLK2
19 CLK2/IQRESET
DB0P2 30
DUTP30
WRT2
20 WRT2/IQSEL
DB1P2 29
DUTP29
21 DCOM2
DB2P2 28
DUTP28
DB3P2 27
DUTP27
22 DVDD2
1
C16
22nF
DUTP11
WRT1
R5
50Ω
FSADJ2 41
U2
S6
OUT1
T1
FSADJ1 44
8
AGND; 3, 4, 5
1
MODE
JP8
DVDD
4
1
C6 2
10pF 1
10pF 1
1
2
R7
50Ω
1
2
R8
50Ω
2
R15
256Ω
1
REFIO
TP36
WHT
2
R14
256Ω
1
1
C14
2 0.1µF
2
JP10
2
WHT
TP46
BL3
TP35
WHT
3
R12
VAL
2
NC = 5
4
AGND; 3, 4, 5
1:1
1
S11
OUT2
6
T2
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DUTP23
23 DB7P2 (MSB)
DB4P2 26
DUTP26
DUTP24
24 DB6P2
DB5P2 25
DUTP25
BL4
AVDD
C11
2 1µF
1
C12
2 0.01µF
1
C13
2 0.1µF
NC = NO CONNECT
Figure 48. AD9709 and Output Signal Conditioning
Rev. A | Page 26 of 32
00606-049
1
AD9709
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00606-050
EVALUATION BOARD LAYOUT
00606-051
Figure 49. Assembly, Top Side
Figure 50. Assembly, Bottom Side
Rev. A | Page 27 of 32
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00606-052
AD9709
00606-053
Figure 51. Layer 1, Top Side
Figure 52. Layer 2, Ground Plane
Rev. A | Page 28 of 32
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00606-054
AD9709
00606-055
Figure 53. Layer 3, Power Plane
Figure 54. Layer 4, Bottom Side
Rev. A | Page 29 of 32
AD9709
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
0.15
0.05
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
VIEW A
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
24
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
051706-A
0.75
0.60
0.45
Figure 55. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9709AST
AD9709ASTRL
AD9709ASTZ 1
AD9709ASTZRL1
AD9709-EB
1
Z = RoHS Compliant Part.
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
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Rev. A | Page 30 of 32
Package Option
ST-48
ST-48
ST-48
ST-48
AD9709
NOTES
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Rev. A | Page 31 of 32
AD9709
NOTES
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©2000–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00606-0-1/08(A)
Rev. A | Page 32 of 32