Download DN-103 Controlling a -5V Rail Using UCC2913 +3V to +8V Hot-Swap Power Manager

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Transcript
DN-103
Design Note
Controlling a –5V Rail Using the UCC3919, +3V to +8V Hot Swap Power Manager
By Dave Olson
Fig. 1 shows the UCC3919 configured to control a
–5V rail using low side (ground side) current sensing. As shown in fig 1, a positive 5V is established
across the UCC3919 by connecting the IC’s VDD
pin to the interface ground or return lead, and the
IC’s GND pin to the –5V input. Using low side current sensing maintains the proper input common
mode voltage range on the internal Linear Current
Amplifier and Overcurrent comparators and therefore allows direct connection from the sense resistor to the CSP and CSN pins. The external
n-channel MOSFET should be placed between the
load and the input source (–5V) to provide adequate gate drive voltage when the load is switched
on.
This design note is intended to show the hot swap
designer how to control a –5V rail using a
UCC3919 Hot Swap Power Manager. The technique shown could also be applied using other
positive Hot Swap Power Managers. Two circuit
configurations are presented, one for systems with
independent ground returns that will allow low side
current sensing, and one for systems employing a
common ground plane that require high side current sensing.
RSENSE
CBYPASS
0.1µF
R1
13
–5VIN
1
14
IMAX
R2
CPUMP
0.1µF
12
2
IBIAS
4
CAP
5
L/R
6
SD
7
FLT
UCC3919N
N/C
3
CT
8
LOAD
CT
GATE 10
–5VIN
RPL
GND
PLIM
9
11
–5VIN
Figure 1. Controlling a –5V Rail with the UCC3919 with low side current sensing.
07/99
www.BDTIC.com/TI
UDG-99122
DN-103
shift circuitry will be required to interface the SD,
L/R and FLT pins to standard 5V logic. Possible
level shift circuits for interfacing to the SD, L/R,
and FLT pins are shown in Fig. 3.
Fig. 2 shows the UCC3919 configured to control a
–5V rail using high side (source side) current sensing. Because the voltage on the sense resistor is
outside the acceptable common mode input range
of the internal Linear Current Amplifier, level shift
circuitry must be used. The current is sensed differentially using a low offset, rail-to rail input/output,
op amp. The op amp translates the current sensed
in the –5V rail to a voltage level in the common
mode range of the internal Linear Current Amplifier
for direct comparison to the IMAX pin. To minimize
errors associated with the differential amplifier precision resistors should be used. Using 0.1% tolerance resistors provides a 9.5% RSS tolerance on
the sensed current at VSENSE = 50mV.
In either circuit configuration all IC or hot swap
functions are maintained. However, operation of
the power limit function changes slightly. Note that
the voltage on RPL is fixed at –5V regardless of the
voltage across the load. Therefore, the additional
current injected into the fault timer capacitance will
always be fixed at IPL= VIN/RPL. Equations (15)
and (16) in the UCC3919 datasheet should use
this value of IPL in place of IPL(avg) listed on the
datasheet. All other equations presented in the
data sheet are valid.
It is important that the components and signal inputs which interface to the UCC3919 keep their
correct voltage reference with respect to the IC. In
other words, components referenced to the IC’s
GND pin should remain referenced to the IC’s GND
pin and components normally referenced to VDD
should remain referenced to the VDD pin. Level
Please Note: The UCC3919 is not a floating Hot
Swap Power Manager, absolute maximum voltage ratings must be adhered to.
For complete details about the operation of the
UCC3919 Hot Swap Power Manager , please refer to
the UCC3919 Data Sheet and the UCC3919 Application
Note.
CBYPASS
0.1µF
R1
–5VIN
13
1
IMAX
2
IBIAS
4
CAP
5
L/R
14
R2
CPUMP
UCC3919N
12
N/C
3
CT
8
LOAD
CT
IRF7413
GATE 10
6
SD
7
FLT
–5VIN
100k
RPL
GND
PLIM
11
9
100k
RSense
0.05
–
+
100k
V+
V–
100k
–5VIN
Figure 2: Controlling a –5V rail using the UCC3919 with high side current sensing.
www.BDTIC.com/TI
2
UDG-99123
DN-103
LOCAL
VDD (+5V)
100K
VDD
FLTOUT
SYSTEM CONTROL
LOGIC
+5V
100K
100K
6/7
SD
L/R
7
FLT
100K
–5VIN
UDG-9912
Figure 3: Level shift circuitry for interfacing to the SD, FLT, and L/R pins.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
www.BDTIC.com/TI
3
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