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Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning AD10465 FEATURES The AD10465 uses innovative high density circuit design and laser trimmed, thin film resistor networks to achieve exceptional matching and performance, while still maintaining excellent isolation and providing for significant board area savings. Dual, 65 MSPS minimum sample rate Channel-to-channel matching, ±0.5% gain error Channel-to-channel isolation, >90 dB DC-coupled signal conditioning included Selectable bipolar input voltage range (±0.5 V, ±1.0 V, ±2.0 V) Gain flatness up to 25 MHz: <0.2 dB 80 dB spurious-free dynamic range Twos complement output format 3.3 V or 5 V CMOS-compatible output levels 1.75 W per channel Industrial and military grade The AD10465 operates with ±5.0 V supplies for the analog signal conditioning with a separate 5.0 V supply for the analogto-digital conversion and 3.3 V digital supply for the output stage. Each channel is completely independent, allowing operation with independent encode and analog inputs. The AD10465 also offers the user a choice of analog input signal ranges to further minimize additional external signal conditioning, while remaining general-purpose. APPLICATIONS The AD10465 is packaged in a 68-lead ceramic leaded chip carrier package, footprint-compatible with the earlier generation AD10242 (12-bit, 40 MSPS) and AD10265 (12-bit, 65 MSPS). Manufacturing is done on the Analog Devices Mil38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (−40°C to +85°C). The AD6644 internal components are manufactured on Analog Devices’ high speed complementary bipolar process (XFCB). Phased array receivers Communications receivers FLIR processing Secure communications GPS antijamming receivers Multichannel, multimode receivers www.BDTIC.com/ADI GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD10465 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. The module includes two wide dynamic range AD6644 ADCs. Each AD6644 has a dc-coupled amplifier front end including an AD8037 low distortion, high bandwidth amplifier that provides high input impedance and gain and drives the AD8138 singleto-differential amplifier. The AD6644s have on-chip track-andhold circuitry and utilize an innovative multipass architecture to achieve 14-bit, 65 MSPS performance. 1. Guaranteed sample rate of 65 MSPS. 2. Input amplitude options, user configurable. 3. Input signal conditioning included; both channels matched for gain. 4. Fully tested/characterized performance. 5. Footprint-compatible family; 68-lead CLCC package. FUNCTIONAL BLOCK DIAGRAM AINA3 AINA2 AINA1 8 7 REF_A 6 AINB3 AINB2 AINB1 3 64 63 62 DRAOUT 12 D0A (LSB) 15 D2A 17 D3A 18 AD10465 D4A 19 TIMING D5A 20 D6A 21 D7A 22 11 VREF DROUT VREF DROUT 14 14 D8A 23 TIMING D10A 25 28 OUTPUT BUFFERING 9 OUTPUT BUFFERING 3 D9A 24 29 ENCODEA ENCODEA 31 32 5 33 34 35 36 D11 D12A D13A (MSBA) D0B (LSBB) D1B D2B 37 38 39 D3B D4B D5B 40 41 D6B D7B 42 D8B 56 REF_B 55 DRBOUT 52 ENCODEB 51 ENCODEB 49 D13B (MSBB) 48 D12B 47 D11B 46 D10B 45 D9B 02356-001 D1A 16 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD10465 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 12 Applications....................................................................................... 1 Using the Flexible Input ............................................................ 12 General Description ......................................................................... 1 Applying the AD10465 .................................................................. 13 Product Highlights ....................................................................... 1 Encoding the AD10465 ............................................................. 13 Functional Block Diagram .............................................................. 1 Jitter Considerations .................................................................. 13 Revision History ............................................................................... 2 Power Supplies ............................................................................ 14 Specifications..................................................................................... 3 Output Loading .......................................................................... 14 Test Circuits....................................................................................... 6 Layout Information.................................................................... 14 Absolute Maximum Ratings............................................................ 7 Evaluation Board ............................................................................ 15 ESD Caution.................................................................................. 7 Bill Of Materials List for AD10465 Evaluation Board........... 19 Pin Configuration and Pin Function Descriptions...................... 8 Silkscreens ................................................................................... 20 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 24 Terminology .................................................................................... 11 Ordering Guide .......................................................................... 24 www.BDTIC.com/ADI REVISION HISTORY 3/06—Rev. 0 to Rev. A Remove AZ Grade ..............................................................Universal Changes to General Description Section ...................................... 1 Changes to Table 1............................................................................ 3 Inserted Test Circuits Section ......................................................... 6 Updates to Ordering Guide........................................................... 24 2001—Revision 0: Initial Version Rev. A | Page 2 of 24 AD10465 SPECIFICATIONS AVCC = +5 V; AVEE = –5 V; DVCC = 3.3 V applies to each ADC, unless otherwise noted. All specifications guaranteed within 100 ms of initial power-up, regardless of sequencing. Table 1. Parameter RESOLUTION DC ACCURACY No Missing Codes Offset Error Offset Error Channel Match Gain Error 2 Gain Error Channel Match ANALOG INPUT (AIN) Input Voltage Range AIN1 AIN2 AIN3 Input Resistance AIN1 AIN2 AIN3 Input Capacitance 3 Analog Input Bandwidth 4 ENCODE INPUT (ENC, ENC) 5 Differential Input Voltage Differential Input Resistance Differential Input Capacitance SWITCHING PERFORMANCE Maximum Conversion Rate 6 Minimum Conversion Rate6 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulse Width High ENCODE Pulse Width Low Output Delay (tOD) ENCODE, Rising to Data Ready, Rising Delay (TE_DR) SNR 7 Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Temp Test 1 Level Mil Subgroup Full 25°C Full Full 25°C Full 25°C Max Min VI I VI V I VI I I I 1, 2, 3 1 2, 3 Full Full Full V V V 1 2, 3 1 2 3 Min −2.2 −2.2 −1 −3 −5 −1.5 −3 −5 AD10465BZ/QML-H Typ Max 14 Guaranteed ±0.02 ±1.0 ±1.0 −1.0 ±2.0 ±0.5 ±1.0 +2.2 +2.2 +1 +1 +5 +1.5 +3 +5 ±0.5 ±1.0 ±2 Analog Input @ 19.5 MHz Analog Input @ 32.1 MHz IV IV IV IV V Full 25°C 25°C IV V V Full Full 25°C 25°C 25°C 25°C 25°C Full Full VI V V IV V IV IV V 25°C 25°C Full 25°C Full 25°C Full V I II I II I II 12 12 12 12 99 198 396 0 100 200 400 4.0 100 101 202 404 7.0 0.4 65 20 12 12 12 6.2 6.2 4 5, 6 4 5, 6 4 5, 6 69 68 68 67 67 67 Rev. A | Page 3 of 24 1.5 250 0.3 7.7 7.7 6.8 11.5 70 70 70 70 70 69 69 Ω Ω Ω pF MHz V p-p kΩ pF 10 2.5 4, 5, 6 12 % FS % FS % % FS % FS % % % V V V www.BDTIC.com/ADI Full Full Full 25°C Full Unit Bits 500 9.2 9.2 MSPS MSPS ns ps ps rms ns ns ns ns dBFS dBFS dBFS dBFS dBFS dBFS dBFS AD10465 Parameter SINAD 8 Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 19.5 MHz Analog Input @ 32.1 MHz SPURIOUS-FREE DYNAMIC RANGE 9 Analog Input @ 4.98 MHz Analog Input @ 9.9 MHz Analog Input @ 19.5 MHz Analog Input @ 32.1 MHz TWO-TONE IMD REJECTION 10 fIN = 10 MHz and 11 MHz f1 and f2 are −7 dB fIN = 31 MHz and 32 MHz f1 and f2 Are −7 dB CHANNEL-TO-CHANNEL ISOLATION 11 TRANSIENT RESPONSE OVERVOLTAGE RECOVERY TIME VIN = 2.0 × fS VIN = 4.0 × fS DIGITAL OUTPUTS 12 Logic Compatibility DVCC = 3.3 V Logic 1 Voltage Logic 0 Voltage DVCC = 5 V Logic 1 Voltage Logic 0 Voltage Output Coding POWER SUPPLY AVCC Supply Voltage 13 I (AVCC) Current AVEE Supply Voltage13 I (AVEE) Current DVCC Supply Voltage13 I (DVCC) Current ICC (Total) Supply Current per Channel Power Dissipation (Total) Power Supply Rejection Ratio (PSRR) Passband Ripple to 10 MHz Passband Ripple to 25 MHz Temp Test 1 Level Mil Subgroup Min 25°C 25°C Full 25°C Full 25°C Full V I II I II I II 4 5, 6 4 5, 6 4 5, 6 67.5 67.5 65 65 60 58 70 69 69 68 68 63 61 dB dB dB dB dB dB dB 25°C 25°C Full 25°C Full 25°C Full V I II I II I II 4 5, 6 4 5, 6 4 5, 6 73 70 72 70 62 60 85 82 82 78 78 68 66 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 25°C 4 5, 6 4 5, 6 12 78 78 68 60 87 25°C Full 25°C 25°C I II I II IV V dBFS dBFS dBFS dBFS dB ns Full Full IV IV 12 12 AD10465BZ/QML-H Typ Max 70 90 15.3 Unit www.BDTIC.com/ADI 40 150 100 200 ns ns 0.5 V V CMOS Full Full I I Full Full V V Full Full Full Full Full Full Full Full Full VI I VI V VI V I I V V V 1, 2, 3 1, 2, 3 2.5 DVCC − 0.2 0.2 DVCC − 0.3 0.35 Twos complement 4.85 −5.25 3.135 1, 2, 3 1, 2, 3 Rev. A | Page 4 of 24 5.0 270 −5.0 38 3.3 30 338 3.5 0.02 0.1 0.2 5.25 308 −4.75 49 3.465 46 403 3.9 V V V mA V mA V mA mA W % FSR/% VS dB dB AD10465 1 See Table 3. Gain tests are performed on AIN1 input voltage range. 3 Input capacitance specification combines AD8037 die capacitance and ceramic package capacitance. 4 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 5 All ac specifications tested by driving ENCODE and ENCODE differentially. 6 Minimum and maximum conversion rates allow for variation in encode duty cycle of 50% ± 5%. 7 Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). ENCODE = 65 MSPS. SNR is reported in dBFS, related back to converter full power. 8 Analog input signal power at –1 dBFS. Signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. ENCODE = 65 MSPS. 9 Analog input signal power swept from −1 dBFS to −60 dBFS; SFDR is the ratio of converter full scale to worst spur. 10 Both input tones at −7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermodulation product. 11 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel. 12 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads > 10 pF degrade performance. 13 Supply voltage recommended operating range. AVCC can be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. 2 www.BDTIC.com/ADI Rev. A | Page 5 of 24 AD10465 TEST CIRCUITS tA N+3 N AIN N+1 N+2 tENC tENCH N ENC, ENC N+4 tENCL N+1 N+2 N+3 N+4 tOD tE, DR D[13:0] N–2 N–1 N 02356-015 N–3 DRY Figure 2. Timing Diagram AVIN3 DVCC 200Ω AVIN2 CURRENT MIRROR 100Ω TO AD8037 AVIN1 02356-016 100Ω DVCC www.BDTIC.com/ADI Figure 3. Analog Input Stage VREF DR_OUT LOADS AVCC AVCC AVCC AVCC 10kΩ ENCODE CURRENT MIRROR ENCODE 10kΩ 02356-018 10kΩ 10kΩ DVCC Figure 4. ENCODE Inputs CURRENT MIRROR DVCC VREF 100Ω CURRENT MIRROR Figure 6. Digital Output Stage Rev. A | Page 6 of 24 D0 TO D13 02356-019 LOADS 02356-017 Figure 5. Digital Output Stage AD10465 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter ELECTRICAL VCC Voltage VEE Voltage Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) ENCODE, ENCODE Differential Voltage Digital Output Current ENVIRONMENTAL1 Operating Temperature Range (Case) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Min Max Units 0 –7 VEE −10 0 +7 0 VCC +10 VCC 4 +10 V V V mA V V mA +85 174 300 +150 °C °C °C °C −10 −40 −65 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Test Levels Level I II III IV 1 Typical thermal impedance for 68-lead CLCC package: θJC = 2.2°C/W; θJA = 24.3°C/W. V VI Description 100% production tested. 100% production tested at 25°C, and sample tested at specified temperatures. AC testing done on sample basis. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25°C, sample tested at temperature extremes. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. www.BDTIC.com/ADI Rev. A | Page 7 of 24 AD10465 2 AGNDA 10 AGNDB AINB2 1 68 67 66 65 64 63 62 61 3 AINB1 4 AGNDB AINB3 5 AVCC SHIELD AGNDB 6 AVEE AGNDA REF_A AGNDA 7 AINA1 8 AGNDA 9 AINA2 AGNDA AINA3 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS 60 AGNDB PIN 1 IDENTIFIER AGNDA 11 59 AGNDB DRAOUT 12 AVEE 13 58 AGNDB 57 AGNDB AVCC 14 56 REF_B D0A (LSBA) 15 55 DRBOUT D1A 16 D2A 17 AD10465 D3A 18 TOP VIEW (Not to Scale) D4A 19 54 AGNDB 53 AGNDB 52 ENCODEB 51 ENCODEB D5A 20 50 DVCC D6A 21 49 D13B (MSBB) D7A 22 48 D12B D8A 23 47 D11B D9A 24 46 D10B D10A 25 45 D9B DGNDA 26 44 DGNDB 02356-002 DGNDB D8B D7B D6B D5B D3B D4B D2B D1B D0B (LSBB) D12A D13A (MSBA) DVCC D11A DGNDA ENCODEA ENCODEA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Figure 7. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2, 4, 5, 9 to11 www.BDTIC.com/ADI Mnemonic SHIELD AGNDA 3 6 7 8 12 13 14 26, 27 15 to 25, 31 to 33 28 29 30 43, 44 34 to 42, 45 to 49 53, 54, 57 to 61, 65, 68 REF_A AINA1 AINA2 AINA3 DRAOUT AVEE AVCC DGNDA D0A to D13A ENCODEA ENCODEA DVCC DGNDB D0B to D13B AGNDB 50 51 52 55 56 62 63 64 66 67 DVCC ENCODEB ENCODEB DRBOUT REF_B AINB1 AINB2 AINB3 AVCC AVEE Description Internal Ground Shield Between Channels. A Channel Analog Ground. A ground and B ground should be connected as close to the device as possible. A Channel Internal Voltage Reference. Analog Input for A Side ADC (Nominally ±0.5 V). Analog Input for A Side ADC (Nominally ±1.0 V). Analog Input for A Side ADC (Nominally ±2.0 V). Data Ready A Output. Analog Negative Supply Voltage (Nominally −5.0 V or −5.2 V). Analog Positive Supply Voltage (Nominally 5.0 V). A Channel Digital Ground. Digital Outputs for ADC A. D0A (LSBA). Complement of ENCODE. Data Conversion Initiated on Rising Edge of ENCODE Input. Digital Positive Supply Voltage (Nominally 5.0 V or 3.3 V). B Channel Digital Ground. Digital Outputs for ADC B. D0B (LSBB). B Channel Analog Ground. A ground and B ground should be connected as close to the device as possible. Digital Positive Supply Voltage (Nominally 5.0 V or 3.3 V). Data conversion initiated on rising edge of ENCODE input. Complement of ENCODEB. Data Ready B Output. B Channel Internal Voltage Reference. Analog Input for B Side ADC (Nominally ±0.5 V). Analog Input for B Side ADC (Nominally ±1.0 V). Analog Input for B Side ADC (Nominally ±2.0 V). Analog Positive Supply Voltage (Nominally 5.0 V). Analog Negative Supply Voltage (Nominally −5.0 V or −5.2 V). Rev. A | Page 8 of 24 AD10465 TYPICAL PERFORMANCE CHARACTERISTICS –20 –30 –20 –30 –40 –40 –50 –50 –60 –60 –70 –80 –70 –80 3 4 –100 5 –120 –130 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. Single Tone @ 5 MHz Figure 11. Single Tone @ 10 MHz 0 –20 –30 –40 –50 –50 –60 –60 –90 –100 –110 (dB) –40 –80 –70 3 2 6 –80 5 –90 4 0 5 6 –110 –120 –130 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY (MHz) Figure 12. Single Tone @ 25 MHz Figure 9. Single Tone @ 20 MHz 100 90 SFDR 80 70 –50 60 2 (–dBc) –40 3 –70 SINAD 50 40 –80 30 5 6 20 4 –110 –120 0 02356-008 –90 –100 02356-005 (dB) 0 ENCODE = 65MSPS –10 A = 32MHz (–1dBFS) IN –20 SNR = 70.22 SFDR = 66.40dBc –30 –60 4 –100 FREQUENCY (MHz) –130 2 www.BDTIC.com/ADI 3 –120 –130 ENCODE = 65MSPS AIN = 25MHz (–1dBFS) SNR = 70.36 SFDR = 74.58dBc –10 02356-004 (dB) 0 ENCODE = 65MSPS –10 A = 20MHz (–1dBFS) IN SNR = 70.71 –20 SFDR = 79.73dBc –30 –70 3 4 –110 02356-003 –120 5 6 –100 –110 0 2 –90 6 02356-006 2 –90 –130 ENCODE = 65MSPS AIN = 10MHz (–1dBFS) SNR = 70.79 SFDR = 86.06dBc –10 (dB) (dB) 0 ENCODE = 65MSPS AIN = 5MHz (–1dBFS) SNR = 71.02 SFDR = 92.11dBc 02356-007 0 –10 10 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 4.9898 9.989 19.000 INPUT FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. SFDR and SINAD vs. Frequency Figure 10. Single Tone @ 32 MHz Rev. A | Page 9 of 24 32.000 AD10465 –20 –30 –20 –30 –40 –40 –50 –50 –60 –60 –70 –80 F2– –90 F1 2F1+ F2 F1+ F2 2F2– F1 2F1– F2 2F2+ F1 –90 –110 02356-009 –100 –120 –130 0 2F2– F1 F1+ F2 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY (MHz) FREQUENCY (MHz) Figure 14. Two Tone @ 9 MHz and 10 MHz Figure 17. Two Tone @ 17 MHz and 18 MHz 3 ENCODE = 65MSPS DNL MAX = +0.549 LSB DNL MIN = –0.549 LSB 2.5 2F1– F2 –120 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 3.0 2F1+ F2 F2– F1 –80 –110 0 2F2+ F1 –70 –100 –130 ENCODE = 65MSPS AIN = 17MHz AND 18MHz (–7dBFS) SFDR = 77.68dBc –10 (dB) (dB) 0 ENCODE = 65MSPS AIN = 9MHz AND 10MHz (–7dBFS) SFDR = 82.83dBc 02356-012 0 –10 ENCODE = 65MSPS INL MAX = +1.173 LSB INL MIN = –1.332 LSB 2 2.0 1 (LSB) 1.0 0.5 –1 0 www.BDTIC.com/ADI –2 02356-010 –0.5 –1.0 0 0 2048 4096 6144 8192 10240 12288 14336 –3 16384 0 2048 4096 6144 CODES 12288 14336 16384 Figure 18. Integral Nonlinearity 0 72.0 –1 71.5 –2 71.0 SNR FULL SCALE –3 –4 –5 –6 –7 –40°C 70.5 +25°C 70.0 +85°C 69.5 69.0 68.5 –9 4.2 7.4 10.6 13.8 17.0 20.2 23.4 26.6 29.8 33.0 68.0 67.5 02356-014 –8 02356-011 (dBFS) 10240 CODES Figure 15. Differential Nonlinearity –10 1.0 8192 02356-013 (LSB) 1.5 5 10 19 AIN (MHz) FREQUENCY (MHz) Figure 16. Gain Flatness Figure 19. SNR vs. AIN Frequency Rev. A | Page 10 of 24 32 AD10465 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between a differential crossing of ENCODE and ENCODE, and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE, and the time when all output data bits are within valid logic levels. Overvoltage Recovery Time The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. ENCODE Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable encode duty cycle. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Can be reported in dB (that is, relative to signal level) or in dBFS (always related back to converter full scale). Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Signal-to-Noise Ratio (Without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Can be reported in dB (that is, relative to signal level) or in dBFS (always related back to converter full scale). www.BDTIC.com/ADI Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed, above which converter performance can degrade. Spurious-Free Dynamic Range The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. Transient Response The time required for the converter to achieve 0.03% accuracy when a one-half, full-scale step function is applied to the analog input. Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBFS. Rev. A | Page 11 of 24 AD10465 THEORY OF OPERATION The AD10465 is a high dynamic range, 14-bit, 65 MHz pipeline delay (three pipelines) analog-to-digital converter. The custom analog input section maintains the same input ranges (1 V p-p, 2 V p-p, and 4 V p-p) and input impedance (100 Ω, 200 Ω, and 400 Ω) as the AD10242. The AD10465 employs four monolithic Analog Devices components per channel (AD8037, AD8138, AD8031, and AD6644), along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 14-bit analog-to-digital converter. The input signal is passed through a precision laser trimmed resistor divider allowing the user to externally select operation with a full-scale signal of ±0.5 V, ±1.0 V, or ±2.0 V by choosing the proper input terminal for the application. The AD10465 analog input includes an AD8037 amplifier featuring an innovative architecture that maximizes the dynamic range capability on the amplifiers inputs and outputs. The AD8037 amplifier provides a high input impedance and gain for driving the AD8138 in a single-ended to differential amplifier configuration. The AD8138 has a −3 dB bandwidth at 300 MHz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier. The AD8138 differential outputs help balance the differential inputs to the AD6644, maximizing the performance of the ADC. The AD6644 has complementary analog input pins, AIN and AIN. Each analog input is centered at 2.4 V and should swing ±0.55 V around this reference. Since AIN and AIN are 180° out of phase, the differential analog input signal is 2.2 V peak-topeak. Both analog inputs are buffered prior to the first trackand-hold, TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is applied to the input of a 5-bit coarse ADC1. The digital output of ADC1 drives 14 bits of precision, which is achieved through laser trimming. The output of DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1. The first residue signal is applied to a second conversion stage consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4. The second DAC requires 10 bits of precision, which is met by the process with no trim. The input to TH5 is a second residue signal generated by subtracting the quantized output of DAC2 from the first residue signal held by TH4. TH5 drives a final 6-bit ADC3. The digital outputs from ADC1, ADC2, and ADC3 are added together and corrected in the digital error correction logic to generate the final output data. The result is a 14-bit parallel digital CMOS-compatible word, coded as twos complement. www.BDTIC.com/ADI The AD8031 provides the buffer for the internal reference of the AD6644. The internal reference voltage of the AD6644 is designed to track the offsets and drifts of the ADC and is used to ensure matching over an extended temperature range of operation. The reference voltage is connected to the output common-mode input on the AD8138. The AD6644 reference voltage sets the output common mode on the AD8138 at 2.4 V, which is the midsupply level for the AD6644. USING THE FLEXIBLE INPUT The AD10465 has been designed with the user’s ease of operation in mind. Multiple input configurations have been included on board to allow the user a choice of input signal levels and input impedance. While the standard inputs are ±0.5 V, ±1.0 V, and ±2.0 V, the user can select the input impedance of the AD10465 on any input by using the other inputs as alternate locations for GND or an external resistor. Table 5 summarizes the impedance options available at each input location. Table 5. Input Impedance Options Input AIN1 AIN2 AIN3 Impedance 100 Ω 75 Ω 50 Ω 200 Ω 100 Ω 75 Ω 50 Ω 400 Ω 100 Ω 75 Ω 50 Ω Condition When AIN2 and AIN3 are open When AIN3 is shorted to GND When AIN2 is shorted to GND When AIN3 is open When AIN3 is shorted to GND When AIN2 to AIN3 has an external resistor of 300 Ω, with AIN3 shorted to GND When AIN2 to AIN3 has an external resistor of 100 Ω, with AIN3 shorted to GND When AIN3 has an external resistor of 133 Ω to GND When AIN3 has an external resistor of 92 Ω to GND When AIN3 has an external resistor of 57 Ω to GND Rev. A | Page 12 of 24 AD10465 APPLYING THE AD10465 ENCODING THE AD10465 JITTER CONSIDERATIONS The AD10465 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 32 MHz input signals when using a high jitter clock source. See the Analog Devices Application Note AN-501, Aperture Uncertainty and ADC System Performance, for complete details. For optimum performance, the AD10465 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and ENCODE pins via a transformer or capacitors. These pins are biased internally and require no additional bias. The signal-to-noise ratio (SNR) for an ADC can be predicted. When normalized to ADC codes, Equation 1 accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter. Figure 20 shows one preferred method for clocking the AD10465. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The backto-back Schottky diodes across the transformer secondary limit clock excursions into the AD10465 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD10465, and limits the noise presented to the ENCODE inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limiting resistor (typically 100 Ω) is placed in the series with the primary. ⎡ 1+ ε ⎢⎛⎜ N ⎞⎟ + ⎢⎝ 2 ⎠ ⎢ 2 SNR = − 20 × log ⎢(2 × π × f ANALOG × t j rms ) ⎢ 2 ⎢⎛⎜ v NOISE rms ⎞⎟ ⎢⎜ 2 n ⎟ ⎠ ⎣⎝ ⎤ ⎥ ⎥ ⎥ +⎥ ⎥ ⎥ ⎥ ⎦ 1/ 2 (1) where: fANALOG is the analog input frequency. tj rms is the rms jitter of the encode (rms sum of encode source and internal encode circuitry). ε is the average DNL of the ADC (typically 0.50 LSB). www.BDTIC.com/ADI T1-4T ENCODE AD10465 02356-020 ENCODE HSMS2812 DIODES Figure 20. Crystal Clock Oscillator, Differential ENCODE If a low jitter ECL/PECL clock is available, another option is to ac couple a differential ECL/PECL signal to the ENCODE and ENCODE input pins as shown in Figure 21. A device that offers excellent jitter performance is the MC100LVEL16 (or same family) from Motorola. For a 14-bit analog-to-digital converter like the AD10465, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. The chart below shows a family of curves that demonstrates the expected SNR performance of the AD10465 as jitter increases. The chart is derived from Equation 1. For a complete discussion of aperture jitter, please consult the Analog Devices Application Note AN-501, Aperture Uncertainty and ADC System Performance. 71 VT 69 ENCODE AD10465 68 AIN = 10MHz 67 66 65 AIN = 20MHz 64 63 62 RMS CLOCK JITTER (ps) Figure 22. SNR vs. Jitter Rev. A | Page 13 of 24 02356-022 3.9 3.7 3.5 3.3 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 60 3.1 AIN = 32MHz 61 0.1 Figure 21. Differential ECL for ENCODE SNR (dBFS) VT 02356-021 ENCODE 0.9 0.1µF 0.7 ECL/ PECL AIN = 5MHz 70 0.1µF 0.5 0.1nF 100Ω VNOISE rms is the V rms noise referred to the analog input of the ADC (typically 5 LSB). 0.3 CLOCK SOURCE N is the number of bits in the ADC. AD10465 POWER SUPPLIES LAYOUT INFORMATION Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that can be “received” by the AD10465. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 μF chip capacitors. The schematic of the evaluation board (see Figure 24) represents a typical implementation of the AD10465. The pinout of the AD10465 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. It is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. All capacitors can be standard high quality ceramic chip capacitors. The AD10465 has separate digital and analog power supply pins. The analog supplies are denoted AVCC and the digital supply pins are denoted DVCC. AVCC and DVCC should be separate power supplies. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that AVCC must be held within 5% of 5 V. The AD10465 is specified for DVCC = 3.3 V as this is a common supply for digital ASICs. OUTPUT LOADING Care should be taken when placing the digital output runs. Because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. Internal circuitry buffers the outputs of the ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate. Care must be taken when designing the data receivers for the AD10465. The digital outputs drive an internal series resistor (for example, 100 Ω) followed by a gate, such as the 75LCX574. To minimize capacitive loading, there should only be one gate on each output pin. An example of this is shown in the evaluation board schematic shown in Figure 26. The digital outputs of the AD10465 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace has a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷1 ns) of dynamic current per bit flows in or out of the device. A full-scale transition can cause up to 140 mA (14 bits ×10 mA/bit) of current flow through the output stages. These switching currents are confined between ground and the DVCC pin. Standard TTL gates should be avoided because they can appreciably add to the dynamic switching currents of the AD10465. It should also be noted that extra capacitive loading increases output timing and invalidates timing specifications. Digital output timing is guaranteed with 10 pF loads. www.BDTIC.com/ADI Rev. A | Page 14 of 24 AD10465 EVALUATION BOARD The AD10465 evaluation board (Figure 23) is designed to provide optimal performance for evaluation of the AD10465 analog-to-digital converter. The board encompasses everything needed to ensure the highest level of performance for evaluating the AD10465. The board requires an analog input signal, encode clock, and power supply inputs. The clock is buffered on-board to provide clocks for the latches. The digital outputs and clocks are available at the standard 40-pin connectors, Connector J1 and Connector J2. Power to the analog supply pins is connected via banana jacks. The analog supply powers the associated components and the analog section of the AD10465. The digital outputs of the AD10465 are powered via banana jacks with 3.3 V. Contact the factory if additional layout or applications assistance is required. 02356-023 www.BDTIC.com/ADI Figure 23. Evaluation Board Mechanical Layout Rev. A | Page 15 of 24 AD10465 J1 JP5 CLKLATCHB2 AINB3 LATCHB 1 CLKLATCHB1 AGNDB 13 3 2 JP3 J2 U2:A 11 12 74LCX00M AINB2 U2:D 74LCX00M 4 U2:B JP1 BUFLATB JP2 BUFLATA 6 5 74LCX00M DRBOUT DRAOUT AGNDB J22 1 JP4 AINB1 13 3 2 CLKLATCHA1 U4:D 11 12 74LCX00M AGNDB 74LCX00M 4 U4:B 6 5 74LCX00M JP6 CLKLATCHA2 J7 U4:A LATCHA AINA3 AGNDA 47V AT 100MHz L9 –5.2VAB J8 AINA2 47V AT 100MHz L8 47 C59 10µF +5VAB 47 C52 10µF AGNDA DRAOUT L11 +3.3VDA C62 10µF DGNDA 47 AINB1 AINB2 AINB3 +5VAB AGNDA AINA1 AGNDB AINB1 AINB2 +5VAB AGNDB AINB3 AGNDB –5.2VAB SHIELD REFA AGNDA AGNDA AGNDA AINA1 C63 0.1µF DGNDA DRBOUT AGNDB ENCBB ENCB DUT_3.3VDB D13B (MSB) C64 0.1µF D12B D11B D10B D9B L6 47 +3.3VDB C58 10µF DGNDB AGNDB D8B D7B D5B D6B C61 0.1µF DGNDB DUT_3.3VDB 10 C26 0.1µF DUT_3.3VDA SPARE GATE U2:C 9 8 C27 0.1µF 9 74LCX00M DGNDB DGNDB Figure 24. Evaluation Board Rev. A | Page 16 of 24 SPARE GATE U4:C 10 8 74LCX00M DGNDA DGNDA 02356-024 DGNDA D4B D10A D2B D3B D8A D9A D1B D7A D13A D0B D5A D6A AD10465 D12A D4A D11A D3A U1 DUT_+3.3VDA AGNDA D2A ENCA 47 47Ω AT 100MHz D1A 27 DGNDA 28 ENCAB 29 ENCA 30 +3.3VDA 31 D11A 32 D12A 33 D13A (MSB) 34 D0B (LSB) 35 D1B 36 D2B 37 D3B 38 D4B 39 D5B 40 D6B 41 D7B 42 D8B 43 DGNDB L7 C53 10µF 60 AGNDB 59 AGNDB 58 AGNDB 57 AGNDB 56 REFB 55 DRBOUT 54 AGNDB 53 AGNDB 52 ENCBB 51 ENCB 50 +3.3VDB 49 D13B (MSB) 48 D12B 47 D11B 46 D10B 45 D9B 44 DGNDB www.BDTIC.com/ADI +5VAA D0A +5VAA ENCAB AGNDA 10 AGNDA 11 AGNDA 12 DRAOUT 13 –5.2VAA 14 +5VAA 15 D0A (LSB) 16 D1A 17 D2A 18 D3A 19 D4A 20 D5A 21 D6A 22 D7A 23 D8A 24 D9A 25 D10A 26 DGNDA AGNDB 4 3 2 1 68 67 66 65 64 63 62 61 AINA3 9 8 47 C22 10µF AINA3 L10 AGNDA AGNDA –5.2VAA 7 6 5 C57 0.1µF AGNDA AINA2 AINA1 AINA2 AGNDB J20 AD10465 +5VAA U6 2 6 +5VAA ADP3330 IN OUT NR SD ERR 1 C45 100pF 8 3 AGNDA GND C42 0.1µF J6 4 JP11 OPEN ENCODEA AGNDA R140 33kΩ R82 51Ω 1 2 C40 0.1µF 3 ENCODEA AGNDA C44 0.1µF U7 AGNDA J18 AGNDA 4 R83 51Ω JP8 JP7 NC D Q D Q VBB 7 C49 0.1µF 6 ENCA 5 VEE R94 100Ω AGNDA AGNDA +5VAA R89 100Ω C41 0.47µF MC10EP16D NC = NO CONNECT AGNDA ENCAB 8 VCC AGNDA U8 2 ADP3330 IN OUT NR 1 C43 100pF 8 www.BDTIC.com/ADI 6 +5VAA SD ERR 3 AGNDB GND ENCODEB AGNDB R141 33kΩ R76 51Ω 1 2 C39 0.1µF 3 ENCODEB AGNDB AGNDB C48 0.1µF U9 AGNDB J17 4 JP12 OPEN R79 51Ω AGNDB 4 JP10 JP9 NC D D VBB VCC Q Q VEE ENCB 8 7 C46 0.1µF 6 5 MC10EP16D NC = NO CONNECT AGNDB C38 0.47µF AGNDB Figure 25. Evaluation Board Rev. A | Page 17 of 24 R95 100Ω AGNDB ENCBB R97 100Ω 02356-025 C37 0.1µF J16 AD10465 OUT_3.3VDA R117 100Ω OUT_3.3VDA U21 C13 0.1µF C14 0.1µF C15 0.1µF C20 0.1µF LATCHA R98 51Ω +5VAB +5VAA (LSB) D0A R100 0Ω +3.3VDB R99 0Ω +3.3VDA E1 DGNDA D1A D2A D3A D4A D5A E2 D6A E3 D7A D8A E4 D9A E5 D10A D11A E6 D12A (MSB) D13A E7 25 24 DGNDA BANANA JACKS FOR GNDS AND PWRS VCC E8 E9 E10 VCC CP2 VCC OE2 26 I15 27 I14 29 I13 30 I12 32 I11 33 I10 35 I9 36 I8 48 CP1 1 OE1 37 I7 38 I6 40 I5 41 I4 43 I3 44 I2 46 I1 47 I0 28 GND 34 GND 39 GND 45 GND 42 31 O6 O5 O4 R116 100Ω 7 18 VCC 23 O15 22 O14 20 O13 19 O12 17 O11 16 O10 14 O9 13 O8 O7 R115 100Ω 12 11 9 8 6 O3 5 O2 3 O1 2 O0 21 GND 15 GND 18 GND 4 GND R114 100Ω AGNDA –5.2VAA DGNDB 19 18 R105 100Ω 17 16 R104 100Ω 15 14 R106 100Ω 13 R118 51Ω BUFLATA R103 100Ω 12 11 10 9 8 R102 100Ω 20 21 19 22 18 23 17 24 16 25 15 26 14 27 13 28 12 29 11 30 10 31 9 32 8 33 R109 100Ω R108 100Ω R107 100Ω 22 23 24 25 26 27 28 29 30 31 32 33 J3 R110 100Ω R111 100Ω 21 34 34 35 35 36 36 37 37 38 38 39 39 40 40 7 7 6 6 5 5 4 4 3 3 2 2 1 1 R101 100Ω 74LCX163743MTD –5.2VAB 20 R113 100Ω DGNDA www.BDTIC.com/ADI DGNDA DGNDA OUT_3.3VDA R112 100Ω OUT_3.3VDB U22 C25 0.1µF C21 0.1µF C23 0.1µF C24 0.1µF R119 51Ω LATCHB DGNDA E72 E140 E141 E142 E144 E145 E147 E150 E151 E154 E185 E194 E196 E198 E200 E202 E204 E206 E223 E225 AGNDA E162 E163 E164 E165 E166 E171 E172 E177 1E79 E181 E186 E187 E207 E209 E211 E213 E215 E217 E219 E221 E227 E229 E231 E233 AGNDB E159 E160 E161 E167 E168 E169 E170 E178 E180 E182 E183 E191 E192 E193 E208 E210 E212 E214 E216 E218 E220 E222 E228 E230 E232 E234 (LSB) D0B R123 0Ω 25 24 DGNDB E87 E88 E89 E139 E143 E146 E148 E149 E152 E153 E184 E188 E189 E190 E195 E197 E199 E201 E203 E205 E224 E226 VCC R124 D1B 0Ω D2B D3B D4B D5B DGNDB D6B D7B D8B D9B D10B D11B D12B (MSB) D13B VCC CP2 OE2 26 I15 27 I14 29 I13 30 I12 32 I11 33 I10 35 I9 36 I8 48 CP1 1 OE1 37 I7 38 I6 40 I5 41 I4 43 I3 44 I2 46 I1 47 I0 28 GND 34 GND 39 GND 45 GND VCC 42 31 O6 O5 O4 R126 100Ω 7 18 VCC 23 O15 22 O14 20 O13 19 O12 17 O11 16 O10 14 O9 13 O8 O7 R127 100Ω 12 11 9 8 6 O3 5 O2 3 O1 2 O0 21 GND 15 GND 18 GND 4 GND R125 100Ω DGNDB Figure 26. Evaluation Board Rev. A | Page 18 of 24 21 19 22 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 23 18 R128 100Ω R134 100Ω R137 51Ω BUFLATB R135 100Ω R136 100Ω R131 100Ω R132 100Ω R133 100Ω R120 100Ω 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 J4 R121 100Ω R122 100Ω 20 19 R129 100Ω 74LCX163743MTD DGNDB 20 R130 100Ω DGNDB MSB 02356-026 AGNDB MSB AD10465 BILL OF MATERIALS LIST FOR AD10465 EVALUATION BOARD Table 6. Bill of Materials Qty 2 Reference Designator U2, U4 2 U21, U22 1 U1 2 U6, U8 Description IC, low-voltage Quad 2-input nand, SOIC-14 IC, 16-bit transparent latch with three-state outputs, TSSOP-48 DUT, IC 14-bit analog-to-digital converter IC, voltage regulator 3.3 V, RT-6 10 E1 to E10 Banana jack, socket 22 C13 to C15, C20, C21, C23 to C27, C37, C39, C40, C42, C44, C46, C48, C49, C57, C61, C63, C64 C38, C41 C43, C45 J3, J4 L6 to L11 2 2 2 6 2 6 4 2 8 36 8 U7, U9 C22, C52, C53, C58, C59, C62 R99, R100, R123, R124 R140, R141 Value Manufacturer and Part Number Toshiba/TC74LCX00FN Component Name 74LCX00M Fairchild/74LCX163743MTD 74LCX163743MTD ADI/AD10465BZ ADI/AD10465BZ Analog Devices/ADP3330ART3, 3-RLT Johnson Components/080740-001 Mena/GRM40X7R104K025BL ADP3330 Banana Hole 0.1 μF Capacitor, 0.1 μF, 20%, 12 V dc, 0805 0.47 μF 100 pF Vitramon/VJ1206U474MFXMB Johansen/500R15N101JV4 Samtec/TSW-120-08-G-D Fair-Rite/2743019447 CAP 1206 CAP 0805 HD40M IND2 Motorola/MC10EP16D Kemet/T491C106M016A57280 MC10EP16D POLCAP 1812 Panasonic/ERJ-6GEY0R00V Panasonic/ERJ-6GEYJ333V RES2 0805 RES2 0805 51 Ω Capacitor, 0.47 μF, 5%, 12 V dc, 1206 Capacitor, 100 pF, 10%, 12 V dc, 0805 Connector, 40-pin header male Inductor, 47 μH @ 100 MHz, 20%, IND2 IC, differential receiver, SOIC-8 Capacitor, 10 μF, 20%, 16 V dc, 1812POL Resistor, 0.0 Ω, 0805 Resistor, 33,000 Ω, 5%, 0.10 Watt, 0805 Resistor, 51 Ω, 5%, 0.10 Watt, 0805 Panasonic/ERJ-6GEYJ510V 100 Ω Resistor, 100 Ω, 5%, 0.10 Watt, 0805 Panasonic/ERJ-6GEYJ101V RES2 0805, RES 0805 RES2 0805, RES 0805 Connector, SMA female Johnson Components/1420701-201 47 μH 10 μF CAP 0805 www.BDTIC.com/ADI R76, R79, R82, R83, R98, R118, R119, R137 R89, R94, R95, R97, R101 to R117, R120 to R122, R125 to R136 J1, J2, J6 to J8, J16 to J18, J20, J22 0.0 Ω 33,000 Ω Rev. A | Page 19 of 24 SMA AD10465 02356-027 SILKSCREENS www.BDTIC.com/ADI 02356-028 Figure 27. Top Layer Copper Figure 28. Second Layer Copper Rev. A | Page 20 of 24 02356-029 AD10465 Figure 29. Third Layer Copper 02356-030 www.BDTIC.com/ADI Figure 30. Fourth Layer Copper Rev. A | Page 21 of 24 02356-031 AD10465 Figure 31. Fifth Layer Copper 02356-032 www.BDTIC.com/ADI Figure 32. Bottom Layer Copper Rev. A | Page 22 of 24 02356-033 AD10465 Figure 33. Bottom Silkscreen 02356-034 www.BDTIC.com/ADI Figure 34. Bottom Assembly Rev. A | Page 23 of 24 AD10465 OUTLINE DIMENSIONS 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) 0.235 (5.97) MAX 0.960 (24.38) 0.950 (24.13) SQ 0.940 (23.88) 9 61 10 60 PIN 1 TOE DOWN ANGLE 0–8 DEGREES 1.070 (27.18) MIN TOP VIEW 0.800 (20.32) BSC 1.190 (30.23) 1.180 (29.97) SQ 1.170 (29.72) (PINS DOWN) 0.010 (0.254) 44 26 30° 43 27 0.050 (1.27) 0.060 (1.52) 0.050 (1.27) 0.040 (1.02) 0.020 (0.508) DETAIL A ROTATED 90° CCW DETAIL A 0.175 (4.45) MAX 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 35. 68-Lead Ceramic Leaded Chip Carrier [CLCC] (Z-68A) Dimensions shown in inches and (millimeters) www.BDTIC.com/ADI ORDERING GUIDE Model AD10465BZ 2 5962-9961601HXA AD10465/PCB 1 2 Temperature Range 1 −40°C to +85°C −40°C to +85°C Package Description 68-Lead Ceramic Leaded Chip Carrier [CLCC] 68-Lead Ceramic Leaded Chip Carrier [CLCC] Evaluation Board with AD10465BZ Case temperature. Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02356-0-3/06(A) Rev. A | Page 24 of 24 Package Option Z-68A Z-68A