Download A Bio-inspired Ultra-Energy-Efficient Analog-to-Digital Converter for Biomedical Applications

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 11, NOVEMBER 2006
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A Bio-Inspired Ultra-Energy-Efficient
Analog-to-Digital Converter
for Biomedical Applications
Heemin Y. Yang and Rahul Sarpeshkar, Member, IEEE
Abstract—There is an increasing trend in several biomedical
applications such as pulse-oximetry, ECG, PCG, EEG, neural
recording, temperature sensing, and blood pressure for signals to
be sensed in small portable wireless devices. Analog-to-digital converters (ADCs) for such applications only need modest precision
( 8 bits) and modest speed ( 40 kHz) but need to be very energy
efficient. ADCs for implanted medical devices need micropower
operation to run on a small battery for decades. We present a
bio-inspired ADC that uses successive integrate-and-fire operations like spiking neurons to perform analog-to-digital conversion
on its input current. In a 0.18- m subthreshold CMOS implementation, we were able to achieve 8 bits of differential nonlinearlity
limited precision and 7.4 bits of thermal-noise-limited precision at
a 45-kHz sample rate with a total power consumption of 960 nW.
This converter’s net energy efficiency of 0.12 pJ/quantization level
appears to be the best reported so far. The converter is also very
0 021 mm2 ) and can be used in applications
area efficient (
that need several converters in parallel. Its algorithm allows easy
generalization to higher speed applications through interleaving,
to performing polynomial analog computations on its input before
digitization, and to direct time-to-digital conversion of event-based
cardiac or neural signals.
Index Terms—Analog–digital (A/D), bio-inspired, energy efficient, successive subranging, time based, time to digital.
I. INTRODUCTION
HE increasing trend of sensing biomedical signals with
portable electronic devices has created a strong demand
for a new breed of energy-efficient analog-to-digital converters
(ADCs). Portable and wearable medical devices are now capable of detecting biomedical signals in areas such as pulseoximetry, electrocardiography (ECG), and electroencephalography (EEG), to name a few. Many of these applications are now
being integrated into personal area networks (PAN) for wireless health monitoring systems [1], [2]. Therefore, energy-efficient data converters at the front- and back-end of these systems
are playing an important role. Biomedical signals are often very
slow ( 1 kHz) and have limited dynamic range ( 60 dB), but
energy efficiency is paramount in many such systems that need
T
Manuscript received December 15, 2005; revised August 4, 2006. This work
was supported in part by the Office of Naval Research under Grant N0014-02-10434. This paper was recommended by Guest Editor A. G. Andreou.
H. Y. Yang was with Massachusetts Institute of Technology, Cambridge, MA
02139 USA. He is now with Linear Technologies, Milpitas, CA 95035 USA
(e-mail: [email protected]).
R. Sarpeshkar is with the Electrical Engineering Department, Massachusetts
Institute of Technology, Cambridge, MA 02139 USA (e-mail: [email protected]).
Digital Object Identifier 10.1109/TCSI.2006.884463
a long battery life, that are implanted in the body, or that operate
by rectifying small amounts of received RF energy.
A. ADC Requirements
The precision and bandwidth requirements on ADCs for
most biomedical applications are rather modest. While ECG
and EEG systems may require small minimum detectable signals for detecting subtle waveform differences (5 and 0.3 V,
respectively), the necessary dynamic range in a linear system
corresponds to 8 bits and the high-frequency bandwidth requirements range from 100 to 500 Hz [3]. The converter utilized
in the acquisition of cardiac signals in implantable pacemakers
requires only 8 bits of precision at a bandwidth of 250 Hz [4].
Pulse-oximetry systems require 7 bits of precision and 100 Hz
of bandwidth to digitize their outputs if analog preprocessing is
used [5]. Consequently, inherently energy-efficient conversion
techniques that achieve moderate speed and precision may
be used. Recent publications show that most converters with
well-known algorithmic, successive-approximation, and oversampling architectures can achieve a good energy efficiency.
The energy efficiency of a converter is often measured as the
where
energy per quantization level and given by
is the power consumption, is the sample rate, and is the precision of the converter. The energy efficiency of many good converters is near 1 pJ/(quantization level) today. While such converters are adequate in many applications, we were motivated
to see if we could create an ultra-energy-efficient converter with
submicrowatt operation. Such converters are extremely useful in
emerging applications like passive medical RF-ID tags that need
to operate a complete heart monitoring system with 1–10 W
of received-and-rectified RF power; such tags will enable battery-free operation and may be able to operate by rectifying
ambient RF energy in the environment. Implanted medical devices like pacemakers that need to run on small batteries for
10–100 years need microwatt operation and could benefit from
ultra-energy-efficient ADCs as well. Thus, we decided to explore architectures that were less traditional to see if we could
exceed the state-of-the-art in energy efficiency. Interestingly, we
found a possible solution in neurons.
B. Neuronally Inspired ADCs
Since neurons do not perform analog–digital (A/D) conversion per se, it may seem strange to look to nature for clues
on how to perform A/D conversion. However, one needs to realize that A/D conversion is one of the simplest forms of pattern recognition where an analog signal is classified into one of
1057-7122/$20.00 © 2006 IEEE
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 11, NOVEMBER 2006
Fig. 1. Typical set of analog capacitor voltage waveforms and its corresponding
spiking output from a VLSI implementation of our algorithm are shown.
different patterns for bits of precision. Since neurons are
extremely efficient at pattern recognition, a neuronally inspired
A/D architecture has the potential to be very energy efficient;
the 22 billion neurons of the brain consume near 14.6 W of
power [6], with the average neuron consuming approximately
0.5 nW of power. Unfortunately, previously published works
on neuronally inspired ADCs were unable to demonstrate energy-efficient operation. The work presented in [7] approaches
A/D conversion as an optimization problem and uses a network
of analog processors connected with binary-weighted resistors
to minimize the error between the analog input and the quantized estimation. The algorithm presented in [8] uses an integrate-and-fire oscillating neuron with a time-varying threshold
and basis functions. These functions are set such that the period
of the oscillating neuron’s spiking output translates to the quantization level of the input. The input is considered as the initial
condition of the oscillating neuron. The converter presented in
[9] and [10] utilizes two integrate-and-fire neurons with scaled
reference currents to quantize an input current in a successive
subranging and overranging manner. While [9] is one of the few
publications to demonstrate a fully integrated experimental prototype, several sources of error such as charge-injection, current
source mismatches, and comparator delay render its design to
be inefficient. Consequently, none of these neuronally inspired
converters can compete with other traditional architectures because of poor performance.
In this paper, we present an energy-efficient time-based ADC
whose design is inspired by the operation of integrate-and-fire
spiking neurons. Like neurons, the converter uses charging
currents, comparators, and times between comparator events,
expressed as spikes or pulses, to do pattern recognition (see
Fig. 1). The scheme explicitly exploits time as a signal variable including interspike-times to improve efficiency and a
synchronous clock to do many operations such as subtraction
and error cancellation automatically. The scheme is based on
some of our recent prior work [11] where we proposed the first
time-based ADC whose conversion time scaled linearly with
bit precision instead of exponentially. However, that converter
only achieved an energy-efficiency near 1 pJ/quantization level
due to its need to operate at 11 to 12 bits of precision. In this
work, we focus on a converter with a similar algorithm of
operation. However, because of the lower precision requirements for medical applications, it can operate with significantly
less circuitry, lower power-supply voltages, and with more
algorithmic optimizations. Consequently, we were able to
achieve nearly an order-of-magnitude improvement in energy
efficiency, placing the converter, to the best of our knowledge,
as the most energy-efficient ADC reported so far. Our work
suggests that looking to neurons for inspiration on how to
do A/D conversion and other signal-to-symbol conversion
computations may indeed be promising.
This paper is organized as follows. Section II reviews the
algorithm for A/D conversion used in the paper. Section III
describes the circuits used in the converter. Section IV presents
experimental results. Section V presents generalizations of our
algorithm to computational A/Ds that compute a polynomial
function of their input before digitization. Such A/Ds could
be useful in applications like pulse oximetry that need to
calibrate their final oxygen-saturation outputs with empirical
polynomials [12]. Section VI presents our conclusions.
II. ALGORITHM REVIEW
The algorithm consists of two distinct stages and is illustrated in Fig. 2. During the first stage, we calculate the first
two most significant bits (MSBs) in a method similar to that
charges a capacof a dual-slope ADC: The input current
charges
itor for one clock cycle; then, a reference current
another matched capacitor until its voltage equals that of the
first capacitor; the number of clock cycles that elapse during
. The
this charging period yield the first two MSBs of
is
number of elapsed clock cycles can never exceed 4 since
never more than
in our algorithm for maximum conversion efficiency [13]. At the end of the first stage of conversion,
clock cycles in the figure, ena residual time, denoted
. These bits are quantized in
codes the remaining bits of
the second iterative stage of the conversion process described in
the next paragraph. In this example, is positive such that the
residue is greater than a half clock cycle.
overall
,
In the second stage, we first convert the residual time,
into a residual voltage during what we call a time-to-voltage
conversion. Then, we charge another capacitor until it reaches
this residual voltage and repeat the process again such that the
is doubled to
residual time before the clock edge,
after the clock edge. We label this process a
voltage-to-time conversion. In essence, we amplify the residue
” provides
by 2 by doing things twice in time. The “1” in “
quantization information revealing that the previous residue was
is automatically engreater than a half clock cycle, and the
coded as a residue referenced to this clock edge for the next
stage of the conversion. Thus, subtraction of intermediate quantized bits is automatic because they occur as an integer number
of clock edges, and amplified residues are always encoded with
respect to the last seen edge.
The amplification, quantization, and subtraction of the
residue
residues are repeated to obtain successive bits. The
YANG AND SARPESHKAR: BIO-INSPIRED ULTRA-ENERGY EFFICIENT ADC FOR BIOMEDICAL APPLICATIONS
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Fig. 2. Time is normalized with respect to T . The residual time, :
", leading up to the next clock edge is at least as large as one-half the clock period. After
amplification by two and automatic subtraction of the intermediate quantization bit “1, ” the original residue is transformed to a new residue " which is used in
the next stage of conversion.
2
Fig. 4. Wide-output swing OTA with positive feedback and staggered rail voltages was used as our asynchronous comparator.
Fig. 3. Integrating capacitor waveforms and their corresponding spiking outputs for ten interleaved converters.
is converted to a 1– residue by converting the time from the
end of amplification to the next clock edge into a voltage. We
process
can then recursively repeat the
to get successive conversion bits. The overall scheme ensures
correct treatment of all residues whether quantization edges
do or do not occur during amplification. Note that our subtraction-and-amplification routine produces alternating signs in the
residues. Unlike a traditional binary weighted summation, each
successive bit during subranging either adds or subtracts from
the code. Hardware implementation of the conversion from
our binary code to a traditional binary code is straightforward.
Note that during the second stage, we iteratively calculate bits
by performing a subtraction-and-amplification process for each
bit in a manner similar to that of an algorithmic or pipelined
ADC but using time as the signal variable.
A problem common to many time-based algorithms is the
possibility of an infinitesimally small temporal residue [14]. We
can guarantee a minimum residue by integrating for an extra
clock period during the time-to-voltage conversion, a scheme we
algorithm. The amplification process will then not
term the
only amplify the residue but the extra clock cycle as well. We
can digitally subtract the two amplified extra clock cycles with
little overhead. To minimize its impact on the efficiency of the
scheme for the first
converter, we need only implement the
few significant bits: Small errors introduced after lots of stages
of cascaded residue amplification have transpired in later stages
of the conversion have little impact on the overall precision of
the converter.
Our algorithm inherently has error cancellation that makes it
noise, digital
robust to comparator offset, comparator delay,
state-machine delays, and switching charge injection: Whatever
elements “add” error to our signal during time-to-voltage conversion also “subtract” the same error from our signal during
voltage-to-time conversion. For example, a delay in the comparator will reduce the time to the next clock edge, thus decrease the voltage used for comparison in the next phase, and
reduce the time taken after the clock edge to reach this voltage;
however, the comparator delay is now re-added to the smaller
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D
Fig. 5. Output of the comparator
is passed as the input to the pulsewidth control circuit above. The width of the pulse is controlled by two currents,
and
. A state machine resets the pulsewidth circuit with the control signal Reset.
I
timing residue after the clock edge to bring it back to its correct
value. Further details of the error-cancellation mechanism are
presented in [11] and will not be discussed here.
It is worth summarizing the main features of our converter:
Like a dual-slope converter, our converter uses time as an intermediate signal variable as opposed to current or voltage. However, unlike dual-slope converters whose conversion time grows
for
bits of precision), our conversion
exponentially (
time grows linearly with the bit precision, . Our ADC functions like a successive-subranging converter but uses time as an
intermediate signal variable for the gain and subtraction routines. In addition, the converter naturally alleviates errors due
to charge injection, comparator delays and offsets because of
the nature of its algorithm. Since the residual signal information is in time, amplification by 2 is done by doing things twice
in time which allows one to build an amplifying ADC without
an explicit amplifier, thus saving power. Our ADC consists of
two LSB-matched capacitors, a reference current, a comparator
with a finite pulsewidth output, a state machine, and registers.
If higher sampling speeds are desired in our algorithm, multiple converters can be interleaved in parallel to achieve higher
sampling speeds up to the clock frequency. As an example,
Fig. 3 illustrates experimental waveforms from ten interleaved
converters on a MOSIS 0.35- m TSMC process. Each of the
converters begins its integration-of-the-input phase on a clock
cycle that is sequentially staggered amongst the converters.
III. CIRCUIT IMPLENTATION
Compared to the 12-bit ADC presented in [11], which also
used our algorithm, we were able to achieve an order-of-magnitude improvement in energy efficiency by simplifying several
of the building blocks and changing our design to operate at
lower voltages. First, we implemented a single-stage comparator shown in Fig. 4 rather than a two-stage comparator in
our original design. We used a wide-output-swing operational
transconductance amplifier (OTA) with a positive-feedback
mechanism (implemented by M11 in Fig. 4) and separated
I
the analog and digital supplies (AVDD and DVDD in Fig. 4).
Second, the integrating caps were reduced from 20 pF to 500 fF
and the integrating current from 10 A to 80 nA. Third, we
algorithm for the first three bits, resulting
utilized the
in an average conversion time of 22 clock cycles for 8 bits
of precision. Finally, the analog power supply, AVDD, was
reduced to 1.2 V and the digital power supply, DVDD, was
reduced to 0.75 V.
The pulsewidth control circuit, which creates a finite
pulsewidth output from the comparator, is an adaptation of the
spiking neuron circuits in [15], [16] and is shown in Fig. 5.
When the pulsewidth control circuit is inactive, nodes , ,
are low and nodes
and
are high. Note that
and
node
is pinned low through transistor M12 in this initial
,
configuration. As soon as the output of the comparator,
, the pulsewidth
increases past the threshold of inverter
control circuit is activated. First, the comparator’s output signal
and
. Since
is low and
is sharpened by inverters
is high, the sharpened signal is passed directly onto node
through transmission gate A which in turn sets node
to
and the positive-feedback transistor
zero through inverter
M7. Assuming that the state machine has set the control signal
to the correct value (inactivated transistors M13 and
goes high and node
goes low through
M16), node
and
. The change in these
the final two inverters,
two signals then initiates the refractory phase of the pulsewidth
circuit. Transmission gate A prevents the comparator from influencing the pulsewidth circuit during the refractory phase by
and
from the rest of the circuit.
detaching inverters
Concurrently, transmission gate B connects current source M5
to node . Initially, this current source cannot overcome the
. However,
strong positive feedback loop around inverter
flowing through M10 and M11 charges node ,
as current
transistor M6 slowly turns off, reducing transistor M7’s hold on
pulls down node below the
node . Eventually, current
and the pulsewidth circuit returns
threshold of inverter
to its initial state. Fig. 6 provides an illustration of the node
YANG AND SARPESHKAR: BIO-INSPIRED ULTRA-ENERGY EFFICIENT ADC FOR BIOMEDICAL APPLICATIONS
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TABLE I
SUMMARY OF EXPERIMENTAL RESULTS
Fig. 6. Internal node voltages from a simulation of the pulsewidth control circuit are shown.
Fig. 8. INL and DNL plots for our converter is shown. The INL was obtained
using a least-squared approximation.
IV. EXPERIMENTAL RESULTS
Fig. 7. Die photo of six of our ADCs with varying capacitor sizes is shown. It
was fabricated on the MOSIS TSMC 0.18-m process. The converter presented
in this paper is in the upper left-hand corner. The area of interest is 130 by
160 m.
voltages in the circuit. The pulsewidth circuit is an electronic
channels and
analog of inactivating positive feedback in
channels that determine the
delayed negative feedback in
pulsewidth of action potentials in biological neurons [16].
We implemented our submicrowatt design in the MOSIS
TSMC 0.18- m mixed-signal technology. A die photo of the
VLSI implementation is shown in Fig. 7. The layout includes
six complete converters where we varied integrating capacitor sizes and explored different topologies. In the figure, the
converter of interest is in the upper left-hand corner. All six
converters share the same set of registers, and therefore, the
layout is not optimized for area. Nevertheless, the converter of
interest only consumes an area of 130 by 160 m. A layout for
a single converter can be optimized to consume even less area.
The experimental results are summarized in Table I. Compared to the 12-bit converter presented in [11], this converter
consumes significantly less power at 960 nW. For our static
measurements, we swept the input current from 10 to 320 nA
with a reference current of 80 nA. The limited dynamic range
can be attributed to a 10-nA offset current in the input stage. The
integral nonlinearity (INL) and differential nonlinearity (DNL)
data with respect to 8 bits are presented in Fig. 8. The INL is
bound by 1 LSBs while the DNL is limited to 0.8 LSBs. For
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TABLE II
COMPARISON OF ADCS
Fig. 9. For a full-scale sinusoidal input at 3 kHz, the SNR is 47 dB while the
second harmonic limits the SFDR to 51 dB.
operate with an FOM near
quantization states per joule
(or 1 pJ/quantization level), with the efficiency showing some
degradation with the bandwidth. Our 12-bit converter [11] and
our 8-bit converter (this paper) are also plotted. As can be seen,
the 8-bit converter appears to be the most energy efficient that
we have been able to find. Table II shows that recently published
state-of-the-art energy-efficient ADCs do yield an energy efficiency that is near our converter, especially the 3- W successive-approximation design described in [20]. It is heartening to
note that a completely new bio-inspired algorithm has been able
to successfully compete with more traditional algorithms that
have evolved over decades.
V. COMPUTATIONAL A/DS
A potential application for our algorithm is the computation
and digitization of polynomial functions in a sequential Taylorseries fashion: We can perform a “translinear” type calculation
on timing variables in order to quantize successive terms of
an th-order polynomial function. Fig. 11 illustrates the prinquantizes
ciple behind the time-multiplication process.
, in the same manner as the original
the first timing variable,
algorithm. Therefore, we know that
Fig. 10. Survey of recently published ADCs, their bandwidths, and FOM
(FOM given by the number of quantization states per Joule). The line marks
the average FOM versus bandwidth seen in the literature.
our dynamic measurements, we sampled a full-scale 3-kHz sinusoidal input at 45 kHz to obtain 512 sample points. We then
performed a fast-Fourier-transform (FFT) analysis to obtain the
power-spectral density (PSD) presented in Fig. 9. Using the
well-known formula that relates the signal-to-noise ratio (SNR)
to the effective number of bits (ENOB), the SNR of 47 dB translates to an ENOB of 7.4 bits [17]. The spurious-free dynamic
range (SFDR) is limited to 51 dB by the second harmonic. A
thermal-noise analysis similar to that in [11] and described in
[13] shows that our measurements of thermal-noise-limited precision are in good accord with theory.
Fig. 10 plots a figure of merit (FOM), defined as the reciprocal of the energy efficiency (pJ/quantization level) that we
have been using so far, for a range of converters from the literature over a wide range of bandwidths. These data were obtained by surveying a host of recent publications in the IEEE
Journal of Solid-State Circuits. Most energy-efficient converters
(1)
, however, begins integrating
at the end of the
such that it digitizes the
second comparator output of
timing interval,
. The reason for beginning the integration
here instead of immediately after the first
process of
clock cycle is that the time-to-voltage and voltage-to-time
process eliminates the comparator delays and charge-injection
to a following instead of
errors. Furthermore, it references
labeled in
is
preceding clock edge. Specifically,
labeled in
. Then, the quantized output
identical to
will reflect
of
(2)
Combining (1) with (2), we can see that
(3)
YANG AND SARPESHKAR: BIO-INSPIRED ULTRA-ENERGY EFFICIENT ADC FOR BIOMEDICAL APPLICATIONS
2355
Fig. 11. Illustration of a computational ADC and its signal variables.
The same analysis can be performed on the successive ADCs
such that we can derive the following generalized formula:
(4)
The weighting of each order of the polynomial can be adjusted
by changing the reference current for that converter. For in, then (4)
stance, if the reference current in ADC2 is
changes to
(5)
While we have not implemented such computational A/Ds,
our scheme appears to show promise because of its simplicity.
An immediate application could be in pulse oximetry, where
oxygen saturation is a second-order polynomial function of ,
the measured output of the pulse-oximeter [5], [12].
Another interesting use of our algorithm is in biomedical applications that need to digitize event-based signals, for example,
quantizing signals like instantaneous heart rates and instantaneous neural interspike intervals. The time-to-digital nature of
our algorithm allows us to directly digitize the intervals between two such events by a simple modification of the algorithm: Several schemes for doing so can easily be imagined but
the simplest is to have the integration phase of our conversion
be defined by two successive events and to digitize the previous
interevent interval while sampling the next.
VI. CONCLUSION
We have presented a neuronally inspired ADC that is based on
the first ever time-based algorithm whose conversion time grows
linearly with bit precision. Our experimental results demonstrate that operating on time-based residues with a sequence
of integrate-and-fire operations allows for extremely energy-efficient conversion. Our converter appears to be the most energy-efficient converter reported so far. It is also very area efficient. It could be very useful in portable and wireless biomedical sensors for ECG, PCG, EEG, neural recording, temperature, blood pressure, pulse-oximetry, passive RF-ID medical
tags, and in implanted medical devices where moderate precision and moderate speed suffice but ultra energy-efficient operation is critical. Its architecture is easily modifiable to perform
interleaving, polynomial computations on its input before digitization, and direct time-to-digital conversion of event-based signals such as cardiac ECGs or neural action potentials.
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61
Heemin Y. Yang received the B.S. degree in electrical engineering and computer science, the M.Eng.
degree in electrical engineering, and the Ph.D. degree in electrical engineering from the Massachusetts
Institute of Technology (MIT), Cambridge, in 1998,
2000, and 2006, respectively.
From 2000 to 2006, he was a Research Assistant
(under Prof. Sarpeshkar) in the Analog VLSI and Biological Systems group at MIT focusing on ultra-low
power analog–digital conversion techniques. He is
currently a member of the Mixed Signals Group at
Linear Technologies, Milpitas, CA.
Rahul Sarpeshkar received B.S. degrees in
electrical engineering and physics from the Massachusetts Institute of Technology (MIT), Cambridge,
and the Ph.D. degree from Caltech, Pasadena.
He worked at Bell Laboratories as a Member of
the Technical Staff. Since 1999, he has been on the
faculty of MIT’s Electrical Engineering and Computer Science Department where he heads a research
group on Analog VLSI and Biological Systems, and
is currently an Associate Professor. He holds over
20 patents and has authored several publications, including one that was featured on the cover of Nature. His research interests include analog and mixed-signal VLSI, ultra-low-power circuits and systems, biologically inspired circuits and systems, biomedical systems, and control theory.
Prof. Sarpeshkar has received several awards, including the Packard Fellow
Award given to outstanding young faculty, the Office of Naval Research Young
Investigator Award, the National Science Foundation Career Award, and the Junior Bose Award for Excellence in Teaching at MIT.