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DC to 50 MHz, Quad I/Q Demodulator and Phase Shifter AD8339 FEATURES APPLICATIONS Medical imaging (CW ultrasound beamforming) Phased array systems Radar Adaptive antennas Communication receivers FUNCTIONAL BLOCK DIAGRAM RF1N RF1P AD8339 Φ I1OP Φ Q1OP Φ I2OP Φ Q2OP Φ I3OP Φ Q3OP Φ I4OP Φ Q4OP SCLK SDI SDO SERIAL INTERFACE CSB RF2P RF2N 4LOP 4LON 0° ÷4 90° RF3P RF3N VPOS BIAS VNEG RF4N RF4P www.BDTIC.com/ADI 06587-001 Quad integrated I/Q demodulator 16 phase select on each output (22.5° per step) Quadrature demodulation accuracy Phase accuracy: ±1° Amplitude balance: ±0.25 dB Bandwidth 4LO: LF to 200 MHz RF: LF to 50 MHz Baseband: determined by external filtering Output dynamic range: 160 dB/Hz LO drive: >0 dBm (50 Ω), single-ended sine wave Supply: ±5 V Power consumption: 73 mW/channel (290 mW total) Power-down via SPI (each channel and complete chip) Figure 1. GENERAL DESCRIPTION The AD8339 1 is a quad I/Q demodulator configured to be driven by a low noise preamplifier with differential outputs. It is optimized for the LNA in the AD8332/AD8334/AD8335 family of VGAs. The part consists of four identical I/Q demodulators with a 4× local oscillator (LO) input that divides this signal and generates the necessary 0° and 90° phases of the internal LO that drive the mixers. The four I/Q demodulators can be used independently of each other (assuming that a common LO is acceptable) because each has a separate RF input. Continuous wave (CW) analog beamforming (ABF) and I/Q demodulation are combined in a single 40-lead ultracompact chip scale device, making the AD8339 particularly applicable in high density ultrasound scanners. In an ABF system, time domain coherency is achieved following the appropriate phase alignment and summation of multiple receiver channels. A reset pin synchronizes multiple ICs to start each LO divider in the same quadrant. Sixteen programmable 22.5° phase increments are available for each channel. For example, if Channel 1 is used as a reference and Channel 2 has an I/Q phase lead of 45°, then the user can phase align Channel 2 with Channel 1 by choosing the correct code. 1 The mixer outputs are in current form for convenient summation. The independent I and Q mixer output currents are summed and converted to a voltage by a low noise, high dynamic range, current-to-voltage (I-V) transimpedance amplifier, such as the AD8021 or the AD829. Following the current summation, the combined signal is applied to a high resolution analog-to-digital converter (ADC), such as the AD7665 (16-bit, 570 kSPS). An SPI-compatible serial interface port is provided to easily program the phase of each channel; the interface allows daisy chaining by shifting the data through each chip from SDI to SDO. The SPI also allows for power-down of each individual channel and the complete chip. During power-down, the serial interface remains active so that the device can be programmed again. The dynamic range is typically 160 dB/Hz at the I and Q outputs. The AD8339 is available in a 6 mm × 6 mm, 40-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. Patent pending. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD8339 TABLE OF CONTENTS Features .............................................................................................. 1 Summation of Multiple Channels (Analog Beamforming).. 20 Applications....................................................................................... 1 Phase Compensation and Analog Beamforming................... 21 Functional Block Diagram .............................................................. 1 Channel Summing ..................................................................... 21 General Description ......................................................................... 1 Serial Interface ................................................................................ 22 Revision History ............................................................................... 2 ENBL Bits .................................................................................... 22 Specifications..................................................................................... 3 Applications..................................................................................... 23 Absolute Maximum Ratings............................................................ 5 Logic Inputs and Interfaces....................................................... 23 ESD Caution.................................................................................. 5 Reset Input .................................................................................. 23 Pin Configuration and Function Descriptions............................. 6 LO Input ...................................................................................... 23 Equivalent Input Circuits ................................................................ 7 Evaluation Board ............................................................................ 24 Typical Performance Characteristics ............................................. 8 Connections to the Board ......................................................... 25 Test Circuits..................................................................................... 14 Test Configurations.................................................................... 25 Theory of Operation ...................................................................... 18 AD8339-EVALZ Artwork ......................................................... 32 Quadrature Generation ............................................................. 19 Outline Dimensions ....................................................................... 36 I/Q Demodulator and Phase Shifter ........................................ 19 Ordering Guide .......................................................................... 36 Dynamic Range and Noise........................................................ 19 www.BDTIC.com/ADI REVISION HISTORY 8/07—Revision 0: Initial Version Rev. 0 | Page 2 of 36 AD8339 SPECIFICATIONS VS = ±5 V, TA = 25°C, 4fLO = 20 MHz, fRF = 5.01 MHz, fBB = 10 kHz, PLO ≥ 0 dBm, per channel performance, dBm (50 Ω), unless otherwise noted. Single-channel AD8021 LPF values: RFILT = 787 Ω and CFILT = 2.2 nF (see Figure 52). Table 1. Parameter OPERATING CONDITIONS Local Oscillator Frequency Range RF Frequency Range Baseband Bandwidth LO Input Level VSUPPLY (VS) Temperature Range DEMODULATOR PERFORMANCE Input Impedance Transconductance Dynamic Range Maximum Input Swing Peak Output Current (No Filtering) Conditions Min 4× internal LO at Pin 4LOP and Pin 4LON, square wave drive via LVDS (see Figure 62) Mixing Limited by external filtering Max Unit 0.01 200 MHz DC DC 50 50 13 ±5.5 +85 MHz MHz dBm V °C ±4.5 −40 Typ 0 ±5 RF, differential LO, differential Demodulated IOUT/VIN; each Ix or Qx output after lowpass filtering measured from RF inputs, all phases IP1dB − input referred noise (dBm) 25||10 100||4 1.15 kΩ||pF kΩ||pF mS 160 Differential; inputs biased at 2.5 V; Pin RFxP, Pin RFxN 0° phase shift 45° phase shift Ref = 50 Ω Ref = 1 V rms fRF1 = 5.010 MHz, fRF2 = 5.015 MHz, fLO = 5.023 MHz Baseband tones: 0 dBm @ 8 kHz and 13 kHz Baseband tones: −1 dBm @ 8 kHz and −31 dBm @ 13 kHz fRF1 = 5.010 MHz, fRF2 = 5.015 MHz, fLO = 5.023 MHz Measured at RF inputs, worst phase, measured into 50 Ω Measured at baseband outputs, worst phase, AD8021 disabled, measured into 50 Ω All codes, see Figure 41 Output noise/conversion gain (see Figure 46) Output noise/RFILT With AD8334 LNA RS = 50 Ω, RFB = ∞ RS = 50 Ω, RFB = 1.1 kΩ RS = 50 Ω, RFB = 274 Ω Pin 4LOP and Pin 4LON Pin RFxP and Pin RFxN Pin 4LOP and Pin 4LON (each pin) For maximum differential swing; Pin RFxP and Pin RFxN (dc-coupled to AD8334 LNA output) Pin IxOP and Pin QxOP One channel is reference, others are stepped 16 phase steps per channel Ix to Qx; all phases, 1σ Ix to Qx; all phases, 1σ Phase match I-to-I and Q-to-Q; −40°C < TA < +85°C Amplitude match I-to-I and Q-to-Q; −40°C < TA < +85°C 2.8 ±2.4 ±3.1 14.8 1.85 dB (1 Hz BW) V p-p mA mA dBm dBV −60 −66 31 −118 −68 dBc dBc dBm dBm dBm −1.3 11.8 12.9 dB nV/√Hz pA/√Hz 8.4 9.1 11.5 −3 −45 dB dB dB μA μA V V www.BDTIC.com/ADI Input P1dB Third-Order Intermodulation (IM3) Equal Input Levels Unequal Input Levels Third-Order Input Intercept (IIP3) LO Leakage Conversion Gain Input Referred Noise Output Current Noise Noise Figure Bias Current LO Common-Mode Range RF Common-Mode Voltage Output Compliance Range PHASE ROTATION PERFORMANCE Phase Increment Quadrature Phase Error I/Q Amplitude Imbalance Channel-to-Channel Matching Rev. 0 | Page 3 of 36 0.2 3.8 2.5 −1.5 −2 +0.7 22.5 ±1 ±0.05 ±1 ±0.1 +2 V Degrees Degrees dB Degrees dB AD8339 Parameter LOGIC INTERFACES Logic Level High Logic Level Low Logic Level High Logic Level Low Bias Current Input Resistance LO Divider RSET Setup Time LO Divider RSET High Pulse Width LO Divider RSET Response Time Phase Response Time Enable Response Time Output Logic Level High Logic Level Low SPI TIMING CHARACTERISTICS SCLK Frequency CSB Fall to SCLK Setup Time SCLK High Pulse Width SCLK Low Pulse Width Data Access Time (SDO) After SCLK Rising Edge Data Setup Time Before SCLK Rising Edge Data Hold Time After SCLK Rising Edge SCLK Rise to CSB Rise Hold Time CSB Rise to SCLK Rise Hold Time POWER SUPPLY Supply Voltage Current Conditions Min Pin SDI, Pin CSB, Pin SCLK, Pin RSET 1.5 Typ Max 0.9 Pin RSTS 1.8 1.2 Logic high (pulled to +5 V) Logic low (pulled to GND) RSET rising or falling edge to 4LOP to 4LON (differential) rising edge 0.5 0 4 5 20 200 5 12 Measured from CSB going high Measured from CSB going high (with 0.1 μF capacitor on Pin LODC); no channel enabled At least one channel enabled Pin SDO loaded with 5 pF and next SDI input 500 1.7 Pin SDI, Pin SDO, Pin CSB, Pin SCLK, Pin RSTS fCLK t1 t2 t3 t4 15 1.9 0.2 Quiescent Power Disable Current PSRR V V V V μA μA MΩ ns ns ns μs μs ns 0.5 10 0 10 10 www.BDTIC.com/ADI Over Temperature −40°C < TA < +85°C Unit 100 V V MHz ns ns ns ns t5 2 ns t6 2 ns t7 t8 Pin VPOS, Pin VNEG 15 0 ns ns ±4.5 VPOS, all phase bits = 0 VNEG, all phase bits = 0 VPOS, all phase bits = 0 VNEG, all phase bits = 0 Per channel, all phase bits = 0 Per channel maximum (depends on phase bits) All channels disabled; SPI stays on VPOS to Ix/Qx outputs, @ 10 kHz VNEG to Ix/Qx outputs, @ 10 kHz Rev. 0 | Page 4 of 36 ±5 35 −18 33 ±5.5 36 −19 −17 66 88 2.75 −85 −85 V mA mA mA mA mW mW mA dB dB AD8339 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Voltages Supply Voltage (VS) RF Inputs 4LO Inputs Outputs (IxOP, QxOP) Digital Inputs SDO Output LODC Pin Thermal Data (4-Layer JEDEC Board, No Air Flow, Exposed Pad Soldered to PC Board) θJA θJB θJC ψJT ψJB Maximum Junction Temperature Maximum Power Dissipation (Exposed Pad Soldered to PC Board) Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating ±6 V +6 V to GND +6 V to GND +0.7 V to −6 V +6 V to GND +6 V to GND VPOS − 1.5 V to +6 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 32.2°C/W 17.8°C/W 2.7°C/W 0.3°C/W 16.7°C/W 150°C 2W −40°C to +85°C −65°C to +150°C 300°C www.BDTIC.com/ADI Rev. 0 | Page 5 of 36 AD8339 VNEG Q1OP I1OP VPOS RSET COMM RF1N RF1P RSTS SDI PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 40 39 38 37 36 35 34 33 32 31 RF2P 1 2 COMM 3 COMM SCLK 4 5 CSB 6 VPOS 7 VPOS RF3P RF2N RF3N PIN 1 INDICATOR AD8339 30 Q2OP 29 28 27 26 I2OP VPOS VPOS 25 24 4LOP 4LON VNEG 8 23 VNEG 9 10 22 I3OP 21 Q3OP TOP VIEW (Not to Scale) 06587-002 VNEG I4OP Q4OP VPOS LODC COMM RF4P RF4N VPOS SDO 11 12 13 14 15 16 17 18 19 20 Figure 2. 40-Lead LFCSP Table 3. Pin Function Descriptions Pin No. 1, 2, 9, 10, 13, 14, 37, 38 3, 4, 15, 36 5 6 7, 8, 11, 16, 27, 28, 35 Mnemonic RF1P to RF4P, RF1N to RF4N COMM SCLK CSB VPOS Description RF Inputs. Require external 2.5 V bias for optimum symmetrical input differential swing if ±5 V supplies are used. Ground. Serial Interface—Clock. Serial Interface—Chip Select Bar. Active low. Positive Supply. These pins should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF and 1 nF capacitor between the VPOS pins and ground. Because the VPOS pins are internally connected, one set of supply decoupling components on each side of the chip should be sufficient. Serial Interface—Data Output. Normally connected to SDI of next chip or left open. Decoupling Pin for LO. A 0.1 μF capacitor should be connected between this pin and ground. Value of capacitor influences chip enable/disable times. I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via a transimpedance amplifier. Multiple outputs can be summed together by simply connecting them (wireOR). The bias voltage should be set to 0 V or less by the transimpedance amplifier (see Figure 52). Negative Supply. These pins should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF and 1 nF capacitor between the pin and ground. Because the VNEG pins are internally connected, one set of supply decoupling components should be sufficient. LO Inputs. No internal bias; optimally biased by an LVDS driver. For best performance, these inputs should be driven differentially. If driven by single-ended sine wave at 4LOP or 4LON, the signal level should be > 0 dBm (50 Ω) with external bias resistors. LO Interface—Reset. Logic threshold is at ~1.3 V and therefore can be driven by >1.8 V CMOS logic. Serial Interface—Data Input. Logic threshold is at ~1.3 V and therefore can be driven by >1.8 V CMOS logic. Reset for SPI Interface. Logic threshold is at ~1.5 V with ± 0.3 V hysteresis and should be driven by >3.3 V CMOS logic. For quick testing without the need to program the SPI, the voltage on the RSTS pin should be pulled to −1.4 V; this enables all four channels in the phase (I = 1, Q = 0) state. www.BDTIC.com/ADI 12 17 SDO LODC 18, 19, 21, 22, 29, 30, 32, 33 I1OP to I4OP, Q1OP to Q4OP 20, 23, 24, 31 VNEG 25, 26 4LOP, 4LON 34 39 RSET SDI 40 RSTS Rev. 0 | Page 6 of 36 AD8339 EQUIVALENT INPUT CIRCUITS VPOS VPOS SCLK CSB SDI RSET RSTS RFxP LOGIC INTERFACE 06587-006 COMM 06587-003 RFxN COMM Figure 3. Logic Inputs Figure 6. RF Inputs VPOS COMM 4LOP IxOP QxOP 4LON COMM VNEG Figure 7. Output Drivers Figure 4. Local Oscillator Inputs VPOS COMM 06587-005 LODC Figure 5. LO Decoupling Pin Rev. 0 | Page 7 of 36 06587-007 06587-004 www.BDTIC.com/ADI AD8339 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±5 V, TA = 25°C, 4fLO = 20 MHz, fLO = 5 MHz, fRF = 5.01 MHz, fBB = 10 kHz, 4fLO − LVDS drive; per channel performance shown is typical of all channels, differential voltages, dBm (50 Ω), phase select code = 0000, unless otherwise noted (see default test circuit). 2 CODE 0100 CODE 0011 IMAGINARY (Normalized) 1.0 CODE 0010 CODE 0001 Q 0.5 CODE 1000 CODE 0000 0 I –0.5 CODE 1100 –1.5 –1.5 –1.0 –0.5 0 –1 0 0.5 1.0 1.5 CHANNEL 3 CHANNEL 4 –2 2 F = 1MHz 1 0 06587-008 –1.0 –2.0 F = 5MHz 1 –1 CHANNEL 3 CHANNEL 4 –2 0010 0100 0000 2.0 REAL (Normalized) 06587-011 f = 1MHz AMPLITUDE ERROR (Degrees) 1.5 0110 1000 1010 1100 1110 1111 CODE (Binary) Figure 8. Normalized Vector Plot of Phase, CH2, CH3, and CH4 vs. CH1, CH1 Is Fixed at 0°, CH2, CH3, and CH4 Stepped 22.5°/Step, All Codes Displayed Figure 11. Representative Phase Error vs. Binary Phase-Select Code at 1 MHz and 5 MHz, CH3 and CH4 Are Displayed With Respect to CH1 360 315 www.BDTIC.com/ADI PHASE (Degrees) 270 5MHz 225 1 2 180 1MHz 135 0 0000 06587-009 45 06587-012 90 0010 0100 0110 1000 1010 1100 1110 C2 500mV Ω C4 500mV Ω 1111 CODE (Binary) Figure 9. Representative Phase Delay vs. Binary Phase-Select Code at 1 MHz and 5 MHz, CH3 and CH4 Are Displayed With Respect to CH1 R1 500mV 20µs R2 500mV 20µs 20.0µs/DIV 2.5MS/s 400ns/PT A C2 30.0mV Figure 12. Representative Phase Delays of the I or Q Outputs, CH2 Is Displayed With Respect to CH1, for Delays of 22.5°, 45°, 67.5°, and 90° 1 1.0 I OUTPUT OF CHANNEL 1 SHOWN F = 5MHz 0.5 CHANNEL 3 CHANNEL 4 –1.0 1.0 F = 1MHz 0.5 0 CHANNEL 3 CHANNEL 4 –1.0 0000 0010 0100 0110 1000 1010 1100 1110 –1 –2 CODE 0000 CODE 0001 CODE 0010 CODE 0011 06587-010 –0.5 0 –3 1M 1111 06587-013 –0.5 CONVERSION GAIN (dB) AMPLITUDE ERROR (dB) 0 10M 50M RF FREQUENCY (Hz) CODE (Binary) Figure 10. Representative Amplitude Error vs. Binary Phase-Select Code at 1 MHz and 5 MHz, CH3 and CH4 Are Displayed With Respect to CH1 Rev. 0 | Page 8 of 36 Figure 13. Conversion Gain vs. RF Frequency, First Quadrant, Baseband Frequency = 10 kHz AD8339 0.5 0.4 4 2 0 –2 –4 –6 –8 1M 10M 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 06587-017 I/Q AMPLITUDE IMBALANCE (dB) 6 06587-014 QUADRATURE PHASE ERROR (Degrees) 8 –0.4 –0.5 100 50M 1k RF FREQUENCY (Hz) 10k 100k BASEBAND FREQUENCY (Hz) Figure 14. Representative Range of Quadrature Phase Error vs. RF Frequency for All Channels and Codes Figure 17. Representative Range of I/Q Amplitude Imbalance vs. Baseband Frequency for All Channels and Codes (See Figure 43) 2.0 3 2 AMPLITUDE ERROR (dB) 1.0 0.5 0 –1.0 –1.5 1 0 www.BDTIC.com/ADI –2.0 100 –1 –2 1k 10k –3 1M 100k 10M BASEBAND FREQUENCY (Hz) 50M RF FREQUENCY (Hz) Figure 15. Representative Range of Quadrature Phase Error vs. Baseband Frequency for All Channels and Codes (See Figure 43) Figure 18. Typical Channel-to-Channel Amplitude Match vs. RF Frequency, First Quadrant, Over the Range of Operating Temperatures 0.5 8 fBB = 10kHz 0.4 6 PHASE ERROR (Degrees) 0.3 0.2 0.1 0 –0.1 –0.2 4 2 0 –2 –4 –0.3 10M –8 1M 50M RF FREQUENCY (Hz) 06587-019 –0.4 –0.5 1M –6 06587-016 I/Q AMPLITUDE IMBALANCE (dB) 06587-018 –0.5 06587-015 QUADRATURE PHASE ERROR (Degrees) fBB = 10kHz 1.5 10M 50M RF FREQUENCY (Hz) Figure 16. Representative Range of I/Q Amplitude Imbalance vs. RF Frequency for All Channels and Codes Figure 19. Typical Channel-to-Channel Phase Error vs. RF Frequency, First Quadrant, Over the Range of Operating Temperatures Rev. 0 | Page 9 of 36 AD8339 1.4 0 I OUTPUT OF CHANNEL 1 SHOWN TRANSCONDUCTANCE = [(VBB/787Ω)/V RF] –10 –20 IM3 (dBc) 1.2 1.1 –30 3 8 13 18 IM3 PRODUCTS LO = 5.023MHz RF1 = 5.015MHz RF2 = 5.010MHz –40 –50 –60 0.8 1M 10M –70 1M 50M RF FREQUENCY (Hz) 10M 50M RF FREQUENCY (Hz) Figure 23. Representative Range of IM3 vs. RF Frequency, First Quadrant (See Figure 48) Figure 20. Transconductance vs. RF Frequency for First Quadrant Phase Delays 10 35 +85°C +25°C –40°C 0 30 –10 25 OIP3 (dBm) –20 –30 20 15 www.BDTIC.com/ADI –40 10 5 06587-021 –60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 1M 5.0 COMMON MODE VOLTAGE (V) 10M 06587-024 –50 –70 06587-023 PHASE DELAY = 0° PHASE DELAY = 22.5° PHASE DELAY = 45° PHASE DELAY = 67.5° 0.9 CONVERSION GAIN (dB) 0dBm 1.0 06587-020 TRANSCONDUCTANCE (mS) 1.3 50M RF FREQUENCY (Hz) Figure 24. Representative Range of OIP3 vs. RF Frequency, First Quadrant (See Figure 48) Figure 21. LO Common-Mode Range at Three Temperatures 20 35 18 30 16 25 OIP3 (dBm) 12 10 8 6 20 15 10 4 10M 0 1k 50M RF FREQUENCY (Hz) 06587-025 2 0 1M 5 06587-022 IP1dB (dBm) 14 10k 100k BASEBAND FREQUENCY (Hz) Figure 22. Representative Range of IP1dB vs. RF Frequency, Baseband Frequency = 10 kHz, First Quadrant (See Figure 42) Figure 25. Representative Range of OIP3 vs. Baseband Frequency (See Figure 47) Rev. 0 | Page 10 of 36 AD8339 0 20 LO LEVEL = 0dBm 18 –10 16 NOISE FIGURE (dB) –30 –40 –50 –60 –70 14 12 10 8 6 4 06587-026 –80 –90 1M 10M 06587-029 LO LEAKAGE (dBm) –20 2 0 1M 50M 10M RF FREQUENCY (Hz) Figure 29. Noise Figure vs. RF Frequency (When Driven by AD8334 LNA) Figure 26. Representative Range of LO Leakage vs. RF Frequency at I and Q Outputs 0 50M RF FREQUENCY (Hz) 172 LO LEVEL = 0dBm 170 –20 DYNAMIC RANGE (dB) –60 –100 164 162 www.BDTIC.com/ADI 160 Q1 Q2 Q3 Q4 I1 + I2 I3 + I4 Q1 + Q2 Q3 + Q4 I1 + I2 + I3 + I4 Q1 + Q2 + Q3 + Q4 158 –120 06587-027 156 –140 1M 10M 154 152 1M 50M 10M RF FREQUENCY (Hz) 0 14 –144.1 –2 12 –145.4 –4 10 –147.0 –6 8 –148.9 6 –151.4 4 –154.9 –12 2 –161.0 –14 GAIN (dB) NOISE (dBm) –142.9 GAIN = VBB/VRF –8 –10 06587-028 NOISE (nV/√Hz) Figure 30. Dynamic Range vs. RF Frequency, IP1dB Minus Noise Level 16 10M 50M RF FREQUENCY (Hz) Figure 27. Representative Range of LO Leakage vs. RF Frequency at RF Inputs 0 1M 06587-030 –80 166 –16 –3.5 50M RF FREQUENCY (Hz) DELAY = 0° DELAY = 22.5° DELAY = 45° DELAY = 67.5° –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 06587-031 LO LEAKAGE (dBm) 168 –40 0 0.5 1.0 VOLTAGE (V) Figure 28. Representative Range of Input Referred Noise vs. RF Frequency Figure 31. Output Compliance Range for Four Values of Phase Delay (See Figure 49) Rev. 0 | Page 11 of 36 AD8339 T CH3 AMPL 3.18V CH3 AMPL 5.04 V 3 3 CH2 AMPL 790mV CH2 AMPL 370mV 2 CH2 500mV CH3 1.00V Ω M200ns A CH3 T 608.000ns 06587-035 06587-032 2 600mV CH3 2.00V Ω CH2 500mV Figure 32. Enable Response vs. CSB (Filter Disabled to Show Response) with a Previously Enabled Channel (See Figure 43) 3 2.52mV Figure 35. LO Reset Response (see Figure 44) 3 www.BDTIC.com/ADI CH2 AMPL 1.82V CH3 1.00V Ω CH2 500mV M2.00µs A CH3 T 7.840µs 06587-033 2 780mV CH3 1.00V Ω CH2 1.00V CH4 1.00V Figure 33. Enable Response vs. CSB (Filter Disabled to Show Response) with No Channels Previously Enabled (See Figure 43) M40.0µs A CH3 T 46.4000µs 06587-036 2 M200µs A CH3 T –175.200ns 640mV Figure 36. Phase Switching Response at 45° (Top: CSB) CH3 AMPL 3.18V 3 3 CH2 AMPL 210mV 06587-034 CH3 1.00V Ω CH2 500mV M200µs A CH3 T –492.00ns 06587-037 2 2 600mV CH3 1.00V Ω CH2 1.00V CH4 1.00V Figure 34. Disable Response vs. CSB (Top: CSB) (See Figure 43) M40.0µs A CH3 T 46.4000µs 640mV Figure 37. Phase Switching Response at 90° (Top: CSB) Rev. 0 | Page 12 of 36 AD8339 60 SUPPLY CURRENT (mA) 50 3 2 40 VPOS 30 20 VNEG CH3 1.00V Ω CH2 1.00V CH4 1.00V M40.0µs A CH3 T 46.4000µs 0 –50 640mV 06587-040 06587-038 10 –30 –10 10 30 50 TEMPERATURE (°C) Figure 38. Phase Switching Response at 180° (Top: CSB) Figure 40. Supply Current vs. Temperature 0 –10 –20 –40 –50 –60 –70 –80 –90 VNEG www.BDTIC.com/ADI –100 10k VPOS 06587-039 PSRR (dB) –30 100k 1M 10M 50M FREQUENCY (Hz) Figure 39. PSRR vs. Frequency (see Figure 50) Rev. 0 | Page 13 of 36 70 90 AD8339 TEST CIRCUITS AD8021 120nH FB 0.1µF 787Ω AD8334 LNA 20Ω LPF 50Ω 2.2nF RFxP Ix AD8339 0.1µF 20Ω RFxN OSCILLOSCOPE 2.2nF Qx LOP 787Ω SIGNAL GENERATOR 50Ω AD8021 06587-041 SIGNAL GENERATOR Figure 41. Default Test Circuit AD8021 120nH FB 0.1µF 100Ω AD8334 LNA 20Ω LPF 10nF RFxP Ix AD8339 RFxN OSCILLOSCOPE 10nF Qx www.BDTIC.com/ADI 50Ω 0.1µF 20Ω LOP 100Ω SIGNAL GENERATOR 50Ω AD8021 06587-042 SIGNAL GENERATOR Figure 42. P1dB Test Circuit AD8021 120nH FB 0.1µF AD8334 LNA 20Ω LPF 50Ω RFxP Ix 787Ω OSCILLOSCOPE AD8339 0.1µF 20Ω RFxN Qx 787Ω LOP SIGNAL GENERATOR 50Ω AD8021 Figure 43. Phase and Amplitude vs. Baseband Frequency Rev. 0 | Page 14 of 36 06587-043 SIGNAL GENERATOR AD8339 AD8021 120nH FB 0.1µF AD8334 LNA 20Ω RFxP LPF 787Ω Ix OSCILLOSCOPE AD8339 50Ω 0.1µF RFxN RSET 20Ω 787Ω Qx LOP SIGNAL GENERATOR 50Ω 50Ω SIGNAL GENERATOR 06587-044 SIGNAL GENERATOR AD8021 Figure 44. LO Reset Response 120nH FB 0.1µF AD8334 LNA OSCILLOSCOPE 20Ω RFxP LPF 50Ω Ix AD8339 0.1µF RFxN 20Ω 50Ω 50Ω Qx LOP SIGNAL GENERATOR 50Ω 06587-045 SIGNAL GENERATOR www.BDTIC.com/ADI Figure 45. RF Input Range AD829 6.98kΩ AD8334 LNA 270pF 20Ω RFxP 0.1µF 0.1µF 20Ω Ix AD8339 RFxN SPECTRUM ANALYZER 270pF Qx LOP 6.98kΩ 50Ω SIGNAL GENERATOR Figure 46. Noise Rev. 0 | Page 15 of 36 AD829 06587-046 120nH FB 0.1µF AD8339 AD8021 SPLITTER AD8334 –9.5dB LNA 120nH 20Ω FB 0.1µF 50Ω 787Ω 100pF RFxP Ix AD8339 SIGNAL GENERATOR 50Ω 0.1µF RFxN 20Ω SPECTRUM ANALYZER 100pF Qx LOP 787Ω SIGNAL GENERATOR 50Ω AD8021 06587-047 SIGNAL GENERATOR Figure 47. OIP3 vs. Baseband Frequency AD8021 SPLITTER AD8334 –9.5dB LNA 120nH 20Ω FB 0.1µF 50Ω 787Ω 2.2nF RFxP Ix AD8339 SIGNAL GENERATOR 50Ω 0.1µF RFxN 20Ω SPECTRUM ANALYZER 2.2nF Qx LOP 787Ω SIGNAL GENERATOR www.BDTIC.com/ADI 50Ω AD8021 06587-048 SIGNAL GENERATOR Figure 48. OIP3 and IM3 vs. RF Frequency AD8021 787Ω AD8334 LNA 20Ω LPF 50Ω 2.2nF RFxP Ix AD8339 0.1µF 20Ω RFxN OSCILLOSCOPE 2.2nF Qx LOP SIGNAL GENERATOR 787Ω 50Ω SIGNAL GENERATOR AD8021 Figure 49. Output Compliance Range Rev. 0 | Page 16 of 36 06587-049 120nH FB 0.1µF AD8339 SIGNAL GENERATOR VPOS VPOS RFxP 0.1µF Ix SPECTRUM ANALYZER AD8339 RFxN Qx LOP SIGNAL GENERATOR 06587-050 VPOS Figure 50. PSRR www.BDTIC.com/ADI Rev. 0 | Page 17 of 36 AD8339 THEORY OF OPERATION RF2N 1 RF2P 2 COMM 3 COMM 4 SCLK 5 RSTS SDI RF1P RF1N 40 39 38 37 COMM VPOS 36 RSET I1OP Q1OP VNEG 34 33 32 31 35 0° Φ CURRENT MIRROR 30 Q2OP Φ CURRENT MIRROR 29 I2OP Φ CURRENT MIRROR 28 VPOS Φ CURRENT MIRROR 27 VPOS 26 4LOP 25 4LON V TO I V TO I SERIAL INTERFACE (SPI) 0° LOCAL OSCILLATOR DIVIDE BY 4 90° CSB 6 VPOS 7 Φ CURRENT MIRROR 24 VNEG Φ CURRENT MIRROR 23 VNEG V TO I VPOS 8 BIAS www.BDTIC.com/ADI RF3P 9 Φ CURRENT MIRROR 22 I3OP Φ CURRENT MIRROR 21 Q3OP V TO I RF3N 10 11 12 13 14 VPOS SDO RF4P RF4N 15 16 COMM VPOS 17 18 19 20 LODC I4OP Q4OP VNEG 06587-051 AD8339 Figure 51. AD8339 Block Diagram The AD8339 is a quad I/Q demodulator with a programmable phase shifter for each channel. The primary application is phased array beamforming in medical ultrasound. Other potential applications include phased array radar and smart antennas for mobile communications. The AD8339 can also be used in applications that require multiple well matched I/Q demodulators. The AD8339 is architecturally very similar to its predecessor, the AD8333. The major differences are • The addition of a serial (SPI) interface that allows daisy chaining of multiple devices • Reduced power per channel Figure 51 shows the block diagram and pinout of the AD8339. Four RF inputs that accept signals from the RF sources and a local oscillator (applied to differential input pins marked 4LOP and 4LON) common to all channels comprise the analog inputs. Each channel has the option to program 16 delay states/360° (or 22.5°/step) selectable via the SPI port. The part has two reset inputs: RSET is used to synchronize the LO dividers in multiple AD8339s used in arrays; RSTS is used to set the SPI port bits to all zeros. This can be useful in testing or to quickly turn off the device without first programming the SPI port. Each of the current formatted I and Q outputs sum together for beamforming applications. Multiple channels are summed and converted to a voltage using a transimpedance amplifier. If desired, channels can also be used individually. Rev. 0 | Page 18 of 36 AD8339 QUADRATURE GENERATION The internal 0° and 90° LO phases are digitally generated by a divide-by-four logic circuit. The divider is dc-coupled and inherently broadband; the maximum LO frequency is limited only by its switching speed. The duty cycle of the quadrature LO signals is intrinsically 50% and is unaffected by the asymmetry of the externally connected 4LO input. Furthermore, the divider is implemented such that the 4LO signal reclocks the final flipflops that generate the internal LO signals and thereby minimizes noise introduced by the divide circuitry. For optimum performance, the 4LO input is driven differentially, but can also be driven single-ended. A good choice for a drive is an LVDS device as is done on the evaluation board. The commonmode range on each pin is approximately 0.2 V to 3.8 V with the nominal ±5 V supplies. The minimum 4LO level is frequency dependent when driven by a sine wave. For optimum noise performance, it is important to ensure that the LO source has very low phase noise (jitter) and adequate input level to ensure stable mixer-core switching. The gain through the divider determines the LO signal level vs. RF frequency. The AD8339 can be operated to very low frequencies at the LO inputs if a square wave is used to drive the LO, as is done with the LVDS driver on the evaluation board. Following the phase shift circuitry, the differential current signal is converted from differential to single-ended via a current mirror. An external transimpedance amplifier is needed to convert the I and Q outputs to voltages. Table 4. Phase Select Code for Channel-to-Channel Phase Shift Φ Shift 0° 22.5° 45° 67.5° 90° 112.5° 135° 157.5° 180° 202.5° 225° 247.5° 270° 292.5° 315° 337.5° PHx3 (MSB) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PHx2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PHx1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PHx0 (LSB) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DYNAMIC RANGE AND NOISE www.BDTIC.com/ADI Beamforming applications require a precise channel-to-channel phase relationship for coherence among multiple channels. A reset pin is provided to synchronize the LO divider circuits in different AD8339s when they are used in arrays. The RSET pin resets the dividers to a known state after power is applied to multiple AD8339s. A logic input must be provided to the RSET pin when using more than one AD8339. Note that at least one channel must be enabled for the LO interface to also be enabled and the LO reset to work. See the Reset Input section in the applications section for more detail. I/Q DEMODULATOR AND PHASE SHIFTER The I/Q demodulators consist of double-balanced Gilbert cell mixers. The RF input signals are converted into currents by transconductance stages that have a maximum differential input signal capability of 2.8 V p-p. These currents are then presented to the mixers, which convert them to baseband (RF − LO) and twice RF (RF + LO). The signals are phase shifted according to the codes programmed into the SPI latch (see Table 4); the phase bits are labeled PHx0 through PHx3 where 0 indicates LSB and 3 indicates MSB. The phase shift function is an integral part of the overall circuit (patent pending). The phase shift listed in Column 1 of Table 4 is defined as being between the baseband I or Q channel outputs. As an example, for a common signal applied to a pair of RF inputs to an AD8339, the baseband outputs are in phase for matching phase codes. However, if the phase code for Channel 1 is 0000 and that of Channel 2 is 0001, then Channel 2 leads Channel 1 by 22.5°. Figure 52 is an interconnection block diagram of all four channels of the AD8339. More channels are easily added to the summation (up to 16 when using an AD8021 as the summation amplifier) by wire-OR connecting the outputs as shown for four channels. For optimum system noise performance, the RF input signal is provided by a very low noise amplifier, such as the LNA of the AD8332/AD8334 or the AD8335. In beamforming applications, the I and Q outputs of a number of receiver channels are summed (for example, the four channels illustrated in Figure 52). The dynamic range of the system increases by the factor 10log10(N), where N is the number of channels (assuming random uncorrelated noise). The noise in the 4-channel example of Figure 52 is increased by 6 dB while the signal quadruples (+12 dB), yielding an aggregate SNR improvement of (+12 − 6) = +6 dB. Judicious selection of the RF amplifier ensures the least degradation in dynamic range. The input referred spectral voltage noise density (en) of the AD8339 is nominally ~11 nV/√Hz. For the noise of the AD8339 to degrade the system noise figure (NF) by 1 dB, the combined noise of the source and the LNA should be approximately twice that of the AD8339, or 22 nV/√Hz. If the noise of the circuitry before the AD8339 is less than 22 nV/√Hz, the system NF degrades more than 1 dB. For example, if the noise contribution of the LNA and source is equal to the AD8339, or 11 nV/√Hz, the degradation is 3 dB. If the circuit noise preceding the AD8339 is 1.3× as large as that of the AD8339 (or ~14 nV/√Hz), the degradation is 2 dB. For a circuit noise 1.45× that of the AD8339 (16 nV/√Hz), the degradation is 1.5 dB. Rev. 0 | Page 19 of 36 AD8339 To determine the input referred noise, it is important to know the active low-pass filter (LPF) values RFILT and CFILT, shown in Figure 52. Typical filter values for a single channel are 1.58 kΩ and 1 nF, and implement a 100 kHz single-pole LPF. In the case that two channels are summed, as is done on the evaluation board, the values are the same as for a single channel of the AD8333, namely 787 Ω and 2.2 nF. frequency, thereby increasing the gain. The factor limiting the magnitude of the gain is the output swing and drive capability of the op amp selected for the I-to-V converter, in this instance, the AD8021. If the RF and LO are offset by 10 kHz, the demodulated signal is 10 kHz and is passed by the LPF. The single-channel mixing gain, from the RF input to the AD8021 output (for example, I1´, Q1´) is approximately 1.7 (4.7 dB) for 1.58 kΩ and 1 nF, or 6 dB less when a single channel is operated on the evaluation board (×0.85; −1.3 dB). This, together with the 11 nV/√Hz of AD8339 noise, results in ~18.7 nV/√Hz at the AD8021 output. Because the AD8021, including the 1.58 kΩ feedback resistor, contributes another 6.3 nV/√Hz, the total output referred noise is approximately 19.7 nV/√Hz. This value can be adjusted by increasing the filter resistor while maintaining the corner SUMMATION OF MULTIPLE CHANNELS (ANALOG BEAMFORMING) AD8332, AD8334 LNA OR AD8335 PREAMP Beamforming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals generated from a common source, but received at different times by a multielement ultrasound transducer. Beamforming has two functions: it imparts directivity to the transducer, enhancing its gain and it defines a focal point within the body from which the location of the returning echo is derived. The primary application for the AD8339 is in analog beamforming circuits for ultrasound. AD8339 RFB TRANSMITTER Because any amplifier has limited drive capability, there is a finite number of channels that can be summed. This is explained in detail in the Channel Summing section. 2 2 2 2 I1 Φ 2 T/R SW Q1 Φ www.BDTIC.com/ADI TRANSDUCER RFB 2 2 CFILT I2 Φ * 2 T/R SW 2 2 RFILT ΣI ADC 16-BIT 570kSPS I DATA Q2 Φ AD8021 RFB 2 I3 Φ CFILT AD7665 OR AD7686 2 RFB 2 2 2 2 2 2 Q3 Φ I4 Φ * RFILT ΣQ ADC 16-BIT 570kSPS Q DATA AD8021 2 0° 90° QUADRATURE DIVIDER Q4 Φ SDI CONTROLLER CLOCK DATA SYSTEM TIMING Figure 52. Interconnection Block Diagram for AD8339 Rev. 0 | Page 20 of 36 06587-052 T/R SW T/R SW 2 AD8339 The AD8339 integrates the phase shifter, frequency conversion, and I/Q demodulation into a single package, and directly yields the baseband signal. Figure 53 is a simplified diagram showing the idea for all four channels. The ultrasound wave (USW) is received by four transducer elements, TE1 through TE4, in an ultrasound probe and generates signals E1 through E4. In this example, the phase at TE1 leads the phase at TE2 by 45°. PHASE COMPENSATION AND ANALOG BEAMFORMING Modern ultrasound machines used for medical applications employ an array of receivers for beamforming, with typical CW Doppler array sizes of up to 64 receiver channels that are phase shifted and summed together to extract coherent information. When used in multiples, the desired signals from each of the channels can be summed to yield a larger signal (increased by a factor N, where N is the number of channels), while the noise is increased by the square root of the number of channels. This technique enhances the signal-to-noise performance of the machine. The critical elements in a beamformer design are the means to align the incoming signals in the time domain, and the means to sum the individual signals into a composite whole. CHANNEL SUMMING The circuit shown in Figure 55 of the AD8333 data sheet can be used to sum 32 channels of the AD8339. The reason for this is that the peak output currents of the AD8339 are approximately half of those the AD8333. As is explained in the Channel Summing section of the AD8333 data sheet, the channel-summing limit relates directly to the current drive capability of the amplifier used to implement the active low-pass filter and current-tovoltage converter shown in Figure 52. The maximum sum, when the AD8021 is used, is 16 channels of the AD8339 vs. eight channels of the AD8333; that is, four AD8339s (4 × 4 = 16 channels) can be summed in one AD8021. In traditional analog beamformers incorporating Doppler, a V-to-I converter per channel and a crosspoint switch precede passive delay lines used as a combined phase shifter and summing circuit. The system operates at the carrier frequency (RF) through the delay line, which also sums the signals from the various channels, and then the combined signal is downconverted by a very large dynamic range I/Q demodulator. In a real application, the phase difference depends on the element spacing, λ (wavelength), speed of sound, angle of incidence, and other factors. The signals E1 through E4 are amplified 19 dB by the low noise amplifiers in the AD8334; for lower performance portable ultrasound applications, the combination of the AD8335 and the AD8339 result in the lowest power per channel. For optimum signal-to-noise performance, the output of the LNA is applied directly to the input of the AD8339. In order to sum the signals E1 through E4, E2 is shifted 45° relative to E1 by setting the phase code in Channel 2 to 0010, E3 is shifted 90° (0100), and E4 is shifted 135° (0110). The phase aligned current signals at the output of the AD8339 are summed in an I-to-V converter to provide the combined output signal with a theoretical improvement in dynamic range of 6 dB for the four channels. The resultant I and Q signals are filtered and then sampled by two high resolution analog-to-digital converters. The sampled signals are processed to extract the relevant Doppler information. www.BDTIC.com/ADI Alternatively, the RF signal can be processed by downconversion on each channel individually, phase shifting the downconverted signal, and then combining all channels. The AD8333 and the AD8339 implement this architecture. The downconversion is done by an I/Q demodulator on each channel, and the summed current output is the same as in the delay line approach. The subsequent filters after the I-to-V conversion and the ADCs are similar. TRANSDUCER ELEMENTS TE1 THROUGH TE4 CONVERT US TO ELECTRICAL SIGNALS AD8332 CH 1 PHASE SET FOR 135° LAG S1 19dB LNA 19dB LNA CH 2 PHASE SET FOR 90° LAG S2 E2 CH 3 PHASE SET FOR 45° LAG S3 19dB LNA CH 4 PHASE SET FOR 0° LAG S4 19dB LNA 45° E3 135° SUMMED OUTPUT S1 + S2 + S3 + S4 E4 Figure 53. Simplified Example of the AD8339 Phase Shifter Rev. 0 | Page 21 of 36 06587-053 90° S1 THROUGH S4 ARE NOW IN PHASE E1 0° 4 US WAVES ARE DELAYED 45° EACH WITH RESPECT TO EACH OTHER AD8339 PHASE BIT SETTINGS AD8339 SERIAL INTERFACE The AD8339 contains a 4-wire SPI-compatible digital interface (SDI, SCLK, CSB, and SDO). The interface comprises a 20-bit shift register plus a latch. The shift register is loaded MSB first. Phase selection and channel enabling information are contained in the 20-bit word. Figure 54 is a bit map of the data-word, and Figure 55 is the timing diagram. ENBL BITS When all four ENBL bits are low, only the SPI port is powered up. This feature allows for low power consumption (~13 mW per AD8339 or 3.25 mW per channel) when the CW Doppler function is not needed. Because the SPI port stays alive even with the rest of the chip powered down, the part can be awakened again by simply programming the port. As soon as the CSB signal goes high, the part turns on again. Note that this takes a fair amount of time because of the external capacitor on the LODC pin. It takes ~10 μs to 20 μs with the recommended 0.1 μF decoupling capacitor. The decoupling capacitor on this pin is intended to reduce bias noise contribution in the LO divider chain. The user can experiment with the value of this decoupling capacitor to determine the smallest value without degrading the dynamic range within the frequency band of interest. The shift direction is to the right with MSB first. Because the latch is implemented with D-flip-flops (DFF) and CSB acts as the clock to the latch, anytime that CSB is low, the latch flipflops monitor the shift register outputs. As soon as CSB goes high, the data present in the register is latched. New data can be loaded into the shift register at any time. Twenty bits are required to program each AD8339 and the data transfers from the register to the latch when CSB goes high. Depending on the data, the corresponding channels are enabled, and the phases are selected. Figure 55 illustrates the timing for two sequentially programmed devices. The SPI also has an additional pin that can be used in a test mode, or as a quick way to reset the SPI and depower the chip. All bits in both the shift register and the latch are reset low when Pin RSTS is pulled above ~1.5 V. For quick testing without the need to program the SPI, the voltage on the RSTS pin should be first pulled high and then pulled to −1.4 V; this enables all four channels in the (I = 1, Q = 0) state (all phase bits are 0000); the channel enable bits are all set to 1. Note that the data is latched into the register flip-flops on the rising edge of SCLK, which means that the data output transitions when SDO goes high. www.BDTIC.com/ADI TO PHASE SELECT AND BIAS BLOCKS FOR TO CHANNEL 1 PHASE TO CHANNEL 2 PHASE TO CHANNEL 3 PHASE TO CHANNEL 4 PHASE CHANNEL ENABLES SELECT BLOCK SELECT BLOCK SELECT BLOCK SELECT BLOCK CSB ENABLE BITS PH SEL CH 1 LATCH LSB CH1 CH2 MSB LSB CH3 CH4 CH1 SHIFT REGISTER LSB CH1 CH2 CH3 MSB LSB CH4 CH1 PH SEL CH 2 CH1 MSB LSB CH1 CH1 CH2 CH1 CH1 MSB LSB CH1 CH2 PH SEL CH 3 CH2 MSB LSB CH2 CH2 CH3 CH2 CH2 MSB LSB CH2 CH3 PH SEL CH 4 CH3 MSB LSB CH3 CH3 CH4 CH4 CH4 MSB CH4 CH3 CH3 MSB LSB CH3 CH4 CH4 CH4 MSB CH4 SDI SCLK SDO TO NEXT AD8339 06587-054 RSTS 06587-055 Figure 54. Serial Interface Showing the 20-Bit Shift Register and Latch Figure 55. Timing Diagram Rev. 0 | Page 22 of 36 AD8339 APPLICATIONS The AD8339 is the key component of a phase shifter system that aligns time-skewed information contained in RF signals. Combined with a variable gain amplifier (VGA) and a low noise amplifier (LNA) as in the AD8332/AD8334/AD8335 VGA family, the AD8339 forms a complete analog receiver for a high performance ultrasound CW Doppler system. LOGIC INPUTS AND INTERFACES The SDI, SCLK, SDO, CSB, and RSET pins are CMOS compatible to 1.8 V. The threshold of the RSTS pin is 1.5 V, with a hysteresis of ±0.3 V. Each logic input pin is Schmitt trigger activated, with a threshold centered at ~1.3 V, and a hysteresis of ±0.1 V around this value. The only logic output, SDO, generates a signal that has a logic low level of ~0.2 V and a logic high level of ~1.9 V to allow for easy interfacing to the next AD8339 SDI input. Note that the capacitive loading for the SDO pin should be kept as small as possible (< 5 pF), ideally only a short trace to the SDI pin of the next chip. The output slew is limited to approximately ±500 μA, which limits the speed when a large capacitor is connected. Excessive values of parasitic capacitance on the SDO pin can affect the timing and loading of data into the next chip’s SDI input. The RSET mechanism also allows the measurement of nonmixing gain from the RF input to the output. The rising edge of the active high RSET pulse can occur at any time; however, the duration should be ≥ 20 ns minimum. When the RSET pulse transitions from high to low, the LO dividers are reactivated on the next rising edge of the 4LO clock. To guarantee synchronous operation of an array of AD8339s, the RSET pulse must go low on all devices before the next rising edge of the 4LO clock. Therefore, it is best to have the RSET pulse go low on the falling edge of the 4LO clock; at the very least, the tSETUP should be ≥ 5 ns. An optimal timing setup would be for the RSET pulse to go high on a 4LO falling edge and to go low on a 4LO falling edge; this gives 10 ns of setup time even at a 4LO frequency of 50 MHz (12.5 MHz internal LO). Check the synchronization of multiple AD8339s using the following procedure: 1. Activate at least one channel per AD8339 by setting the appropriate channel enable bit in the serial interface. 2. Set the phase code of all AD8339 channels to the same logic state, for example, 0000. 3. Apply the same test signal to all devices that generates a sine wave in the baseband output and measure the output of one channel per device. www.BDTIC.com/ADI RESET INPUT The RSET pin is used to synchronize the LO dividers in AD8339 arrays. Because they are driven by the same internal LO, the four channels in any AD8339 are inherently synchronous. However, when multiple AD8339s are used, it is possible that their dividers wake up in different phase states. The function of the RSET pin is to phase align all the LO signals in multiple AD8339s. The 4LO divider of each AD8339 can initiate in one of four possible states—0°, 90°, 180°, and 270°, relative to other AD8339s. The internally generated I/Q signals of each AD8339 LO are always at a 90° angle relative to each other, but a phase shift can occur during power-up between the dividers of multiple AD8339s used in a common array. The LO divider reset function has been improved in the AD8339 over the AD8333. The RSET pin still provides an asynchronous reset of the LO dividers by forcing the internal LO to hang; however, in the AD8339, the LO reset function is fast and does not require a shutdown of the 4LO input signal. 4. Apply a RSET pulse to all AD8339s. 5. Because all the phase codes of the AD8339s should be the same, the combined signal of multiple devices should be N times greater than a single channel. If the combined signal is less than N times one channel, then one or more of the LO phases of the individual AD8339s is in error. LO INPUT The LO input is a high speed, fully differential, analog input that responds to differences in the input levels (and not logic levels). The LO inputs can be driven with a low common-mode voltage amplifier, such as the National Semiconductor DS90C401 LVDS driver. The graph in Figure 21 shows the range of common-mode voltage. Logic families, such as TTL or CMOS, are unsuitable for direct coupling to the LO input. Rev. 0 | Page 23 of 36 AD8339 EVALUATION BOARD Figure 56 is a photograph of the AD8339 evaluation board, and the schematic diagram is shown in Figure 61, Figure 62, and Figure 63. Four single-ended RF inputs can be phase aligned using the LNA inputs of an AD8334 and the 16 phase adjustment options of the AD8339. The RF input signals can be derived from three sources, user selectable by jumpers. Test points enable signal tracing at various circuit nodes. The AD8339 requires dual power supplies, the AD8334 and digital section only a single supply. A 3.3 V on-board regulator provides power for the USB and EEPROM devices. The AD8339 can be configured using the software provided on the CD-ROM included with the board, or using an external digital pattern generator via the 20-pin flat-cable connector. 06587-056 www.BDTIC.com/ADI Figure 56. AD8339 Evaluation Board Rev. 0 | Page 24 of 36 AD8339 CONNECTIONS TO THE BOARD Table 5 is a list of equipment required to activate the board with suggested test equipment, and Figure 59 shows a typical setup. In order to phase align any two RF input signals, the RF and clock inputs must be coherent, that is, from the same timing source. Many laboratory signal generators have this capability, including the Rohde & Schwartz model shown in Table 5. Other signal generators can also be used; the only requirement is that they have external clock inputs and outputs. Selecting the frequency of the generators is quite simple. As an example, select an RF frequency of interest, for example 5 MHz. Then select the 4LO frequency, which is four times the RF frequency, in this example 20 MHz. The output frequency is 0 Hz—note that the AD8021 outputs are at either a positive or negative dc voltage under this condition under perfect RF and 4LO frequency lock; more likely the signal is slowly varying if the lock is not perfect. To detect an output, advance or retard the RF frequency by the desired baseband frequency. A baseband frequency of 10 kHz at the output results from an RF frequency of 5.01 MHz or 4.99 MHz. Table 5. Recommended Equipment List Description Signal Generators (2), with Synchronizing Connectors 4-Channel Oscilloscope Suggested Equipment Rohde & Schwartz SMT3 or equivalent Tektronix DPO7104 or equivalent Agilent E3631A or equivalent Tektronix P6104 or equivalent Using a common input signal source as shown in Figure 59, the same input is applied to all four channels of the AD8339. To observe an output at the I or Q connectors, simply enable the appropriate channel or channels using the menu shown in Figure 60. For example, if only Channel 1 is enabled and the phases set to 0°, a waveform is seen at the I1 + I2 and Q1 + Q2 outputs. If Channel 2 is enabled with the phase also set to 0°, the amplitude of the waveforms double. If Channel 1 is 0° and Channel 2 phase set to 180°, the output becomes zero because the phases of the two channels cancel. When using the common input drive mode, it is important that only the top two positions of P4A and P4B be used to avoid shorting the LNA outputs together. Independent Channel Drive Independent input mode means that each channel is driven by an LNA. Of course, the LNA inputs of the AD8334 can be driven by up to four independent signal generators or from a single generator. If the user chooses this mode, it is important not to connect the LNA inputs in parallel because of the active matching feature. Any standard splitter can be used. AD9271 Input Drive Connectors P3A, P3B and P4A, P4B are configured to route input signals from the AD8334 LNA outputs or from an AD9271 evaluation board. The AD9271 is an octal ultrasound front end with a 12-bit ADC for each channel. When using an AD9271 as an input drive, consult the AD9271 data sheet for setup details. www.BDTIC.com/ADI Power Supplies Scope Probes (4) TEST CONFIGURATIONS The three test configuration options for the AD8339-EVALZ are common input, independent input, and AD9271 drive. Common Input Signal Drive Figure 57 is a block diagram showing the simplest way to use the evaluation board, with a common signal applied to all four AD8339 inputs in parallel. Boards are configured this way as shipped. The inputs of each of the channels are connected in common by means of jumpers, as shown in Table 6, although they can be just as easily connected to any of the AD8334 LNA outputs. As seen in Figure 62, two pairs of summing amplifiers provide the I and Q outputs so that Channel 1 and Channel 2 can be observed independently of Channel 3 and Channel 4. The AD9271 board is attached to the AD8339 by inserting the three plastic standoffs into the three guide holes in the AD8339EVALZ board; all the jumpers in P3 and P4 are removed. The bottom connectors of the AD9271 board engage P3 and P4 and route the LNA outputs of the AD9271 to the AD8339. Figure 58 is a photograph of the two boards attached. Table 6. P3, P4 Input Jumper Configuration Common Input P4A-1 to P4B-1, top two positions (2) RF12N, RF12P, RF23N, RF23P, RF34N, RF34P Rev. 0 | Page 25 of 36 Independent Input P3A-1 to P3B-1, P4A-1 to P4B-1 P3A-1 to P3B-1, P4A-1 to P4B-1, all positions (8) AD8339 COMMON SIGNAL PATH AD8334 LNA AD8339 I1 CH1 RF Q1 Q1 + Q2 I TO V I1 + I2 I2 CH2 RF Q2 I TO V I3 CH3 RF Q3 I TO V I3 + I4 I4 Q4 Q3 + Q4 I TO V 06587-057 CH4 RF Figure 57. AD8339 Test Configuration—Common Signal Input Drive 06587-058 www.BDTIC.com/ADI Figure 58. AD8339-EVALZ with AD9271 Attached as Input Source Rev. 0 | Page 26 of 36 AD8339 TOP: SIGNAL GENERATOR FOR 4LO INPUT (e.g., 20MHz, 1Vp-p) BOTTOM: SIGNAL GENERATOR FOR RF INPUT (e.g., 5.01MHz) POWER SUPPLY PERSONAL COMPUTER SYNCHRONIZE GENERATORS USB CABLE +5V –5V POWER SPLITTER 4LO INPUT www.BDTIC.com/ADI 06587-059 OUTPUTS Figure 59. AD8339-EVALZ Typical Test Setup Rev. 0 | Page 27 of 36 AD8339 Using the SPI Port Channel and phase selection are accessed via the SPI port on the AD8339 and the evaluation board provides two means of access. If it is desired to exercise the SPI input with custom waveforms, the SDI, SCLK, and CSB are available at the auxiliary connector P1. A digital pattern generator can be programmed in conformance with the timing diagram shown in Figure 55. The most convenient way to select channels and phase delays is through the USB port of a PC using the executable program provided on the CD-ROM or the Analog Devices, Inc. website. Copy the .EXE and .MSI files into the same folder on the PC. Double-click on the .EXE file and the program will self-install and place a shortcut on the desktop. Double-clicking on the desktop icon brings up the control menu, as shown in Figure 60. The menu consists of an array of radio buttons that are self- explanatory. Channels are enabled or disabled by clicking on the boxes in the list, and the 16 phase options are selected from a drop-down menu for each of the channels. Hardwired Jumpers Hardwired jumpers provide for interconnection of channels and as a means for measuring output voltages at various strategic modes. When shipped, the board is configured to connect all the AD8339 RF inputs to a single LNA output. In this configuration, the phases of the four channels can be shifted throughout the full range and the outputs viewed on a multichannel scope using one of the channels as a reference. To operate all the LNA channels independently, it is only necessary to move the input shorting jumpers to the channel RF outputs. 06587-060 www.BDTIC.com/ADI Figure 60. SPI Software Control Menu Table 7. Jumper and Header List Jumper, Header AxSHT CSB CSBG EN12, EN34 G12, G34 I1234 Q1234 RF1 to RF4 RSTS RSET SDIG SCLK SDI SLKG VO1 to VO4 4LO Description Shorts the current summing outputs—shipped omitted Connects the chip select input to the connector or the USB inputs—normally connected to USB (test) Grounds the CSB input—shipped omitted Enables or disables Channel 1 through Channel 4—boards shipped enabled Connects gain pin for Channel 1 through Channel 4 to ground—boards are shipped with these jumpers inserted Sums all four I-channel current outputs together—shipped omitted Sums all four Q-channel current outputs together—shipped omitted Test points for the LNA outputs—a differential probe fits these Resets the SPI input—shipped omitted Resets the local oscillator input—shipped omitted Grounds the SDI input Connects the S-clock input to the connector or the USB inputs—normally connected to USB (test) Connects the serial data input to the connector or the USB input—normally connected to USB (test) Grounds the S-clock input—shipped omitted Test points for the VGA outputs—a differential probe fits these Test pins for the 4LO level shifter output—a differential probe fits these Rev. 0 | Page 28 of 36 AD8339 LOP1 LON1 RF1 C67 0.1μF C43 0.1μF R44 20Ω LON2 R43 20Ω RF2 LOP2 5 C44 0.1μF C45 0.1μF 5V 8 L17 120nH C87 0.1μF C88 0.1μF 9 VIN2 VPS 2 U1 AD8334 VPS 3 49 50 VCM1 51 EN34 52 EN12 53 54 GAIN12 LOP2 VCM2 COM12 48 VOH1 47 NC VOL 1 46 NC VPS12 45 VOL 2 44 NC VOH2 43 NC COM12 42 MODE 41 NC 40 VIP3 VOH3 38 NC 12 LOP3 VOL 3 37 13 L14 120 nH 5V C65 0.1μF C55 0.1μF L8 120nH L9 120 nH C62 0.1μF IN4S C12 22pF CFB4 18nF R47 20Ω R48 20Ω L12 120nH C63 0.1μF C56 0.1μF C64 0.1μF 5V NC 33 32 31 30 29 28 27 VPS4 26 VIP4 VIN4 25 R64 0Ω C49 0.1μF C50 0.1μF RFB4 274Ω IN4 24 23 LON4 22 21 IN3S VCM3 INH3 VCM4 16 HILO 34 NC CLMP34 VOH4 GAIN34 LMD3 LOP4 15 COM4X 35 NC LMD4 VOL 4 COM34 L15 120 nH 36 COM3X C10 22pF C61 0.1μF 39 14 17 COM3 C48 0.1μF VPS34 LON3 20 RFB3 274Ω CFB3 18nF 11 INH4 LON3 COM34 19 R45 20Ω VIN3 COM4 C47 0.1μF 10 18 R46 20Ω RF3 IN3 55 58 59 60 61 62 63 PIN 1 IDENTIFIER C59 0. 1μF www.BDTIC.com/ADI C46 0. 1μF LOP3 C58 0.1μF 6 VIP2 7 L16 120 nH VPS1 LON2 DIS R63 0Ω VIN1 56 4 LOP1 COM2X LO N1 3 COM1X LMD2 INH1 2 EN34 DIS C57 0. 1μF C85 0.1μF RF4 5V LON4 LOP4 Figure 61. Schematic—LNA Section Rev. 0 | Page 29 of 36 06587-061 RFB2 274Ω EN EN12 C66 0.1μF CLMP12 CFB2 18nF COM2 INH2 COM1 64 C60 0.1μF 1 L13 120nH C53 0.1μF C54 0.1μF C68 0.1μF C8 22pF 5V EN C86 0. 1μF C6 22pF L7 IN2 120 nH IN2S RFB1 274 Ω 57 IN1S CFB1 18nF R49 20Ω VIP1 L10 120nH LMD1 IN1 5V R50 20Ω AD8339 5V R3 1kΩ R4 1kΩ P1 CSB SCLK (SHT3) SDI RSTS R32 2.8kΩ R61 0Ω VPIS R62 0Ω R59 0Ω 2 R72 2.8kΩ VPOS 28 VPOS 27 DUT AD8339 SCLK - 1 I 1234 R14 0Ω 6 I1+I2 5 + 3 Q1234 C81 2.2nF 7 AD8021 8 R18 0Ω C82 5PF 4 -VA C24 0.1µF VPOS C30 0.1µF U7 DSC90C401 RF3P I3OP 22 R8 0Ω RF3N Q3OP 21 R7 0Ω R28 C28 3.48kΩ 0.1µF RF34P RF34N SDO R34 2.8kΩ N23 P12 P23 R51 0Ω I4O P 2 8 R6 0Ω 3 I4OP - C80 5PF 4 C22 0. 1µF 5V VNEG R42 787 Ω 7 1 U6 C32 2.2nF 2 Q4OP 8 3 AD8021 5 + 4 R38 Q3+Q4 0Ω 6 C33 5PF -VA C52 0. 1µF 2 1 LON4 LOP4 1 LON3 -VA C51 0.1µF R2 0Ω I3+I 4 5 + R5 0Ω C20 0.1µF R54 49.9Ω R11 0Ω 6 AD8021 LOP C79 2.2nF 7 P34 LOP3 LON2 LOP2 LON1 C21 0. 1µF R9 0Ω 1 COMPONENTS SHOWN IN GRAY ARE NOT INSTALLED 2 1 1 P4A P4B VA VA R36 5.23kΩ R30 4.22kΩ N34 R10 787 Ω C18 0.1µF VPOS W7 W8 RF3P N12 SDO R56 0Ω W6 SDO RF2N W11 RF2P W10 C17 0.1µF RF1N W13 R33 2. 8kΩ 5V W9 RF3N VPOS R37 1.5kΩ VNEG C29 0. 1µF C19 0.1µF R65 4.22kΩ 4 2 17 12 11 VPOS VPOS R57 0Ω VNEG 23 Q4OP VNEG LODC VPOS COMM 10 24 15 9 VNEG 14 RF4N 8 R69 2.8kΩ R27 100 Ω 4LO VPOS 13 RF4P R58 0Ω 26 25 SDO 7 4LOP 4LON 16 RF23N RF23P SLKG 5 R70 2.8kΩ RF1P W12 2 R19 0Ω 29 R13 787 Ω C23 0.1µF VA R12 0Ω Q1+Q 2 -VA www.BDTIC.com/ADI VPOS RF3N COMM CSBG 6 CSB C16 0.1µF 5V R67 5.23kΩ LOP1 R21 0Ω COMM RF3P C26 0. 1µF 31 34 RSET 35 36 37 38 I2OP C84 5PF 4 Q1OP 30 R17 0Ω 6 5 + 3 Q2OP 7 AD8021 8 VNIS 3 4 - 1 VPOS R66 4.22kΩ 2 -5V PIN 1 IDENTIFIER RF2P C83 C25 0. 1µF 2.2nF R15 0Ω L1 120 nH C27 R20 0. 1µF 0Ω CO MM RF2N RF1N 1 RF1P RSTS R71 2.8kΩ RF2P 39 RF12P 40 RF2N 19 VNEG VPOS RF12N R60 0Ω VA I1OP C1 0.1µF SDI R68 5.23kΩ 15 17 C31 0.1µF RSET VPOS 5V 16 18 20 R16 787 Ω L2 120 nH 5V RF1P RF1N R29 4.22kΩ 9 11 13 VNEG R31 2.8kΩ W1 SDI (SHT3) 10 12 14 32 R35 5.23kΩ W2 Q1OP 5V SDO 3 5 7 33 SLKG W4 CSB (SHT3) SCLK 1 4 6 8 I1OP CSBG 2 FROM AD9271 P3A P3B C34 0.1 µF 5V U7 1 DSC90C401 7 8 FROM LNA OUTPUTS 6 5 Figure 62. Schematic—IQ Demodulator and Phase Shifter Rev. 0 | Page 30 of 36 06587-062 R1 1kΩ AD8339 5VS -5VS RED VAS GRN -VAS ORG BLUE PLUS 5V MINUS -VAS GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 VAS C9 1 µF L11 10V 120 nH W3 + 3 2 1 OUT GND IN -5VS 5VS C77 0.1 µF A6 ADP3339AKC-3.3 OUT TAB C14 + 10µF 25V L6 120 nH C13 10µF 25V + L5 120 nH C11 + 10µF 25V L4 120 nH C15 10µF 25V+ L15 120 nH C38 0. 1µF C37 0. 1µF C36 0. 1µF C35 0. 1µF 3.3V 5V 3.3V VA -5V BLK TEST LOOP (8) -VA R41 100kΩ C5 22pF C76 0.1 µF C7 0.1 µF NC Y1 24MHz 3.3V 2 3 C69 0.1 µF 4 5 C3 12 pF C2 12 pF AVCC 43 3. 3V VCC WAKEUP PD0/FD8 PD1/FD9 PD2/ FD10 PD3/ FD11 PD4/FD12 PD5/FD13 PD6/FD14 GND VCC RDY1/SLWR NC NC NC NC 48 47 46 45 44 RESET # GND PA7/FLAGD/SLCS PA6/PKTEND XTALOUT PA5/ FIFOADR1 XTALIN 42 R40 100kΩ 41 C4 22pF 40 39 38 CSB(SHT2) SCLK(SHT2) SDI (SHT2) www.BDTIC.com/ADI C72 0.1 µF Z1 24LC00/ P 1 A0 2 A1 VCC R52 22. 1kΩ R53 22. 1kΩ 8 WP 7 3 A2 SCL 6 4 VSS SDA 5 18 19 20 21 22 23 24 25 NC 17 VCC GND 26 27 NC 36 NC 35 NC 34 NC 33 NC 32 31 NC 3.3V C75 0.1 µF 30 NC 29 NC 28 C74 0.1 µF C73 0.1 µF R22 0Ω 3.3V 3.3V 16 NC 15 37 GND CTL0/FLAGA PB7/FD7 RESERVED PB6/FD6 CTL1/FLAGB PB5/FD5 IFCLK/PE0/TOUT SCL R39 10kΩ CTL2/FLAGC NC 14 GND PB4/FD4 13 NC VCC NC 12 PA0/ INT0# VCC PB3/FD3 C71 0.1 µF GND NC 11 PB2/FD2 CR1 3. 3V NC 555 499Ω 10 PA1/ INT1# PB1/FD1 1 5V PA2/SLOE DMINUS NC VBUS 9 DPLUS PB0/FD0 D- PA3/WU2 U2 CY7C6801 3A-56LFXC NC 8 AVCC VCC GND 4 7 C70 0.1 µF PA4/ FIFOADR0 GND 3.3V 2 6 SDA 3.3V A7 USB TYPE B D+ 3 RDY0/SLRD NC NC NC NC 52 51 50 49 PD7/FD15 1 CLKOUT/PE1/T1OUT NC NC 54 53 55 GND 56 R23 0Ω R24 0Ω R25 0Ω R26 0Ω Figure 63. Schematic—USB Rev. 0 | Page 31 of 36 06587-063 C78 0.1 µF AD8339 AD8339-EVALZ ARTWORK Figure 64 through Figure 67 show the artwork for the AD8339-EVALZ. 06587-064 www.BDTIC.com/ADI 06587-065 Figure 64. AD8339-EVALZ Component Side Copper Figure 65. AD8339-EVALZ Wiring Side Copper Rev. 0 | Page 32 of 36 06587-066 AD8339 Figure 66. AD8339-EVALZ Component Side Silkscreen 06587-067 www.BDTIC.com/ADI Figure 67. AD8339-EVALZ Assembly Rev. 0 | Page 33 of 36 AD8339 Table 8. Bill of Materials Qty 1 1 24 Name Test Loop Test Loop Header Description Green Blue Berg 2 1 1 Red 3.3 V regulator 1 Test Loop Integrated Circuit Connector 63 Capacitor 2 6 1 4 Capacitor Capacitor Capacitor Capacitor 4 4 4 Capacitor Capacitor Capacitor 1 12 LED Test Loop 1 7 9 Integrated Circuit Header Test Loop Berg 3 Black 9 Connector SMA right angle 17 Bead Ferrite, 120 μH 1 3 Connector Connector 2 Connector 2 3 31 Connector Resistor Resistor 20-pin RT/A latch eject Header, vertical, 1" 1X4 30AU Header, vertical, 1" 3X4P 30AU Header, 100 dual str, 2 × 4 1.0 kΩ, 1/16 W, 1%, 0603 0 Ω, 5%, 1/10 W, 0603 4 1 1 1 Resistor Resistor Resistor Resistor 787 Ω, 1%, 1/16 W, 0603 100 Ω, 1%, 1/16 W, 0603 3.48 kΩ, 1%, 1/16 W, 0603 1.5 kΩ, 1%, 1/16 W, 0603 Right angle USB, Type B, 4-position 0.1 μF, 16 V, 0603 X7R 12 pF, 50 V, 5%, 0603 22 pF, 50 V, 5%, 0603 1 μF, 6.3 V, 10%, 0603 Tantalum 10 μF, 10 V, 20%, 3216, SMD 2.2 nF, 50 V, 10%, 0603 5 pF, 50 V, 0603 0.018 μF, 10%, 50 V, X7R, 0603 Green, USS type, 0603 Purple Reference Designator −5VS −VAS 4LO, I1234, IN1S, IN2S, IN3S, IN4S, MINUS, PLUS, Q1234, RF1, RF2, RF3, RF4, RF12N, RF12P, RF23N, RF23P, RF34N, RF34P, VNIS, VPIS, WQ3, W18, W19 +VS A6 Manufacturer Components Corp. Components Corp. Molex Part Number TP-104-01-05 TP-104-01-06 22-10-2021 Components Corp. Analog Devices TP-104-01-02 AD3339AKCZ-3.3-RL A7 Tyco 292304-1 C1, C7, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C34, C35, C36, C37, C38, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C60, C61, C62, C63, C64, C65, C66, C67, C68, C69, C70, C71, C72, C73, C74, C75, C76, C77, C78, C85, C86, C87, C88 C2, C3 C4, C5, C6, C8, C10, C12 C9 C11, C13, C14, C15 Kemet C0603C104K4RACTU AVX Panasonic Panasonic Nichicon 06035A120JAT2A ECJ-1VC1H220J ECJ-1VB0J105K F931A106MAA www.BDTIC.com/ADI Quad I/Q demodulator C32, C79, C81, C83 C33, C80, C82, C84 CFB1, CFB2, CFB3, CFB4 Panasonic Panasonic AVX ECJ-1VB1H222K ECJ-1VC1H050C 06035C183KAT2A CR1 CSB, CSB-TP, I1OP, I4OP, Q1OP, Q4OP, RESET, RSTS-TP, SCLK-TP, SDI, SDI-TP, SDO-TP U8 Panasonic Components Corp. LNJ314G8TRA TP-104-01-07 Analog Devices AD8339ACPZ EN12, EN34, SDO, W1, W2, W4, W5 GND1, GND2, GND3, GND4, GND5, GND6, GND7, GND8, GND9 I1 + I2, I3 + I4, IN1, IN2, IN3, IN4, LOP, Q1 + Q2, Q3 + Q4 L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15, L16, L17 P1 P2, Positions W14 to W15, Positions W16 to W17 Positions 3A to 3B, Positions 4A to 4B Molex Components Corp. 22-10-2031 TP-104-01-00 Amphenol 901-143-6RFX Murata BLM18BA750SN1D 3M Molex 3428-5603 22-10-2041 Samtec TSW-104-14-G-T Positions W10 to W13, Positions W6 to W9 R1, R3, R4 R2, R5, R6, R7, R8, R9, R11, R12, R14, R15, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R38, R51, R56, R57, R58, R59, R60, R61, R62, R63, R64 R10, R13, R16, R42 R27 R28 R37 Sullins Panasonic Panasonic S2011E-04-ND ERJ-3EKF1001V ERJ-2GE0R00X Panasonic Panasonic Panasonic Panasonic ERJ-3EKF7870V ERJ-3EKF1000V ERJ-3EKF3.48K ERJ-3EKF1501V Rev. 0 | Page 34 of 36 AD8339 Qty 1 2 8 2 1 1 4 1 1 4 1 1 1 1 Name Resistor Resistor Resistor Resistor Resistor Resistor Resistor Integrated Circuit Integrated Circuit Integrated Circuit Integrated Circuit Test Loop Crystal Integrated Circuit Description 10 kΩ, 1%, 1/16 W, 0603 100 kΩ, 1%, 1/16 W, 0603 20.0 Ω, 1%, 1/16 W, 0603 22.1 kΩ, 1%, 1/16 W, 0603 49.9 Ω, 1%, 1/16 W 499 Ω, 1%, 1/16 W, 0603 274 Ω, 1%, 1/16 W, 0603 Quad VGA Reference Designator R39 R40, R41 R43, R44, R45, R46, R47, R48, R49, R50 R52, R53 R54 R55 RFB1, RFB2, RFB3, RFB4 U1 Manufacturer Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Analog Devices Part Number ERJ-3EKF1002V ERJ-3EKF1003V ERJ-3EKF20R0V ERJ-3EKF2212V ERJ-3EKF49R9V ERJ-3EKF4990V ERJ-3EKF2740V AD8334ACPZ-REEL7 MCU USB peripheral, high speed, 56 QFN Amplifier U2 Cypress CY7C68013A-56LFXC U3, U4, U5, U6 Analog Devices AD8021ARZ LVDS driver U7 DS90C401M Orange 24.00 MHz, 12 pF, HC-49/US EEPROM VAS Y1 National Semiconductor Components Corp. ECS Inc. Microchip Technology 24LC00/P Z1 TP-104-01-03 ECS-240-12-4X www.BDTIC.com/ADI Rev. 0 | Page 35 of 36 AD8339 OUTLINE DIMENSIONS 6.00 BSC SQ 0.60 MAX 0.60 MAX PIN 1 INDICATOR 31 30 TOP VIEW 0.50 BSC 5.75 BCS SQ 0.50 0.40 0.30 12° MAX (BOT TOM VIEW) 10 11 21 20 0.25 MIN 4.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.20 REF 4.25 4.10 SQ 3.95 EXPOSED PAD THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 101306-A PIN 1 INDICATOR 40 1 Figure 68. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters ORDERING GUIDE www.BDTIC.com/ADI Model AD8339ACPZ 1 AD8339ACPZ-R71 AD8339ACPZ-RL1 AD8339-EVALZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06587-0-8/07(0) Rev. 0 | Page 36 of 36 Package Option CP-40-1 CP-40-1 CP-40-1