Download AN-737: How ADIsimADC Models an ADC

AN-737
APPLICATION NOTE
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How ADIsimADC™ Models an ADC
by Salina Downing and Brad Brannon
Converter Modeling
Converter modeling has often been overlooked, omitted,
or accomplished using an ideal data converter model.
With more and more systems using mixed-signal technology, the importance of system modeling is ever
increasing. Coupled with shortened design cycles and
pressure for first pass success, this drives the continuing
importance of complete system modeling. ADIsimADC
has been developed to answer this growing need.
Often ideal converter models are used for functional
modeling, but this fails to give the required details of
performance to determine if a particular device will meet
the desired goals of the system. This is why ADIsimADC
has been developed. For the first time, a model will provide a means for customers to validate performance of
a particular converter in their system, using their conditions to determine the applicability of a selected device.
While this model doesn’t emulate every characteristic of
an ADC, it goes a very long way towards achieving the
goal of allowing customers to model real converters in
their system simulations.
Bit Exact vs. Behavioral
A bit exact model is a model that, given a known stimulus,
provides a known and predictable output. ADIsimADC is
not a bit exact model. These types of models are often
found in digital systems. In dealing with analog functions, there is never a known response for a given input
because of noise, distortion, and other nonlinearities.
While some portion of the response may be predictable,
much of the remainder is subject to distortion, noise, and
even part-to-part variation. Additionally, to provide a bit
exact model would require providing circuit simulation
files, such as SPICE models, that process transient
response. However, these models are large, complex,
very slow and, in the end, provide limited accuracy. A
reduced or equivalent SPICE model would reduce the
complexity, but not be able to provide adequate modeling of fine details of static and dynamic performance.
A behavior model eliminates the complexity, and at the
same time, allows modeling of fine performance details
not possible to attain with a circuit file. ADIsimADC acts
as a standalone converter evaluation tool, and can also
be included in many other third party simulation tools,
including MATLAB® and C++.
REV. A
Model vs. Hardware
Modeling a system, or just an ADC, should never be a
substitute for building and characterizing a real system.
As any engineer will tell you, it is one thing to model a
circuit, but it is another matter to actually build it and
test it.
As with any analog or mixed-signal device, proper layout
and configuration is required to achieve the performance
shown in simulation. Therefore, it is important that all
layout rules and guidelines be followed as shown in
the product data sheet (figure 1). An example is the
importance of providing adequate power supply bypass
capacitors. Because mixed-signal devices include some
amount of digital circuitry, digital switching noise is often
a problem, and failure to provide capacitors to moderate
these switching currents can significantly reduce performance of even the best devices. Other support devices
are often required around the converter, including additional capacitors, inductors, and resistors. The best way
to know what is required is to consult the product data
sheet and the evaluation board schematic.
Which Specifications Are Important to Model?
ADIsimADC is targeted to provide realistic performance
of real devices. Which specification is important to
model depends on what kind of analysis you are trying
to perform. For example, control loops need accurate
transfer function and delay information, while radio systems may require an accurate representation of noise
and distortion. ADIsimADC models many of the critical
specifications of data converters, including: offset, gain,
sample rate, bandwidth, jitter, latency, and both ac and
dc linearity.
This application note describes these specifications in
detail and how ADIsimADC treats them.
Gain, Offset, and DC Linearity
The full-scale range of the converter is defined by the
design of the converter. It may be fixed, selectable, or
variable. Gain error of a converter is the deviation from
the nominal value, often called the input span. Since an
ADC is a voltage input device, this value is specified in
volts at dc or low frequency.
Offset is defined as the deviation of the actual major
carrier transition from one-half of the full-scale range
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AN-737
of the converter. This can be measured by shorting the
input(s) to one-half of the full scale. Many devices have
internal connections that bias the input pins to set up
the input common - mode voltage (Figure 2). On such
devices, it is not necessary to make this connection
externally. The input may be floated in the case of a
single - ended input or shorted together in the case of
differential inputs. Devices that do not have connec tions internally to the common - mode voltage must
be externally connected (Figure 3). As with input
span, the common - mode voltage may either be fixed
or may be adjustable. The data sheet should be con sulted to determine how your device is configured.
BUF
VINB
VCL
CPIN
–
+
QS2
The dc linearity (Figure 4) for an ADC is determined by
the quantization method and the static transfer function of
the converter. There are many types of converters, each of
which has a unique transfer function and will produce different results at dc and at high frequency. In the Addendum,
see the first and second references for more information
about the different types of converters, and how the transfer
function affects a converter’s performance.
T/H
VCL
Figure 2. Typical Analog Input with Internal
Common-Mode Voltage
2
QH1 CS
ADIsimADC does not allow either the input span or the
common-mode to be changed. Different converter models are provided for devices with multiple input spans.
The common-mode is fixed for all devices and may not
be changed. If it is desired to model a system that uses
a different common-mode range, the difference may be
subtracted by an external offset.
VREF
BUF
QS1
Figure 3. Typical Analog Input Without Internal
Common-Mode Voltage
500
AIN
CS
CH
T/H
BUF
AVCC
QS1
CPAR
500
+5VA
ITE
+3P3VD
+3P3V
U4 5 NC7SZ32
1
4 OPT_LAT
2
GND
E4
3
DR_OUT
E3
BUFLAT
E5
PECL ENCODE OPTION3
+5VA
F
VREF
+5VA
5
R6
25
U3
+5VA
R151
176.4
R5 499
1
2
T3
6
5
3
4
ADT4-1WT 4:1
IMPEDANCE
RATIO
5
12
6
11
7
10
8
9
C30
0.1 F
J1
1
2
3
4
5
D0
Q0
D1
Q1
D2
Q2
Q3
D3
6 D4
7
D5
8 D6
9 D7
10 GND
RN2
(SEE NOT
20
19
1
18
2
17
3
16
4
15
5
14
Q5
13
Q6
12
Q7
11
CK
6
7
Q4
CLO
8
BUFLAT
74LCX574
BUFLA
D4
D5
GND
D6
D7
DVCC
D8
D9
D10
1
AD6644/ AD6645
U2
1
16
2
2
15
3
39
3
14
4
38
4
13
5
37
5
12
6
36
D0
35
DMID
34
GND
33
DVCC
32
OVR
31
DNC
30
AVCC
29
GND
28
AVCC
27
GND
6
11
7
7
10
8
8
9
D3
D1
C2
3
+5VA
R7
25
VREF
4
5
VREF
GND
8
2
13
D2
AVCC
6
AD8138
4
GND
GND
5
ENC
6
ENC
7
GND
8
AVCC
9
AVCC
10
GND
11
AIN
12
AIN
13
GND
2
R4 499
DVCC
C1
4
-COUPLED AIN OPTION2
1
2
3 CR1
1
5V
1
D11
C34
0.1 F
3
S2812
4
52 51 50 49 48 47 46 45 44 43 42 41 40
GND
C33
0.1 F
AL
3
14
VCC
RN3
(SEE NOTE 4)
V1
AVCC
+3P3V
EL16
15
3
C32
0.1 F
D12
R14
100
2
OUT_EN
GND
D13
R12
100
DR_OUT
GND
6
Q
VEE 5
R13
66.5
2
+3P3V
+5VA
DRY
+5VA
R11
66.5
AVCC
8
Q 7
GND
VCC
16
PREF
OUT EN
D0
D1
D2
D3
D4
D5
D6
9 D7
10
GND
C
74LCX5
+3P3V
+5VA
+5VA
AVCC
R9
348
1
1
GND
R10
619
U7
RN1
(SEE NOTE 4)
+3P3VD
GND
VCH
CPAR
VINA
AVCC
AIN
QS2
CPIN
AVCC
VCH
CH
14 15 16 17 18 19 20 21 22 23 24 25 26 NOTES
1. R2 IS INSTALLED FOR INPUT MATCHING
R15 IS INSTALLED FOR INPUT MATCHING
R2 IS NOT INSTALLED.
+5VA +5VA +5VA
+5VA
+5VA 2. AC-COUPLED AIN IS STANDARD. R3, R4,
IF DC-COUPLED AIN IS REQUIRED, C30,
C8
C7
3. AC-COUPLED ENCODE IS STANDARD. C
0.1 F
0.1 F
IF PECL ENCODE IS REQUIRED, CR1, AN
4. IF AD6644 IS USED: VALUE FOR RN1–RN
IF AD6645 IS USED: VALUE FOR RN1–RN
F1 2
1
+5VA
FERRITE
C2
C19
C20
C21
C16
C17
C18
C40
10 F
0.01 F
0.01 F
0.01 F
0.1 F
0.01 F
0.01 F
0.01
+3P3VIN
–5V
+3P3V
1
+
C1
10 F
C9
0.1 F
C10
0.1 F
C11
0.01 F
C12
0.01 F
C13
0.01 F
F4
2
C14 FERRITE
0.01 F
C2
0.1
Figure 1. Typical Evaluation Board Schematic: Shows Typical Support Components
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REV. A
AN-737
SNR, WORST-CASE SPURIOUS (dB AND dBc)
100
95
WORST SPUR @ AIN = 2.2MHz
90
85
80
75
SNR @ AIN = 2.2MHz
70
65
15
45
60
75
ENCODE FREQUENCY (MHz)
90
105
Figure 5. Typical Converter Performance vs.
Sample Rate Bandwidth
Figure 4. Typical Converter DNL, an Important
Contributor to the Converter Transfer Function
Sample Rate
Converter performance changes as both the sample
rate and analog input frequency change. From a
sample rate point of view, most good converters pro vide consistent performance from the minimum to the
maximum specified sample rates (Figure 5). At sample
rates below the minimum, some converters will fail to
operate properly. This may be due to charges stored on
on- chip capacitors discharging or drooping, causing
incorrect data conversion. Therefore, the data sheet
should be consulted to determine the minimum usable
sample rate. Above the maximum sample rate, one of
two problems may occur. The device may not be able
to pass on- chip digital signals from one stage to the
next. This is the result of running out of setup or hold
time on- chip. The other problem is failure of a critical
analog signal to stabilize during the time allocated to
the process. One such example is acquisition time for
a hold capacitor. As before, the data sheet should be
consulted to determine the maximum sample rate.
ADIsimADC uses the specified sample rate to determine how the converter should perform. However,
outside the specified range of the device, the model
will produce all zero results.
A converter’s performance will roll-off according to its
frequency response as the analog input frequency
increases (Figure 6). This is modeled in ADIsimADC
and results in a reduced response within the model.
To counter this loss, the input signal amplitude must
increase above the span specified as the default for the
model, resulting in an input that appears to be above the
full-scale range of the converter. In reality, this signal is
attenuated by package and device parasitics, as well as
the filter formed by the hold capacitor of the sampleand-hold amplifier (SHA), and, therefore, the signal is
actually within the specified span.
GAIN (FS INPUT)
FPBW = 1MHz
GAIN
ENOB
ENOB (FS)
Bandwidth
As the analog input frequency is increased, attenuation in the amplitude response effectively increases the
apparent full-scale range of the converter, causing a
roll-off in the response of the converter. The frequency
where the response has diminished by 3 dB is called the
3 dB bandwidth of the converter.
REV. A
30
ENOB (–20dB INPUT)
1
10
1
10
100
ADC INPUT FREQUENCY (Hz)
1
10M
Figure 6. Typical Converter Analog Bandwidth
Distortion: Dynamic and Static
Due to an ADC’s finite bandwidth, there is also a fundamental slew rate limitation, or dynamic limitation. This
slew rate limitation is one source of distortion within an
ADC. As the input frequency of a data converter is swept
from dc to some upper frequency, the SFDR performance and the harmonic performance of the converter
will decline (Figure 7).
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AN-737
ADIsimADC attempts to model the nominal performance
of the data converter. While it does an excellent job,
some part-to-part variation is normal. The data sheet
should be consulted to determine what performance
variation can be expected.
100
95
WORST OTHER SPUR
85
Jitter
In addition to the analog input slew rate limitations of
the converter, one of the most difficult aspects of sampling high frequency analog signals is jitter. Jitter is the
sample-to-sample variation in the sampling process at
the front end of every data converter. At low analog
input frequencies, the jitter is negligible. However at
high analog input frequencies, errors made in the analog sampling process due to jitter can cause significant
degradation (Figure 9). While the sampling time errors
may be on the order of femtoseconds, the resulting
limitations in SNR can be significant (see Addendum
Reference 3). Although there are multiple contributors
to overall noise, at high frequencies jitter is clearly the
dominant factor, especially for high resolution converters, as shown in the equation below.
80
HARMONICS (2ND, 3RD)
75
70
65
60
ENCODE = 80MSPS @ AIN = –1dBFS
TEMPERATURE 25C
0
20
40
60
80
100 120 140
ANALOG FREQUENCY (MHz)
160
180
200
Figure 7. Typical Converter Performance vs.
Analog Input Frequency
Since distortion limitations are due at least in part to
slew rate issues, the amplitude of the signal input can be
reduced while keeping the analog frequency constant,
resulting in a reduced slew rate and improved harmonics
and distortion relative to the full scale of the converter.
While these spurs do not always follow the classic trend
of m-order products, this trend may often be weakly observed. As the signal levels are reduced, dynamic effects
diminish, but static effects rapidly replace them as the
dominant contributor to distortion.
SNR


= −20 log


(2πf
analogt jitter
rms
)
2
 2 1+ ε
+   N 
 3 2 
2


 


 2VNoise
+
N
2

2
rms
2
Jitter Equation
Static distortion is distortion due to the transfer function of the converter (Figure 8). This distortion often
has some very unpredictable results. This may include
spurs that change rapidly as a function of input level, and
can exhibit both positive and negative slope characteristics. Largely, these spurs are due to the architecture
characteristics of the converter. Different converters will
have different static transfer functions, resulting in very
different distortion responses. Additionally, since these
are analog components, each part within the same design
will exhibit different responses to an input signal. Therefore, on a part-to-part basis, some variation will exist.
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Figure 9. Typical Converter Performance vs. Jitter
101
There are two sources of jitter. The first is the native or
internal jitter to the device. Since most contemporary
converter designers seek to minimize the internal jitter
by various techniques, this number will usually be the
smaller (but not negligible) of the two types. The second and major source of jitter is the external clock jitter.
When the model is computing the noise due to jitter,
these two jitter sources are combined prior to the noise
being computed.
MISSING
CODE
100
011
010
001
000
ANALOG INPUT
FS
Figure 8. Typical Data Conversion Transfer Function
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REV. A
AN-737
ADIsimADC estimates the instantaneous slew rate of the
input signal and multiplies this by a Gaussian modeled
jitter noise source with a sigma equal to the combined
rms values of the internal and external jitter. The result
is a jitter contribution to the noise that accurately models
the effects of jitter as a function of both the analog input
frequency and amplitude level. The default for external
jitter is that of the setup used during characterization of
the device. However, the user can set this to any value.
flushes. Care must be taken when using the model to
properly account for the pipeline delay either by flushing
the buffer or by other means.
Conclusion
ADIsimADC is a useful tool for simulating ADC performance under specific operating conditions. The software
emulates real world conditions, enabling more complete
system modeling. While it is not a replacement for hardware, it is a good first step to understanding how an ADC
will work in a system design.
Latency
Many types of converters include a delay between the
sample time and when valid data appears on the digital
outputs. SAR and FLASH converters generally provide
output data immediately after the sample period. Multistage converters, such as pipelined and Delta-Sigma
(also known as Sigma-Delta) converters, do not offer
an output for many clock cycles. This is a concern for
control systems and other systems where latency is important. ADIsimADC models latency in terms of whole
values of the clock period. This has the effect of producing garbage at the beginning of a conversion period
while the pipeline fills, as well as producing valid data
after the end of the conversion period while the pipeline
REV. A
Addendum
1. Kester, Walt, ed. Analog-to- Digital Conversion.
Analog Devices, Inc. 2004, ISBN 0-916550-27-3.
2. Brannon, Brad. “DNL and Some of Its Effects on Converter
Performance.” Wireless Design and Development.
June 2001.
3. Brannon, Brad. “Aperture Uncertainty and ADC System
Performance.” Application Note AN-501, Analog
Devices, Inc. www.analog.com.
4. Looney, Mark. “Analog-to-Digital Converter (ADC)
Signal-to-Noise Ratio (SNR) Analysis.” Unpublished.
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© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
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