Download BD95514MUV

Single-chip Type with Built-in FET Switching Regulators
Output 2A or More
High Efficiency Step-down Switching Regulator
with Built-in Power MOSFET
BD95514MUV
No.10027EAT53
●Description
BD95514MUV is a switching regulator capable of supplying high current output (up to 4A) at low output voltages (0.7V~5.0V)
over a broad range of input voltages (4.5V~28V). The regulator features an internal N-MOSFET power transistor for high
3
TM
efficiency and low space consumption, while incorporating ROHM’s proprietary H Reg control mode technology, yielding
the industry’s fastest transient response time against load changes. SLLM (Simple Light Load Mode) technology is also
integrated to improve efficiency when powering lighter loads, as well as soft start, variable frequency, short-circuit protection
with timer latch, over-voltage protection, and REF tracking functions. This regulator is suited for PC applications.
●Features
1) I Internal low ON-resistance power N-MOSFET (typ:120mΩ)
2) I Internal 5V linear voltage regulator (100mA)
3
TM
3) Integrated H Reg DC/DC converter controller
4) Selectable Simple Light Load Mode (SLLM), Quiet Light Load Mode (QLLM) and forced continuous mode
5) Built-in thermal shutdown, low input, current overload, output over- and under-voltage protection circuitry
6) Soft start function to minimize rush current during startup
7) Adjustable switching frequency (f = 200 kHz ~ 1000 kHz:It changes depending on the setup condition.)
8) Built-in output discharge function
9) VQFN032V5050 power package
10) Tracking function
11) Internal bootstrap diode
●Applications
Mobile PCs, desktop PCs, LCD-TV, digital household electronics
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© 2010 ROHM Co., Ltd. All rights reserved.
1/17
2010.10 - Rev.A
Technical Note
BD95514MUV
●Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
Ratings
Unit
VCC
7 *1
V
Input Voltage 2
VDD
7
*1
V
Input Voltage 3
AVIN
30 *1
Input Voltage 4
VIN
30 *1
Input Voltage 1
External VCC Voltage
BOOT Voltage
BOOT-SW Voltage
Output Feedback Voltage
SS/FS/MODE Voltage
VREG Voltage
V
*1
V
BOOT
35
V
BOOT-SW
7 *1
V
FB
VCC
V
SS/FS/MODE
VCC
V
EXTVCC
7
VREG
VCC
V
EN/CTL Input Voltage
EN/CTL
7 *1
V
PGOOD Voltage
PGOOD
7 *1
V
Isw
4 *1
A
Output Current (Average)
Power Dissipation 1
Pd1
*2
W
*3*6
0.38
Power Dissipation 2
Pd2
0.88
W
Power Dissipation 3
Pd3
2.06*4*6
W
Power Dissipation 4
Pd4
*5*6
Operating Temperature Range
Topr
-10～+100
°C
Storage Temperature Range
Tstg
-55～+150
°C
Tjmax
+150
°C
Junction Temperature
4.56
W
*1 Do not exceed Pd.
*2 Ta≧25°C (IC only), power dissipated at 3.0mW / °C.
*3 Ta≧25°C (single-layer board, 20.2 mm2 copper heat dissipation pad), power dissipated at 7.0mW / °C.
*4 Ta≧25°C (4-layer board, 10.29 mm2 copper heat dissipation pad on top layer, 5505 mm2 pad on 2nd and 3rd layer), power dissipated at 16.5mW / °C.
*5 Ta≧25°C (4-layer board, all layers with 5505 mm2 copper heat dissipation pads), power dissipated at 36.5mW / °C.
*6 Values observed with chip backside soldered. When unsoldered, power dissipation is lower.
●Operating Conditions (Ta=25°C)
Parameter
Input Voltage 1
Symbol
VCC
Ratings
Min
Max
4.5
5.5
Unit
V
Input Voltage 2
VDD
4.5
5.5
V
Input Voltage 3
AVIN
4.5
28
V
Input Voltage 4
External VCC Voltage
BOOT Voltage
SW Voltage
VIN
4.5
28
V
EXTVCC
4.5
5.5
V
BOOT
4.5
33
V
SW
-0.7
28
V
BOOT-SW
4.5
5.5
V
MODE Input Voltage
MODE
0
5.5
V
EN/CTL Input Voltage
EN/CTL
0
5.5
V
PGOOD Voltage
PGOOD
0
5.5
V
tonmin
-
100
nsec
BOOT-SW Voltage
Minimum On Time
*This product is not designed for use in a radioactive environment.
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© 2010 ROHM Co., Ltd. All rights reserved.
2/17
2010.10 - Rev.A
Technical Note
BD95514MUV
●Electrical Characteristics
(Unless otherwise noted, Ta=25℃, AVIN=12V, VCC=VDD=VREG, EN/CTL=5V, MODE=0V, RFS=180kΩ)
Limits
Parameter
Symbol
Unit
Condition
MIN
TYP
MAX
[Whole Device block]
AVIN bias current 1
IIN1
-
1300
2000
μA
AVIN bias current 2
IIN2
-
200
300
μA
EXTVCC=5V
AVN standby current
IINstb
-
0
10
μA
CTL=EN＝0V
EN Low voltage
ENlow
GND
-
0.8
V
EN High voltage
ENhigh
2.3
-
5.5
V
EN bias current
IEN
-
12
20
μA
CTL Low voltage
CTLlow
GND
-
0.8
V
CTL High voltage
CTLhigh
2.3
-
5.5
V
CTL bias current
ICTL
-
1
6
μA
VREG output voltage
VREG
4.90
5.00
5.10
V
Maximum current
IREG
200
-
-
mA
EVCC_UVLO
4.2
4.4
4.6
V
REVCC
-
1.0
2.0
Ω
AVIN threshold voltage
AVIN_ UVLO
4.1
4.3
4.5
V
AVIN hysteresis voltage
dAVIN_ UVLO
100
160
220
mV
VREG threshold voltage
VREG_ UVLO
4.1
4.3
4.5
V
VREG hysteresis voltage
dVREG_ UVLO
100
160
220
mV
ton
400
500
600
nsec
MAX ON Time
tonmax
5.0
11.0
22.0
μsec
MIN OFF Time
toffmin
-
450
550
nsec
[5V Linear regulator block ]
AVIN=6.0 to 25V
IREG=0 to 100mA
[5V switch block ]
EXTVCC input threshold voltage
Switch resistance
EXTVCC:Sweep up
[Under Voltage Locked Out block ]
3
TM
[H Reg
VCC:Sweep up
VCC:Sweep down
VREG:Sweep up
VREG:Sweep down
block]
ON Time
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© 2010 ROHM Co., Ltd. All rights reserved.
3/17
2010.10 - Rev.A
Technical Note
BD95514MUV
(Unless otherwise noted, Ta=25℃, AVIN=12V, VCC=VDD=VREG, EN/CTL=5V, MODE=0V, RFS=180kΩ)
Limits
Parameter
Symbol
Unit
Condition
MIN
TYP
MAX
[FET Driver block]
High side ON resistance
Ron_high
-
120
200
mΩ
Low side ON resistance
Ron_low
-
120
200
mΩ
SCP startup voltage
VSCP
0.420
0.490
0.560
V
Delay time
tSCP
0.5
1
2
ms
OVP setting voltage
VOVP
0.800
0.840
0.880
V
Delay time
tOVP
0.5
1
2
ms
Charge current
Iss
1.4
2.2
3.0
μA
Standby voltage
Vss_stb
-
-
100
mV
High side FET output current limit
IHOCP
4.5
6.0
7.5
A
High peak detect
Low side FET output current limit
ILOCP
3.0
4.0
5.0
A
Low peak detect
Feedback pin voltage 1
VFB1
0.693
0.700
0.707
V
Feedback pin voltage 2
VFB2
0.690
0.700
0.710
V
IFB
-100
0
100
nA
SLLM
VthSLLM
VCC-0.5
-
VCC
V
SLLM
(Maximum LG offtime:∞)
Forced continuous mode
VthCONT
GND
-
0.5
V
Continuous mode
QLLM
VthQLLM
2.5
3.0
3.5
V
QLLM
(Maximum LG offtime:40usec)
VMODE
1.5
-
3.0
V
VFB Power Good Low voltage
VFB PL
0.605
0.630
0.655
V
VFB:10%down
VFB Power Good High voltage
VFB PH
0.745
0.770
0.795
V
VFB:10%up
[SCP block]
VFB:30%down
[OVP block]
VFB:20%up
[Soft start block]
[Current Limit block]
[Output Voltage Sense block]
Feedback pin bias current
Ta=-10℃ to 100℃
Iout=0A to 4A
[Mode block]
Open voltage
[Power Good block]
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© 2010 ROHM Co., Ltd. All rights reserved.
4/17
2010.10 - Rev.A
Technical Note
BD95514MUV
●Reference Data
100
100
100
SLLM
SLLM
SLLM
80
80
60
60
40
20
0.1
Io [A]
1
Continuous Mode
40
40
20
20
0
0.01
60
Continuous Mode
η [%]
η [%]
Continuous Mode
η [%]
80
0
0.01
10
0
0.1
Io [A]
1
10
0.01
2μsec/div
Fig.3 Io-Efficiency
(VIN=19V,VOUT=2.5V)
2μsec/div
2μsec/div
VOUT
(50mV/div)
VOUT
(50mV/div)
VOUT
(50mV/div)
SW
(10V/div)
SW
(10V/div)
SW
(10V/div)
IOUT
(2A/div)
IOUT
(2A/div)
IOUT
(2A/div)
Fig.4 Transient Response
(VIN=7V, VOUT=2.5V)
Fig.6 Transient Response
(VIN=19V, VOUT=2.5V)
Fig.5 Transient Response
(VIN=12V, VOUT=2.5V)
2μsec/div
2μsec/div
2μsec/div
VOUT
(50mV/div)
VOUT
(50mV/div)
VOUT
(50mV/div)
SW
(10V/div)
SW
(10V/div)
SW
(10V/div)
IOUT
(2A/div)
IOUT
(2A/div)
Fig.7 Transient Response
(VIN=7V, VOUT=2.5V)
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© 2010 ROHM Co., Ltd. All rights reserved.
1
Io [A]
Fig.2 Io-Efficiency
(VIN=12V,VOUT=2.5V)
Fig.1 Io-Efficiency
(VIN=7V,VOUT=2.5V)
0.1
IOUT
(2A/div)
Fig.8 Transient Response
(VIN=12V, VOUT=2.5V)
5/17
Fig.9 Transient Response
(VIN=19V, VOUT=2.5V)
2010.10 - Rev.A
10
Technical Note
BD95514MUV
●Reference Data
200μsec/div
2msec/div
EN
VOUT
2[V/div]
VOUT
2[V/div]
PGOOD
SW
IL
5[A/div]
PGOOD
Fig.10 PGOOD Rising
Waveform
200μsec/div
VOUT
2[V/div]
EN
Fig.11 PGOOD Falling
Waveform
Fig.12 SCP Timer Latch
Waveform
400μsec/div
EN
VREG
2[V/div]
VOUT
2[V/div]
SW
Fig.13 EN wake up
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© 2010 ROHM Co., Ltd. All rights reserved.
6/17
2010.10 - Rev.A
Technical Note
BD95514MUV
●Block Diagram
VIN
VREG
13
VCC
AVIN
7
SS
16
VDD
EN
10
8
VREG
AVIN
Reference
Block
UVLO
Soft Start
1
SS
CTL
VREF×0.85
VSS×0.85
VOUT
Delay
PGOOD
ILIM
SCP
2
4
OCP
HG
MODE
EN
Power
Good
H3RegTM
Controller
Block
R
26
SW
MODE
Q
28
MODE
S
FB
30
Driver
Circuit
AVIN
14
VREG
31
18
LG
UVLO
ILIM
SCP
TSD
VOUT
29
SS
EXTVCC
VIN(4.5～28V)
VIN
27
17
6
BOOT
3
OVP
REF(0.7V)
VREG
5
REF×1.2
21
VDD
22
FB
OVP
PGND
23
24
Thermal
Protection
25
TSD
32
20
5V Reg
CE
EN/UVLO
MODE
15
11
VREG
9
VOUT
12
MODE
FS
19
GND
●Pin Configuration
PGND PGND PGND
24
23
22
VDD
CE
VOUT
FB
REF
21
20
19
18
17
16 SS
PGND 25
SW 26
15 VREG
SW 27
14 EXTVcc
SW 28
13 VCC
SW 29
12 GND
SW 30
11 FS
SW 31
10 EN
PGND 32
9 MODE
1
2
3
4
VIN
VIN
VIN
VIN
5
6
7
8
BOOT PGOOD AVIN CTL
*Connect the underside (FIN) to the ground terminal
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© 2010 ROHM Co., Ltd. All rights reserved.
7/17
2010.10 - Rev.A
Technical Note
BD95514MUV
●Pin Function Table
PIN No.
PIN Name
PIN Function
1-4
VIN
5
BOOT
6
PGOOD
7
AVIN
Battery voltage sense
8
CTL
Linear regulator on/off (high = 5.0V, low = off)
Battery voltage input (4.5 ~ 28 V)
HG driver power supply
Power good output (high when output ±10% of regulation)
Control mode selection
GND: Continuous Mode
3.0V: QLLM
VCC: SLLM
9
MODE
10
EN
Enable output (high when VOUT ON)
11
FS
Switching frequency adjustment(RFS = 30 k ~ 300 kΩ)
12
GND
Sense ground
13
VCC
Power supply input
14
EXTVCC
15
VREG
16
SS
17
REF
18
FB
19
VOUT
20
CE
Reversing HG output
21
VDD
Power supply input (5 V)
22-25
PGND
26-31
SW
32
PGND
Underside
FIN
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© 2010 ROHM Co., Ltd. All rights reserved.
External power supply input
IC reference voltage (5.0V / 100mA)
Soft start condenser input
Output reference voltage (0.7 V)
Feedback input (0.7 V)
Voltage discharge output
Power ground
Output to inductor
Power ground
Substrate connection
8/17
2010.10 - Rev.A
Technical Note
BD95514MUV
●Pin Descriptions
・VCC
This pin supplies power to the IC’s internal circuitry, excluding the FET driver. The input supply voltage range is 4.5 to 5.5 V.
This pin should be bypassed with either a power capacitor or RC filter.
・EN
Enables or disables the switching regulator. When the voltage on this pin reaches 2.3V or higher, the internal switching
regulator is turned on. At voltages less than 0.8V, the regulator is turned off.
・VDD
This pin supplies power to the low side of the FET driver, as well as to the bootstrap diode. As the diode draws its peak
current when switching on or off, this pin should be bypassed with a capacitance of approximately 1µF.
・VREG
Output pin from the 5V linear regulator. This pin also supplies power to the internal driver and control circuitry.
VREG standby function is controlled by the CTL pin. The output supplies 5V at 100mA and should be bypassed to ground
using a 10 µF capacitor with a rating of X5R or X7R.
・EXTVCC
External power supply input for the linear regulator. When the voltage on the EXTVCC pin exceeds 4.4V, the regulator
uses it in conjunction with other power sources to supply VREG. Connect the EXTVCC pin to GND when not in use.
・REF
Reference voltage output pin. The reference voltage is set internally by the IC to 0.7V, and the IC works to keep VREF
approximately equal to VFB. Variations in voltage levels on this pin affect the output voltage, so the pin should be
bypassed with a 100pF ~ 0.1µF ceramic capacitor.
・SS
Soft start pin. When EN is set high, the capacitor between the internal current source(typ:2.2μA) and SS-GND controls
the startup time of the IC. When the voltage on the SS pin is lower than the REF output voltage (0.7V), the output voltage
is held at the same voltage as the SS pin.
・AVIN
The BD95514MUV controls the duty cycle and output voltage based upon the input voltage at this pin, so voltage
variations or oscillations on this line can cause operation to become unstable. This pin also acts as the voltage input for
the switching block, so insufficient coupling impedance can also cause operation to become unstable. Therefore, this line
should be bypassed with either a power capacitor or RC filter.
・FS
Frequency-adjusting resistance input pin. Attaching a resistance of 30k~300kΩ adjusts the switching frequency from 200
kHz~1MHz (p.11).
・BOOT
This pin serves as the power source for the high side of the FET driver. A bootstrap diode is integrated within the IC.
The maximum voltage on this pin should not exceed +30V vs. GND or +7V vs. SW. When operating the switching
regulator, the operation of the bootstrap circuitry causes the BOOT voltage to swing from (VIN + VDD) ~ VDD.
・PGOOD
Power good indicator. This open-drain output should be connected via a 100kΩ pull-up resistor.
・MODE
Mode selection pin. When low, the IC functions in forced-continuous mode; at voltages from 0V ~ 3V, QLLM mode;
when high, SLLM mode.
・CTL
Linear regulator control pin. When voltage is 2.3V or higher, a logic HIGH is recognized and the internal regulator
(VREG = 5 V) is switched on. At voltages of 0.8V or lower, a logic LOW is recognized and the regulator is switched off.
However, even if EN is logic HIGH, the switching regulator will not operate if CTL is logic LOW.
・FB
Output voltage feedback input. VFB is held at 0.7V by the IC.
・SW
Output from the switching regulator to the inductor. This output swings from VIN ~ GND. The trace from the output to
the inductor should be as short and wide as possible.
・VOUT
Voltage output discharge pin. When EN is off, this output is pulled low.
・VIN
Power supply input. The IC can accept any input from 4.5V to 28V. This pin should be bypassed directly to ground by a
power capacitor.
・PGND
Power ground terminal.
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© 2010 ROHM Co., Ltd. All rights reserved.
9/17
2010.10 - Rev.A
Technical Note
BD95514MUV
●Operation
3
TM
CONTROLLA control system.
The BD95514MUV is a switching regulator incorporating ROHM’s proprietary H Reg
When VOUT drops suddenly due to changes in load, the system quickly restores the output voltage by extending the ton time
interval. This improves the regulator’s transient response. When light-load mode is activated, the IC employs the Simple
Light Load Mode (SLLM) controller, further improving system efficiency.
3
TM
H Reg Control
(Normal Operation)
VFB
When VFB falls below the reference voltage (0.7V),
3
TM
the H Reg CONTROLLA is activated;
VREF
tON
HG
VREF
VIN
×
1
[sec]・・・(1)
f
High gate output is determined by the above formula.
LG
(Rapid Changes in Load)
When VOUT drops due to a sudden change in load and the
voltage remains below VREF after the preprogrammed
tON time interval has elapsed, the system quickly restores
VOUT by extending the tON time, thereby improving transient
response.
VFB
VREF
Io
tON+α
HG
LG
Light Load Control
(SLLM Mode)
VFB
SLLM mode is enabled by setting the MODE pin to logic
high. When the low gate is off and the current through the
inductor is 0 (current flowing from VOUT to SW), the SLLM
function is activated, disabling high gate output.
If VFB falls below VREF again, the high gate is switched back
on, lowering the switching frequency of the regulator and
yielding higher efficiency when powering light loads.
VREF
HG
LG
0A
(QLLM Mode)
QLLM mode is enabled by setting the MODE pin to HiZ or
middle voltage. When the lower gate is off and the current
through the inductor is 0 (current flowing from VOUT to
SW), QLLM mode is activated, disabling high gate output.
If VFB falls below VREF within a programmed time interval
(typ. 40µs), the high gate is switched on, but if VFB does
not fall below VREF, the lower gate is forced on, dropping
VFB and switching the high gate back on.
The minimum switching frequency is set to 25 kHz (T=40
µS), which keeps the regulator’s frequency from entering
the audible spectrum but yields less efficient results than
SLLM mode.
VFB
VREF
HG
LG
0A
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© 2010 ROHM Co., Ltd. All rights reserved.
10/17
2010.10 - Rev.A
Technical Note
BD95514MUV
●Timing Chart
・Soft Start Function
The soft start function is enabled when the EN pin is set
high. Current control circuitry takes effect at startup,
yielding a moderate “ramping start” in output voltage.
Soft start timing and incoming current are given by equation
(2) and (3) below:
EN
tSS
SS
Soft start period:
VOUT
tSS =
VREF×Css
[sec] ・・・(2)
2.2μA(typ)
Rush current:
IIN
IIN(ON)=
Co×VOUT
tss
[A] ・・・(3)
(Css: soft start capacitor;
Co: All capacitors connected with VOUT)
・Timer Latch-type Short Circuit Protection
VREF×0.70
When output voltage falls to VREF x 0.70 or less, the output
short circuit protection engages, turning the IC off after a set
period of time to prevent internal damage. When EN is
switched back on or when UVLO is cleared, output
continues. The time period before shutting off is set
internally at 1 ms.
VOUT
1ms
SCP
EN/UVLO
・Output Over-Voltage Protection
VREF×1.2
VOUT
When output reaches or exceeds VREF x 1.2, the output
over-voltage protection is engaged, turning the low-side
FET completely on to reduce the output (low gate on, high
gate off). When the output falls, it returns to standard
mode.
HG
LG
Switching
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© 2010 ROHM Co., Ltd. All rights reserved.
11/17
2010.10 - Rev.A
Technical Note
BD95514MUV
●External Component Selection
1. Inductor (L) Selection
The inductor’s value directly influences the output ripple current.
As formula (4) indicates below, the greater the inductance or
switching frequency, the lower the ripple current:
(VIN-VOUT)×VOUT
[A]・・・(4)
ΔIL=
L×VIN×f
ΔIL
VIN
The proper output ripple current setting is about 30% of maximum output
current.
IL
ΔIL=0.3×IOUTmax. [A]・・・(5)
VOUT
L
L=
Co
(VIN-VOUT)×VOUT
ΔIL×VIN×f
[H]・・・(6)
(ΔIL: output ripple current, f: switching frequency)
Output ripple current
※Passing a current larger than the inductor’s rated current will cause magnetic saturation in the inductor and decrease
system efficiency. In selecting the inductor, be sure to allow enough margin to assure that peak current does not
exceed the inductor’s rated current value.
※To minimize possible inductor damage and maximize efficiency, choose an inductor with a low DCR and ACR resistance.
2. Output Capacitor Selection (CO)
VIN
When determining the proper output capacitor, be sure to factor in the equivalent
series resistance (ESR) and equivalent series inductance (ESL) required to set the
output ripple voltage at 20 mV or more.
VOUT
L
ESR
When selecting the limit of the inductor, be sure to allow enough margin for the
output voltage. Output ripple voltage is determined by formula (7) below:
ESL
Co
ΔVOUT=ΔIL×ESR+ESL×ΔIL / TON・・・(7)
Output Capacitor
(ΔIL: Ouput ripple current, ESR: equivalent series resistance,
ESL: equivalent series inductance)
Give special consideration to the conditions of formula (7) for output capacitance. Also, keep in mind that the output rise
time must be established within the soft start timeframe.
Co≦
tss×(Ilimit-IOUT)
VOUT
・・・(8)
tss: Soft start timeframe (see p. 10, equation (2))
Ilimit: Maximum output current
Choosing a capacitance that is too large can cause startup malfunctions, or in some cases, may engage the short circuit
protection.
3. Input Capacitor Selection (CIN)
In order to prevent extreme over-current conditions, the input capacitor must have
a low enough ESR to fully support a large ripple in the output.
The formula for RMS ripple current (IRMS) is given by equation (9) below:
VIN
CIN
VOUT
L
IRMS=IOUT×
√VIN(VIN-VOUT)
[A]・・・(9)
VIN
Co
When VIN=2×VOUT, IRMS=
IOUT
2
Input Capacitor
A low-ESR capacitor is recommended to reduce ESR loss and maximize efficiency.
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12/17
2010.10 - Rev.A
Technical Note
BD95514MUV
4. Frequency Adjustment
The resistance connected to the FS terminal adjusts the
on-time (tON) during normal operation as illustrated to the
left. When tON, input voltage and VREF voltage are
known, the switching frequency can be determined by the
following formula:
VREF
F=
・・・(10)
VIN×tON
500
From top:VIN=
450
400
5V
7V
12V
19V
25V
Frequency [kHz]
350
300
250
However, real-life considerations (such as external
MOSFET gate capacitance and switching time) must be
factored in as they affect the overall switching rise and fall
time. This leads to an increase in tON, lowering the total
frequency slightly.
200
150
100
50
Additionally, when output current lingers around 0A in
continuous mode, this “dead time” also has an effect
upon tON, further lowering the switching frequency.
Confirm the switching frequency by measuring the
current through the coil (at the point where current does
not flow backwards) during normal operation.
0
50
100
150
200
250
300
RFS[kΩ]
The BD95514MUV operates by feeding the output voltage back through a resistive voltage divider.
The output voltage is set by the following equation (see schematic below):
Output Voltage =
R1+R2
R2
×
VREF (0.7V) +
1
2
×ΔIL×ESR・・・(11)
The switching frequency is also amplified by the same resistive voltage divider network:
fsw
=
R1+R2
×
(frequency set by RFS) [Hz]・・・(12)
R2
VIN
REF(0.7V)
H3RegTM
CONTROLLA
VIN
R
Q
SLLM
TM
Output Voltage
Driver
S
SLLM
FB
ESR
Circuit
R1
R2
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© 2010 ROHM Co., Ltd. All rights reserved.
13/17
2010.10 - Rev.A
Technical Note
BD95514MUV
●Evaluation Board Circuit (Frequency=300kHz Continuous Mode/QLLM/SLLM Example Circuit)
SW
VOUT
L1
VOUT
D1
C14
GND_VIN
VIN
R4
PGND
SW
SW
SW
SW
SW
C8
SW
PGND
VIN
C9
VIN
PGND
C10
VIN
PGND
C11
VIN
PGND
VIN
VDD
GND_VOUT
R22
VDD
GND_VDD
R9
BOOT
C13
CE
R7
C12
PGOOD
PGOOD
VOUT
AVIN
FB
REF
SS
VREG
EXTVCC
VCC
GND
D
FS
C7
VDD
EN
REF
CTL
MODE
SW1
R8
CTL
SW3
C6
VDD
C19
VDD
MODE
R6
R5
VDD
C1
C2
R2 C4 C5
EN
SW2
R17
SS
GND
R1
VCC
PGND
VREG R18
GND
VCC
EXTVCC
●Evaluation Board Parts List
Designation
Rating
PART No.
Company
Designation
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R22
C01
C02
10Ω
0Ω
10Ω
10KΩ
270KΩ
10kΩ
3.07kΩ
100KΩ
0Ω
0Ω
0Ω
0Ω
510kΩ
1μF
-
MCR03
MCR03
MCR03
MCR03
MCR03
MCR03
MCR03
MCR03
MCR03
MCR03
MCR03
MCR03
MCR03
ceramic capacitor
-
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
-
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
D1
D
L1
U1
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© 2010 ROHM Co., Ltd. All rights reserved.
14/17
Rating
PART No.
Company
1μF
ceramic capacitor
1μF
ceramic capacitor
3300pF
ceramic capacitor
0.1μF
ceramic capacitor
0.1μF
ceramic capacitor
22μF
ceramic capacitor
0.1μF
ceramic capacitor
1000pF
ceramic capacitor
220μF
4TPE220MF
470pF
ceramic capacitor
RSX501L-20
TDZ5.1
3.2μH CDEP105-3R2MC-50
BD95514MUV
SANYO
ROHM
ROHM
Sumida
ROHM
2010.10 - Rev.A
Technical Note
BD95514MUV
●Notes for use
(1) Absolute maximum ratings
Exceeding the absolute maximum ratings (such as supply voltage, temperature range, etc.) may result in damage to the
device. In such cases, it may be impossible to identify problems such as open circuits or short circuits.
If any operational values are expected to exceed the maximum ratings for the device, consider adding protective
circuitry (such as fuses) to eliminate the risk of damaging the IC.
(2) Power supply polarity
Connecting the power supply in reverse polarity can cause damage to the IC.
Take precautions when connecting the power supply lines. An external power diode can be added.
(3) Power supply lines
The PCB layout pattern should be designed to provide the IC with low-impedance GND and supply lines. To minimize
noise on the supply and GND lines, ground and power supply lines of analog and digital blocks should be separated.
For all power lines supplying ICs, connect a bypass capacitor between the power supply and the GND terminal.
If using electrolytic capacitors, keep in mind that their capacitance is reduced at lower temperatures.
(4) GND voltage
The potential of the GND pin must be the minimum potential in the system in all operating conditions.
(5) Thermal design
Use thermal design techniques that allow for a sufficient margin for power dissipation in actual operating conditions.
(6) Inter-pin shorts and mounting errors
Use caution when positioning he IC for mounting on PCBs.
or if pins are shorted together.
The IC may be damaged if there are any connection errors
(7) Operation in strong electromagnetic fields
Exercise caution when using the IC in the presence of strong electromagnetic fields as doing so may cause the IC to
malfunction.
(8) ASO
When using the IC, set the output transistor so that it does not exceed either absolute maximum ratings or ASO.
(9) Thermal shutdown circuit
The IC incorporates a built-in thermal shutdown circuit (TSD circuit), which is designed to shut down the IC only to
prevent thermal overloading. It is not designed to protect the IC or guarantee its operation. Do not continue to use
the IC if this circuit is activated, or in environments in which activation of this circuitry can be assumed.
BD95514MUV
TSD ON Temp. [°C] (typ.)
Hysteresis Temp. [°C] (typ.)
175
15
(10) Testing on application boards
When testing the IC with application boards, connecting capacitors directly to low-impedance terminals can subject the
IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should be
turned off completely before connecting it to or removing it from a jig or fixture during the evaluation process.
To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport
and storage.
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© 2010 ROHM Co., Ltd. All rights reserved.
15/17
2010.10 - Rev.A
Technical Note
BD95514MUV
(11) Regarding IC input pins
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating
parasitic diodes and/or transistors. For example (refer to the figure below):
・When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode
・When GND > Pin B, the PN junction operates as a parasitic transistor
Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in
mutual interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these
diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate)
should be avoided.
Resistance
Transistor (NPN)
Pin A
Pin B
C
B
Pin B
E
Pin A
N
N
N
P+
P
P+
P+
B
B
N
N
P Substrate
Parasitic Element
P+
P
C
E
N
P Substrate
Parasitic Element
GND
Parasitic Elements
GND
Parasitic Elements
GND
GND
Other Adjacent Elements
Example of IC Structure
(12) Ground wiring traces
When using both small-signal and large-current GND traces, the two ground traces should be routed separately but
connected to a single ground potential within the application in order to avoid variations in the small-signal ground
caused by large currents. Also ensure that the GND traces of external components do not cause variations on GND
voltage.
●Power Dissipation
5.5
①
5.0
IC Only
④4.56W
Power Dissipation : Pd (W)
4.5
θj-a = 328.9 °C/W
4.0
②
3.5
θj-a = 142.0 °C/W
3.0
③
2.5
③2.06W
④
1.5
0.5
2
IC mounted on 4-layer board (with 20.2 mm pad on top layer,
2
5502 mm pad on layers 2,3)
θj-a = 60.7 °C/W
2.0
1.0
2
IC mounted on 1-layer board (with 20.2 mm copper thermal pad)
2
IC mounted on 4-layer board (with 5505mm pad on all layers)
②0.88W
①0.38W
0.0
0
25
50
75
100
125
150
Ambient Temperature: Ta(℃)
VQFN032V5050
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© 2010 ROHM Co., Ltd. All rights reserved.
16/17
2010.10 - Rev.A
Datasheet
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
, transport
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
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Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
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(Note1) Medical Equipment Classification of the Specific Applications
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CLASSⅢ
CLASSⅡb
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4.
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5.
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6.
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7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
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8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
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Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice - GE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
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This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
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[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
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3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
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Notice - GE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
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Notice – WE
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Rev.001