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Analysis of timing resolution of a digital silicon photomultiplier. Shingo Mandai† and Edoardo Charbon I. A BSTRACT This paper presents the analysis of timing resolution for a digital silicon photomultiplier (D-SiPM) using a SPICE simulator. A D-SiPM has more than a hundred of pico seconds timing resolution for single-photon detection due to detector jitter, circuit noise and routing skew. Especially, circuit noise and skew depend on the SiPM design strongly. To investigate how single-photon timing resolution is related to architectural choices and design parameters, we have simulated the timing resolution by sweeping the design parameters: the transistor size and the transistor channel length, wire resistance and capacitance. We considered D-SiPMs of different sizes and with a variety of signal distribution architectures. II. I NTRODUCTION Silicon photomultipliers (SiPMs) are an alternative to photomultiplier tubes (PMTs) because of their robustness to magnetic fields, compactness, and low bias voltage [1]. An analog SiPM (A-SiPM) consists of an array of avalanche photodiodes operating in Geiger mode (single-photon avalanche diodes, SPADs), whose avalanche currents are summed in one node, and the output will be processed with off-chip components as shown in Fig. 1 (a) [1]. In digital SiPMs (D-SiPMs) on the contrary, all of the SPAD outputs are combined together by means of a digital OR, and the output is directly routed to an on-chip time-to-digital converter (TDC) to reduce external components and temporal noise as shown in Fig. 1 (b) [2], [3]. Timing resolution for single-photon detection is limited by SPAD jitter and circuit noise, as well as systematic skew due to imperfectly balanced routing. This paper investigates how single-photon timing resolution is related to architectural choices and design parameters. Design parameters include the transistor size and the transistor channel length, wire resistance and capacitance, assuming that the D-SiPM is implemented in 0.35 µm standard CMOS process with spatial random process variations for the transistor channel length and wire resistance and capacitance [4]. We considered D-SiPMs of different sizes and with a variety of signal distribution architectures. III. S KEW When photons hit a SiPM, the first photon can arrive at any SPAD spatially at random. Thus the timing resolution degrades due to routing skew. H-tree is a well known topology Shingo Mandai and Edoardo Charbon are with TU Delft, The Netherlands († [email protected]) The research leading to these results has received funding from the European Union Seventh Framework Program under Grant Agreement n◦ 256984 (EndoTOFPET-US). for a clock signal to minimize the skew, and it is applicable to a D-SiPM with an OR gate in each junction. As shown in Fig. 2 (a), H-tree is implemented from each SPAD to the timing output via a buffer and 2-input OR gates. We assume that the SPAD pitch and unit wire length is 50 µm and 25 µm, respectively, the number of SPADs is 64 × 64. In Htree design, determination of the maximum transition time is important for skew control, area and power dissipation [5]. We use a parameter λ = Cout /Cin to control the transition time, where Cin is the input capacitance of the OR gate and Cout is its output load capacitance to drive the next stage including the input capacitance of the next OR gate [6]. λ at N th junction is defined using the unit wire capacitance, Cw , as, λ = Cout /Cin = (Cw × 2N/2 + Cin(N +1) )/Cin(N ) . (1) The output of the H-tree is connected to a unit size OR gate to minimize the input capacitance, so Cin(13) is a known value. Therefore, all Cin will be calculated successively. Fig. 3 and Fig. 4 show the propagation delay and skew for each λ varying Cw from 7 fF to 2 fF, and the unit wire resistance, Rw , from 3.5 ohm to 1 ohm, respectively, assuming that each transistor channel length (Ltr ), unit wire capacitance, and unit wire resistance has 5 % sigma process variation. Both the propagation delay and the skew improve dramatically by changing λ from 7 to 2 while the transistor area occupies 4.5 times larger. One future option could be designing the D-SiPM using an advanced CMOS process, such as 180 nm, 130 nm or 90 nm, not to have big impact on the D-SiPM fill factor. Note that that Cw has more effect on the skew than Rw in the case of D-SiPMs, while Rw is very important for A-SiPMs [7]. The process variation for Ltr , Cw and Rw were set to vary from 5 % to 1% to see the dominant factor for the skew as shown in Fig. 5, thus demonstrating that Ltr has the highest impact on the skew. IV. T EMPORAL NOISE The temporal noise of the D-SiPM is composed of SPAD jitter, σspad , and the noise by the timing signal routing, σroute , including transistor induced noise and kTC noise [8]. The temporal noise model is shown in Fig. 6 (a). Assuming that all these sources of noise are wide-sense stationary, statistically independent random processes with gaussian distribution, the total standard deviation of the resulting process is computed as, 2 2 2 σjitter = σspad + σroute . (2) Fig. 6 (b) shows simulation results of the noise by routing, σroute , and the total temporal noise, σspad+route , assuming that the SPAD jitter is 42.6 ps sigma [3]. It is observed that the SPAD jitter is dominant for the temporal jitter. V. T IMING RESOLUTION OF D-S I PM S Under the same assumption of before, the timing uncertainty of D-SiPMs is calculated as, 2 2 2 σsipm = τskew + σjitter . (3) Fig. 7 (a) shows the timing resolution of the D-SiPM for a range of λ derived from τskew and σjitter at 5 % process variation. The timing resolution improves by utilizing small λ because the skew improves. Fig. 7 (b) shows that the timing resolution improves by reducing the transistor channel length variation and approaches to the SPAD jitter. We have also investigated the timing resolution dependency on the size of the D-SiPM. Fig. 8 (a) shows the timing resolution as a function of array size and λ. By reducing the size of the DSiPM, the D-SiPM will be less sensitive to process variations because the skew becomes small. Therefore, to achieve good timing resolution, the D-SiPM should be divided into small groups of SPADs, and connected to TDCs in another die with short 3-D vias, as shown in Fig. 8 (b), as well as optimizing the value of λ and designing transistors carefully not to have any geometrical asymmetry thus introducing Ltr variations. VI. C ONCLUSION We have presented the analysis of timing resolution for a D-SiPM using a SPICE simulator. Generally, a D-SiPM has more than a hundred of picoseconds timing resolution for single-photon detection due to detector jitter, circuit noise and routing skew. We found that SPAD jitter and skew have a strong impact on the timing resolution of the D-SiPM, though the timing resolution can be improved by choosing a proper architecture or modifying the design parameters: i.e. transistor width and length, wire resistance and capacitance, and their process variations. R EFERENCES [1] MPPC, http://jp.hamamatsu.com. [2] T. Frach, G. Prescher, C. Degenhardt, R. Gruyter, A. Schmitz, and R. Ballizany, “The digital silicon photomultiplier principle of operation and intrinsic detector performance,” in Proc. IEEE Nuclear Science Symp. Conf., 2009, pp. 1959–1965. [3] S. Mandai and E. Charbon, “Multi-channel digital SiPMs: Concept, analysis and implementation,” in Proc. IEEE Nuclear Science Symp. Conf., 2012. [4] S. Nassif, “Within-chip variability analysis,” in Proc. IEDM, 1998, pp. 283–286. [5] A. Chandrakasan, W. J. Bowhill, and F. Fox, “Design of high- performance microprocessor circuits,” in IEEE press, 2001. [6] M. Hashimoto, T. Yamamoto, and H. Onodera, “Statistical analysis of clock skew variation in H-tree structure,” in Proc. ISQED, 2005, pp. 402–407. [7] T. Nagano, K. Sato, A. Ishida, T. Baba, R. Tsuchiya, and K. Yamamoto, “Timing resolution improvement of MPPC for TOF-PET imaging,” in Proc. IEEE Nuclear Science Symp. Conf., 2012. [8] A. A. Abidi, “Phase noise and jitter in cmos ring oscillators,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1803–1816, Aug. 2006. 60p 60p All variations (Ltr, Cw, Rw) 50p in t2 Buffer v 1 Buffer v 2 t1 t2 4% 30p 3% 10p OR Only Ltr variation 0 TDC or TAC t = min { t1, t2, ... , tn } TDC 40p 30p 20p 2% tn Preamplifier 3 2 4 λ 5 10p 1% 6 0 7 2 3 4 (a) 60p λ Only Cw variation 5% 4% 3% 2% 1% 5 6 7 (b) t = min { t1, t2, ... , tn } Same die (a) Fig. 1. Buffer v 3 40p All variations (Ltr, Cw, Rw) 50p 5% SPAD 20p tn I = i1 + i2 + ... + in Same die SPAD Skew (s) i2 t1 SPAD SPAD Skew (s) i1 SPAD 50p (b) The concept of (a) an Analog SiPM and (b) a Digital SiPM. Skew (s) SPAD All variations (Ltr, Cw, Rw) 40p 30p 20p 1%-5% 10p 3 SPAD pitch 50μm 4 5 6 0 AN 8 3 2 4 1st 2nd 2N/2th Unit wire 25μm 7 Only Rw variation λ 5 6 7 (c) Cin(N) Rw BN Fig. 5. Skew dependency on (a) Ltr , (b) Cw and (c) Rw . For a broken line, the situation that Ltr , Cw and Rw has 5% sigma process variation at the same time is considered as a refence. Cin(N+1) Cw 2-input OR SPADs Buffer Unit wire Nth OR OR Wire 40p (N+1)th OR (c) Fig. 2. (a) H-tree for timing signals. (b) Model for the route from Nth junction to (N+1)th junction. SPAD jitter Transistor noise OR (b) OR Wire Timing output Temporal noise (s) 1 2 20p σroute 10p Thermal noise (σspad) σspad+route 30p 0 (σroute) 2 3 4 (a) 6 7 2.5n Fig. 6. (a) Temporal noise sources in the D-SiPM. (b) Temporal noise in the D-SiPM in various values of λ. 7f 6f 5f 4f 3f 2f 50p 45p 100p 40p 2.0n 35p 3 4 λ 5 6 30p 7 2 3 4 (a) λ 5 6 7 (b) Fig. 3. (a) Propagation delay and (b) skew in various λ values with different values of Cw . 100p 80p σsipm 60p 50p τskew 40p σjitter 30p 20p 2 3 4 λ 5 6 7 Timing resolution for a single photon (s) 3.0n Unit wire capacitance, Cw (F) 55p Timing resolution for a single photon (s) 3.5n 7f 6f 5f 4f 3f 2f Skew (s) Propagation delay (s) Unit wire capacitance, Cw (F) Ltr variation 80p 5% 60p 4% 50p 3% 2% 1% σspad 40p 30p 20p 2 3 4 (a) Unit wire resisitance, Rw (Ω) Unit wire resisitance, Rw (Ω) Skew (s) 3.0n 2.5n 50p 3.5 3 2.5 2 1.5 1 45p 40p 2.0n 35p 1.5n 2 30p 3 4 λ (a) 5 6 5 6 7 55p 3.5 3 2.5 2 1.5 1 7 2 3 4 λ 5 6 7 (b) Fig. 4. (a) Propagation delay and (b) skew in various λ with different values of Rw . Rw was found to have negligible effect on propagation delays and skews. Timing resolution for a single photon (s) 3.5n λ (b) Fig. 7. (a) Timing resolution of a D-SiPM for single-photon detection. (b) Timing resolution with different values of relative Ltr variations. 60p 4.0n Propagation delay (s) 5 60p 4.0n 1.5n 2 λ (b) SPAD + electronics 80p λ=7 λ=6 70p Routing per cluster 3D via λ=5 SiPM Chip λ=4 60p λ=3 50p λ=2 30p 4x4 SPAD cluster 3D via per cluster 40p 8x8 32x32 16x16 Size of SiPM (a) 64x64 TDC Chip TDC per cluster (b) Fig. 8. (a) Timing resolution of the D-SiPM for a single-photon in different sizes of array for the D-SiPM. (b) Ideal configuration of a D-SiPM.