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Name of University - Class Title Introduction To Embedded System Design Embedded Systems Architecture : A Comprehensive Guide for Engineers and Programmers - An Elsevier Science Publication Name of University - Class Title Overview What is an Embedded System? Embedded Systems Design – Embedded Systems Design & Development Lifecycle Model What is an Embedded Systems Architecture? – The 6 Stages of Creating an Embedded Architecture. Stage 1 : Have a Strong Foundation – Know Your Standards – Embedded Software Putting It All Together – Stages 2-6 of Creating an Architecture Name of University - Class Title What Is An Embedded System ? A type of computer system. Some of the Most Common Traditional Definitions : – Embedded systems are more limited in hardware and/or software functionality then the PC. – An embedded system is designed to perform a dedicated function –… Why don’t these definitions entirely apply, today? Name of University - Class Title What is an Embedded System [Continued]? Automotive – Consumer Electronics – i.e. : Infusion Pumps, Dialysis Machines, Prosthetic Devices,Cardiac Monitors, … Networking – i.e. : robotics, control systems… Medical – i.e. : TVs, STBs, appliances, toys, automobiles, cell phones … Industrial Control – i.e. : Ignition Systems, Engine Control, Antilock Braking System, … i.e. : routers, hubs, gateways, … Office Automation – i.e. : fax machines, photocopiers, printers, monitors, … ** Aside from being types of computer systems, there is no single definition or characterization of embedded systems reflecting them all. ** Name of University - Class Title Embedded Systems Design Phase 1 : Creating The Architecture Product Concept Phase 2 : Implementing the Architecture Preliminary Requirements Analysis Creation of Architecture Design Phase 3 : Testing the System Phase 4 : Maintaining the System Develop Version of Architecture Deliver Final Version of Architecture Incorporate Feedback Develop [Implement] the System Incorporate Feedback Deliver Version of Architecture Review & Obtain Feedback Review and Test the System Embedded Systems Design and Development Lifecycle Model Deliver & Maintain the System Name of University - Class Title What is Embedded Systems Architecture? • An abstraction of the embedded device that represents the embedded system as some combination of interacting elements. - physically represented as structures - many types of structures • Layered, Kernel, Decomposition, Client/Server, Process, … Sum of Structures = Embedded Architecture • Why care about the architecture of an embedded system? Name of University - Class Title 6 Stages of Creating an Embedded Architecture Many industry popular methodologies for creating architectures (adaptable to embedded systems) – Rational Unified Process (RUP), Attribute Driven Design (ADD), Object Oriented Process (OOP), … More Pragmatic Approach [the best of all worlds] – – – – – – Stage 1 : Having a Solid Technical Base Stage 2 : Understanding the ABCs of Embedded Systems Stage 3 : Defining the Architectural Patterns & Reference Models Stage 4 : Creating the Architectural Structures Stage 5 : Documenting the Architecture Stage 6 : Analyzing & Evaluating the Architecture Stanford University - EE109 Stage 1 : Having a Strong Technical Base Name of University - Class Title Embedded Systems Model Application Layer System Software Layer Hardware Layer Embedded System Name of University - Class Title EE109 Platform and the Embedded Systems Model Camera Application User Interface USB Drivers Interrupt Drivers ... Application Layer ... Memory Management Drivers System Layer Cypress EZ-USB FX-2 Xilinix FPGA 16 MB DRAM .... Hardware Name of University - Class Title Know Your Standards General Purpose Standards PJava J2ME SSL128 … Ethernet TCP/IP HTTP … Market Specific Standards MHP ATSC DTV HAVi FDA … Application Software Layer System Software Layer Hardware Layer Market Specific – Consumer Electronics, Medical, Industrial Automation & Control, Networking & Communications, Automotive, Aerospace & Defense, Office Automation, … General Purpose – Networking, Programming Language, Security, Quality Assurance, … Name of University - Class Title How can a Programming Language Spec Add to An Embedded System’s Architecture ? Target [Embedded System] Host [Development System] Application Layer Application Layer Preprocessor Compiler Linker … System Software Layer System Software Layer Hardware Layer Hardware Layer Translating Code – Interpretation, Just-in-Time (JIT), Way-Ahead-of-Time (WAT)/Ahead-of-Time (AOT) Garbage Collection – Copying, Mark&Sweep, Generational, … Name of University - Class Title Translation of Code on Host : Compiling C Source File (s) C Compiler Preprocessing C Header File (s) Compiling C Object File (s) Linker C Executable File Embedded System C System Libraries Host Computer Name of University Translation of Code on Target - Class Title Byte Code 1 Parsing Interpretation vtab Target Code for Source L1 Byte Code 1 Interpreting Byte Code 1 Byte Code 2 Source L1 Source File (s) Byte Code 2 Parsing Source L3 Byte Code 3 Byte Code 2 Interpreting Interpretation Target Code for Source L2 Source L2 Host Compiler Target Code for Source L3 Source L4 Source L5 …. Byte Code File (s) … Byte Code 1 Parsing & Interpreting Just-In-Time [JIT] Byte Code 2 Parsing & Interpreting Byte Code 2 JIT Compiling Byte Code 1 .class File Compiled Byte Code 1 JVM WAT Compiler Byte Code 1 object File Byte Code 2 Compiled Byte Code 2 Byte Code 2 Byte Code 3 Compiled Byte Code 3 Byte Code 3 2 JVM Linker Runtime Libraries …. … …. executables … First Pass of Processing Byte Code Way-Ahead-ofTime/Ahead-Of-Time [WAT/AOT] 1 vtab Byte Code 1 JIT Compiling …………. Source L6 2nd and Additional Passes of Processing Byte Code Name of University - Class Title Garbage Collection : Copying Memory Before GC Memory After GC Copying Garbage Collector Object 1 Object 1 Object 2 Object 2 Object 3 Object 4 Object 4 Name of University - Class Title Garbage Collection : Mark&Sweep Memory Before GC Object 1 Memory After GC Mark & Sweep Garbage Collector Object 1 Object 2 Object 2 [Mark] Object 3 [Sweep] Object 4 Object 4 Name of University - Class Title Garbage Collection : Generational Youngest Generation [Nursery] Older Generation Memory Before GC Mark,Sweep, & Compact Garbage Collector Copying Garbage Collector Memory Before GC Memory After GC Memory After GC Mark & Sweep Object 1 Object 1 Object 1 Object 1 Object 2 [Mark] Object 2 Object 2 Object 2 Object 3 [Sweep] Object 4 Object 3 Object 4 Object 4 Object 4 Copying GC Memory After GC Compaction Object 1 Object 2 Object 4 Mark (Sweep) & Compact GC [Compact] Name of University - Class Title How can Java Add to An Embedded System’s Architecture ? Embedded Java – – – Standards (pJava, J2ME, Embedded Java, …) Processing Bytecode (Interpretation, JIT, WAT/AOT) Garbage Collection (Copying, Mark&Sweep, …) Application Layer Application Layer Java Device Drivers Application Layer JVM JVM System Software Layer System Software Layer Java Processor System Software Layer Hardware Layer Hardware Layer Hardware Layer JVM compiled in application i.e. Esmertec’s Jbed, Kava’s KavaVM, IBM’s J9 … JVM part of System layer i.e. : Skelmir’s Cee-J, Esmertec/Insignia’s Jeode and Jbed, Tao’s Intent, Kava’s KavaVM … JVM in Hardware i.e. : ARM’s Gazzelle, AJile’s aj100,… Name of University - Class Title How can .NetCE Add to An Embedded System’s Architecture ? .NetCE Compact Framework – – – Standard = Common Language Specification Processing Bytecode (Interpretation/JIT) Garbage Collection ( Generational) MSIL Application .NET Compact Framework Application Layer BCL/Platform Extension Libraries Class Loader GC CLR [JIT] Execution Engine System Software Layer Memory Hardware Layer Name of University - Class Title How can Scripting Languages Add to An Embedded System’s Architecture ? Scripting Languages – – Perl, JavaScript, HTML, … Processing Bytecode (Interpretation) Application Software Layer Browser SSL 128 Bit Encryption Java Script HTTP HTML4.0 System Software Layer Hardware Layer Real Audio DOM 0 CSS 1 … Name of University - Class Title How can Networking Add to an Embedded System’s Architecture ? Transmission Medium Device C Server Client C Networking Components Networking Components Networking Components Device A Client A Networking Components Networking Components Distance Device B Client B Networking Components Networking Components Network 1 – Peer-to-Peer Architecture Network 2 – Client/Server Architecture Network ‘s Overall Structure Name of University - Class Title Open Systems Interconnection (OSI) Model OSI Model Application Layer Presentation Layer Application Software Layer Session Layer Transport Layer Network Layer Data-Link Layer Physical Layer System Software Layer Hardware Layer Name of University - Class Title Networking Layers Layer 7 Application Layer Application Layer Presentation Layer Layer 7 Header 1 Presentation Layer Header 2 Header 3 Session Layer Data Data Session Layer Header 4 Data Application Data Presentation Session Transport Data Network Header 5 Transport Layer Data Data Link Transport Layer Data Physical Layer 1 Network Layer Network Layer Data Link Layer Data Link Layer Physical Layer Physical Layer Transmission Medium Layer 1 Name of University - Class Title OSI and Real-World Networking Models : TCP/IP TCP/IP Model OSI Model Application Layer Application Layer Application Software Layer Presentation Layer Session Layer Transport Layer Internet Layer Transport Layer System Software Layer Network Layer Data-Link Layer Network Access Layer Physical Layer Hardware Layer Name of University - Class Title OSI and Real-World Networking Models : WAP OSI Model WAP Model Application Layer Application Layer Session Layer Presentation Layer Transaction Layer Session Layer Security Layer Application Software Layer Transport Layer Transport Layer System Software Layer Network Layer Data-Link Layer Physical Layer Hardware Layer Name of University - Class Title OSI and Real-World Networking Models : Bluetooth Bluetooth Model OSI Model Application Layer Application Software Layer Application Protocol Group Presentation Layer WAP Session Layer Middleware Protocol Group TCP/IP Transport Layer System Software Layer Network Layer Data-Link Layer Transport Protocol Group Physical Layer Hardware Layer Name of University - Class Title OSI Layer 1 : Physical Layer Application Software Layer System Software Layer Hardware Layer LAN Wireless WAN Wired IEEE802.11 Wireless Radio & IR Wireless Wired IEEE 802.3 Ethernet CDMA EIA/TIA 232 (RS-232) IEEE 802.5 Token Ring TDMA ATM (SONET,…) ARCnet TDMA EIA/TIA 449 (RS-449) FDDI GPRS X.21 … GSM EIA/TIA 232 (RS-232) CPDP … Bluetooth Radio and Broadband … … Name of University - Class Title Physical Layer Processing Device 1 Layer 1 Physical Layer Data Link Layer Transmission Medium Layer 2 0111010111001 Data Link Layer 1001110101110 Layer 2 Device 2 Physical Layer Layer 1 Name of University - Class Title OSI Layer 2 : Data-Link Layer Application Software Layer System Software Layer LAN Wireless WAN Wired Wireless Wired NS IEEE802.2 LLC/SNAP IEEE 802.2 LLC/SNAP BSSGP IEEE802.11 MAC IEEE 802.3 Ethernet X.25 PSTN LAPB PPP HDLC PPP Bluetooth LMP, L2CAP, Baseband … ARCnet RFCOMM FDDI … … Hardware Layer Physical Layer ATM … IEEE 802.5 Token Ring … SLIP Name of University - Class Title Data-link Layer Processing Layer 3 Datagram Network Layer Data Link Layer [data] Data-link Headers Stripped Data-Link Headers Appended to Data Field Layer 2 110110101101110111011101110001100111000001100101000111 [Start of frame] [source addr][dest addr][admin][data] [ error chk][end of frame] 1110111000110 1 DataLink Frame Physical Layer Layer 1 Name of University - Class Title OSI Layer 3 : Network Layer Application Software Layer System Software Layer TCP/IP Stack OSPF ICMP RIP Banyan/VINES BGP … RTP ICP IP VIP GPRS SCCP BSSAP BSSMAP ISDN Data-link Layer Hardware Layer Physical Layer …. … Name of University - Class Title Network Layer Processing Layer 4 Packet Transport Layer Network Layer [data] Layer 3 Network Headers Stripped 11011011001101110001100001101101110111011101110001100111000001100101000111 [IP Version] [header len][data type][data len][frag info] [# hops][upper layer][checksum][source IP][dest IP][data] Datagram Network Datagram Network Header Appended to Data Field Data-link Layer Layer 2 Name of University - Class Title OSI Layer 4 : Transport Layer Application Software Layer System Software Layer TCP/IP Stack TCP UDP GSM … BSSMAP DTAP Network Layer Data-link Layer Hardware Layer Physical Layer WAP … WDP … Name of University - Class Title Transport Layer Processing Layer 5 Message/Pscket Session Layer Transport Layer [data] Layer 4 Transport Headers Stripped 11011011001101110001100001101101110111011101110001100111000001100101000111 [Src Port][Dest Port][Seq #][Ack #][H Len][Res][Uflag][Pflag][Rflag][Sflag][Fflag][WinSz][Chksum][UP[O] [Data] Packet TCP Packet Transport Header Appended to Data Field Network Layer Layer 3 Name of University - Class Title OSI Layer 5 : Session Layer Application Software Layer WAP Stack TCP/IP Stack … DNS NFS … WSP System Software Layer Transport Layer Network Layer Data-link Layer Hardware Layer Physical Layer … Name of University - Class Title Session Layer Processing Layer 6 Message Presentation Layer Session Layer [data] Session Headers Stripped 1101101100110111000110000110 [Length][Destination Channel ID][Data] Message/Packet L2CAP Packet Session Header Appended to Data Field Transport Layer Layer 4 Layer 5 Name of University - Class Title OSI Layer 6 : Presentation Layer Application Software Layer JPEG MIDI SSL MPEG Session Layer System Software Layer Transport Layer Network Layer Data-link Layer Hardware Layer Physical Layer … Name of University - Class Title Presentation Layer Processing Layer 7 Message Application Layer Presentation Layer Message conversion [data] Presentation Header Appended to Data Field 1101101100110111000110000110 [Length][Destination Channel ID][Data] Messag e Bluetooth Message Session Layer Layer 5 Layer 6 Name of University - Class Title OSI Layer 7 : Application Layer Application Software Layer MIME POP3 SMTP IMAP4 FTP Finger Telnet HTTP NCP Bootp Presentation Layer Session Layer System Software Layer Transport Layer Network Layer Data-link Layer Hardware Layer Physical Layer APPC SNMP BT-SDP RLOGIN NFS … Stanford University - EE109 Embedded Hardware Name of University - Class Title Many Many Many Embedded Processors To Choose From Architecture Processor Manufacturer AMD Au1xxx Advanced Micro Devices,… ARM ARM7, ARM9, … ARM, … C16X C167CS, C165H, C164CI,… Infineon,… ColdFire 5282, 5272, 5307, 5407, … Motorola,… I960 I960 Vmetro, … M32/R 32170, 32180, 32182, 32192, … Renesas/Mitsubishi, … M Core MMC2113, MMC2114, … Motorola MIPS32 R3K, R4K, 5K, 16, … MTI4kx, IDT, MIPS Technologies, … NEC Vr55xx, Vr54xx, Vr41xx NEC Corporation, … PowerPC (PPC) 82xx, 74xx,8xx,7xx,6xx,5xx,4xx IBM, Motorola,… 68k 680x0 (68K, 68030, 68040, 68060,…) ,683xx Motorola, … SuperH (SH) SH3 (7702,7707, 7708,7709), SH4 (7750) Hitachi, … SHARC SHARC Analog Devices, Transtech DSP, Radstone, … strongARM strongARM Intel, … SPARC UltraSPARC II Sun Microsystems, … TMS320C6xxx TMS320C6xxx Texas Instruments, … x86 X86 [386,486,Pentium (II, III, IV)…] Intel, Transmeta, National Semiconductor, Atlas, … TriCore TriCore1, TriCore2, … Infineon,… … … … Name of University - Class Title ISA Models Application Specific – – – – – General Purpose – – Controller Datapath Finite State Machine with Datapath [FSMD] Java Virtual Machine …. Complex Instruction Set Computing [CISC] Reduced Instruction Set Computing [RISC] Instruction Level Parallelism – – – – Single Instruction Multiple Data [SIMD] Superscaler Machine Very Long Instruction Word (VLIW) Computing …. Name of University - Class Title Implementing an ISA & Von-Neumann embedded system board Master Processor CPU controls usage and manipulation of data Memory Output Input 5 system components commonly connected via buses data from cpu or input devices stored in memory until a cpu or output device request brings data into the embedded system Memory Input Output gets data out of the embedded system Stanford University - EE109 Embedded Software Name of University - Class Title Embedded Software : The System Software Layer Application Software Layer Application Software Layer Application Software Layer System Software Layer System Software Layer System Software Layer Operating System Layer Middleware Layer Operating System Layer Board Support Package Layer Operating System Layer Application Software Layer System Software Layer Application Software Layer System Software Layer Middleware Layer Device Driver Layer Device Drivers Device Driver Layer Device Driver Layer Device Driver Layer Hardware Layer Application Software Layer Hardware Layer Application Software Layer Hardware Layer Hardware Layer Hardware Layer Application Software Layer Application Software Layer System Software Layer System Software Layer Operating System Layer System Software Layer Operating System Layer Middleware System Software Layer Operating System Layer Middleware Middleware Layer Middleware Operating System Layer Board Support Package Layer Device Drivers Device Drivers Board Support Package Layer Device Drivers Device Driver Layer Hardware Layer Hardware Layer Hardware Layer Hardware Layer ………… Name of University What are Device Drivers? - Class Title Application Software Layer System Software Layer Device Driver Layer Higher-layer Interface ----------------------Hardware Interface Higher-layer Interface Hardware Interface r Hardware Layer Application Layer System Software Layer Device Drivers Ethernet (SCC1) RS-232 (SMC2) PCMCIA DMA (IDMA) Interrupts T1/E1 (TDM) ISDN (TDM) MMU I2C … I/O … L1 Cache Buses Hardware Layer Generic (Architecture and Board Specific Driver) Architecture Specific Device Drivers Memory Timers … … Name of University - Class Title Most Common Types of Device Drivers Routines Hardware Startup, initialization of the hardware upon power-on or reset. Hardware Shutdown, configuring hardware into its power-off state. Hardware Disable, allowing other software to disable hardware on-the-fly. Hardware Enable, allowing other software to enable hardware on-the-fly. Hardware Acquire, allowing other software gain singular (locking) access to hardware. Hardware Release, allowing other software to free (unlock) hardware. Hardware Read, allowing other software to read data from hardware Hardware Write, allowing other software to write data to hardware Hardware Install, allowing other software to install new hardware on-thefly Hardware Uninstall, allowing other software to remove installed hardware on-the-fly Name of University - Class Title Embedded Operating Systems Process Management. – – – Process Implementation Scheduling Intertask Communication & Synchronization • – … Segmentation Paging Virtual Memory System Security … I/O System Management. – – Middleware (optional) Kernel Interrupt Handling, Error Detection, … Memory Management. – – – – – Embedded OS File System … Process Management I/O System Management Memory Management Interrupt/Error Handling Security System Management Device Drivers (Optional) Name of University - Class Title OS Models Higher-level Software (Middleware, Applications) Higher-level Software (Middleware, Applications) Microkernel Process Management Memory Management Monolithic Kernel file I/O Memory Management Process Management I/O Drivers Memory Drivers Interrupt Drivers Device Drivers I/O Hardware Memory Hardware The Operator Layered OS Layer 5 User Program Layer 4 Input/Output Management Layer 3 Operator Process Communication Layer 2 Memory & Drum Management Layer 1 Processor Allocation and Multiprogramming Layer 0 Interrupt Name of University - Class Title Process Management What is a process? Tasks vs. Threads Task 1 Program 1 Task 1 Registers Task 1 Stack Program 1 Program 2 OS (ie:..) … Task 2 Program 1 Task 2 Registers Task 2 Stack Task 3 Program 2 Task 3 Registers Task 3 Stack Program 1 OS Task Program 1 Task Registers Task Stack Thread 1 Program 1 Thread 1 Registers Thread 2 Program 2 Thread 2 Registers Thread 3 Program 3 Thread 3 Registers Memory Name of University - Class Title Unitasking vs. Multitasking OSes Program 1 Unitasking OS Task 1 Program 1 Task 1 Registers Task 1 Stack Program 1 Program 2 … Task Program 1 Task Registers Task Stack Multitasking OS Process 2 Program 1 Task 2 Registers Task 2 Stack Process 3 Program 2 Task 3 Registers Task 3 Stack Name of University - Class Title The OS Multitasking Illusion OS How? – – – – Implementation Scheduling Synchronization Inter-task Communication Name of University - Class Title Process Implementation & the Task Hierarchy OS Initial Task Task Task Task Task Task Task Task Task Creation Task Deletion Task Suspension Task Resumption Name of University << Task creation based upon “fork/exec” involve 4 major steps >> - Class Title Memory Process Table Parent Task TCB TCB TCB 1. Parent task makes fork system call to create child task Parent Task stack Parent Program fork System Call Memory Child Task TCB Task Creation and Fork/Exec TCB TCB Child Task [Parent Task Clone] stack Parent Program Parent Task stack Memory Child Task TCB TCB TCB exec System Call Child Task stack Parent Program Child Program 3. Parent task makes exec system call to load child task’s program Parent Task stack Parent Program 4. The child task program loaded into memory. Process Table Name of University - Class Title Task Creation & Spawn << Task creation based upon “spawn” involve 2 major steps >> Memory Process Table Parent Task TCB TCB TCB 1. Parent task makes spawn system call to create child task Parent Task stack Parent Program Spawn System Call Memory Child Task TCB 2. Child Task loaded into memory, including program, TBC, stack, etc. TCB Child Task stack Child Program Parent Task stack Parent Program TCB Process Table Name of University - Class Title Task Deletion System Call Garbage Collection 1 3 4 2 I Name of University - Class Title Resuming & Suspending Tasks : Task States 3 Main States – Ready : The process is ready to be executed at anytime, but is waiting for permission to use the CPU. – Running : The process has been given permission to use the CPU, and can execute. – Blocked or Waiting: The process is waiting for some external event to occur before it can be “ready” to “run”. Task States and Queues Name of University - Class Title Process State Transition Models When a task that is moved from one of the queues (READY or BLOCKED/WAITING) into the RUNNING state, it is called a context switch. Name of University Scheduling in OSes - Class Title Non-preemptive Schedulers – First-Come-First-Serve (FCFS)/ Run-To-Completion Current Task TN …….. T3 T1T2 T1 Scheduler T2 Master CPU No Context Switching After This Point – Shortest Process Next [SPN]/ Run-To-Completion Current Task TN …….. T3 T1T2 T2 T1 T3 Scheduler Master CPU Time T1 = 10ms Time T3 = 2ms Time T2 = 20 ms – Co-operative Current Task TN …….. T3 T1T2 T1 T2 Scheduler Master CPU Only Running Task can force a context switch before completion Name of University - Class Title Scheduling in OSes [Continued] Preemptive Schedulers – Round Robin/FIFO (First-in-First out) Scheduling HIGH KEY = preemption Time slice Priority | = task completion Task 1 Task 2 Task 3 LOW Time Task 1 Task 2 Task 3 Name of University - Class Title Scheduling in OSes [Continued] Preemptive Schedulers [Continued] – Priority [Preemptive] Scheduling Task 3 HIGH KEY = preemption Task 2 Task 2 Priority | = task completion Task 1 Task 1 LOW Time Name of University - Class Title Scheduling in OSes [Continued] Preemptive Schedulers [Continued] – EDF (Earliest Deadline First)/Clock Driven Scheduling p1 p1 q p1 p2 p3 p2 p3 admit r? r p1 q p1 What is an RTOS? – A preemptable kernel! – Deterministic r p2 r p3 Name of University - Class Title Intertask Communication & Synchronization Memory Sharing Memory Process 1 Shared Data Process 2 Process N Message Passing Signaling – Interrupt Handling Name of University - Class Title Memory Management User vs. Kernel Memory Space User Memory Space Divided Into Partitions – Segments – Pages – What is Virtual Memory? User Memory Allocation and Deallocation Scheme Depends on Programming Language Name of University - Class Title What is a BSP [Board Support Package] ? Name of University - Class Title Middleware & Application Software Application Software Layer System Software Layer Application Software Layer browser Video-On-Demand Web server Navigation Middleware Layer System Software Layer Hardware Layer Hardware Layer e-mail Name of University - Class Title Middleware Examples OSI Model Application Layer Presentation Layer Application Layer Application Software Layer Middleware Layer pJava 1.1.8 JVM Session Layer java.net Socket API Networking Middleware Transport Layer TCP Network Layer UDP System Software Layer IP Data-Link Layer Hardware Layer Physical Layer Hardware Layer Name of University - Class Title Application Layer Examples Application Layer Application Software Layer HTTP … FTP JVM System Software Layer System Software Layer Hardware Layer Hardware Layer Application Software Layer Browser SSL 128 Bit Encryption Java Script HTTP HTML4.0 Real Audio System Software Layer Hardware Layer DOM 0 CSS 1 Stanford University - EE109 Putting It All Together Name of University - Class Title 6 Stages Creating An Embedded System’s Architecture Stage 1 Having a solid technical base [Software & Hardware] Stage 2 Understanding the ABCs of Embedded Systems Stage 3 Defining the architectural patterns & reference models Stage 4 Creating the architectural structures Stage 5 Documenting the architecture Stage 6 Analyzing and evaluating the architecture. Name of University - Class Title Stage 2 : Understanding the ABCs [Architecture Business Cycles] of Embedded Systems Influences on Architecture …… Technical Requirements Quality Assurance Requirements System Stakeholders Customers Architecture Business Cycle Architecture Engineers Managers …. Industry Standard Requirements Sales & Marketing Requirements Embedded System Name of University - Class Title What are General ABC Requirements? - Business (Sales & Marketing) : sellability (how the device will sell), time-to-market (when will the device be delivered), costs (development, overhead, etc.), device lifetime (how long the device will be available on the market), target market (what type of device it is), schedule & features (schedule of versions to be released with associated features), etc. - Technical : performance, user friendliness (usability), modifiability (how simple it is to modify the various functional elements), security, reliability, portability, testability, availability, technical industry standards (see industry standards below), etc. - Industry : typically are a result of industry standards (introduced at start of presentation), which may be market specific (i.e. TV standards, medical device standards, etc.) or general purpose across different families of devices (programming language standards, networking standards, etc.) - Quality Assurance : testability (how easily the system can be tested), availability (when the system is available for testing), schedule & features (schedule of versions to be tested with associated features), QA industry standards (ie : ISO9000, ISO9001, and so on – see industry requirements above), etc. …. Name of University - Class Title Performance Scenerio System Response Measures (throughput, latency, data loss, etc.) Internal Stimulus Sources (other internal system elements) Performance Stimuli (periodic events, one-time events, etc.) Effected Element (Entire Embedded System) External Stimulus Sources (user, data over network, etc.) Environment (normal, high network traffic, etc.) System Response (events processed in timely manner, etc) Name of University - Class Title How to Derive System Components from Performance Requirements? System Response Measures (throughput, latency, response timedata loss, etc.) response time decrease Internal Stimulus Sources (other internal system elements) Embedded System Performance Stimuli (periodic events, one-time events, etc.) External Stimulus Sources (user, data over network, etc.) System Response (events processed in timely manner, etc) Operating System - Process events concurrently reducing response times -Scheduler manages requests and arbitration of resources to events -…. Tactic : Resource Management Requests Arbitration …… Name of University - Class Title Security Scenerio System Response Measures (latency in system recovery, effectiveness of system fix for previously encountered stimuli,etc.) External Stimulus Sources (user, data over network, etc.) Security Stimuli (system shutdown, altering data, copying data, etc.) Effected Element (Data in Memory of Embedded System, other accessible system services) Environment (normal, connected/disconnected to network, data uploads/ downloads, etc.) System Response (recovering, detecting, resisting attacks, etc) Name of University - Class Title How to Derive System Components from Security Requirements? System Response Measures (latency in system recovery, effectiveness of system fix for previously encountered stimuli,etc.) fewer security breeches Embedded System External Stimulus Sources (user, data over network, etc.) Operating System Security Stimuli (system shutdown, altering data, copying data, etc.) - Memory Management - Security Management -…. Java [JVM] System Response (recovering, detecting, resisting attacks, etc) - Garbage Collector - Cryptography - Authentication - Authorization - Security “Sandbox” -…. Tactic : Managing Resource Access Authentication Authorization …… Name of University - Class Title Testability Scenerio System Response Measures (testing times, number of tests performed, accuracy of tests, etc.) Internal Stimulus Sources (other internal system elements) External Stimulus Sources (user, data over network, etc.) Testability Stimuli (hardware/software completed, hardware/software update, etc.) Effected Element (Some or all software/hardware elements within Embedded System) Environment (development, production, in field, etc.) System Response (easily controlled and observable responses to tests, , etc) Name of University - Class Title How to Derive System Components from Testability Requirements? System Response Measures (testing times, number of tests performed, accuracy of tests, etc.) easier testing Internal Stimulus Sources (other internal system elements) External Stimulus Sources (user, data over network, etc.) Embedded System Testability Stimuli (hardware/software completed, hardware/software update, etc.) Debug System Software Subroutines Processor - Built-In Monitor - Manipulate Variables - Memory Dumps - Single-step through executing code …. Tactic : Internal Monitoring Visibility Accessibility …… System Response (easily controlled and observable responses to tests, , etc) Name of University - Class Title Stage 3 : Defining the Architectural Patterns & Reference Models Create the system profile Make a matrix to determine if components meet cost, timeto-market, performance ... requirements Requirement 1 Requirement 2 Requirement 3 Requirement … Requirement “N” Product 1 YES Features … NO NOT YET Next Year … … Product 2 YES Features … YES Features … YES Features … … … Product 3 NO YES Features … NO … … Product 4 YES Features … NOT YET In 3 Months NOT YET In 6 Months … … Product … …. …. …. …. … Product “N” … … … … … Name of University - Class Title Selecting a Programming Language Real-Time Fast Performance MHP-Spec ATVEF-Spec Browser Application … Assembly YES YES NOT Required NOT Required NOT Required … C YES YES Slower then assembly NOT Required NOT Required NOT Required … C++ YES YES Slower then C NOT Required NOT Required NOT Required … NO WinCE NOT RTOS Depends on processor, slower then C on less powerful processors NOT Required NOT Required NOT Required … Depends on JVMs byte code processing scheme (WAT almost as fast as C where interpretation requires more powerful processor i.e. 200+ MHz), slower then C on slower processors YES NOT Required NOT Required … Slower because of the interpretation that needs to be done but depends on what language interpreter written in (see above cells of this column) NOT Required YES YES … … … … … … .NetCE (C#) JVM (Java) Depends on JVM’s Garbage Collector and is OS ported to is RTOS HTML (Scripting) Depends on what language written in, and the OS (an RTOS in C/assembly OK, .NetCE platform no, Java depends on JVM … … Name of University - Class Title Selecting an OS Questions to ask : – 1. What type of systems typically use or require an OS? – 2. Is an OS needed to fulfill system requirements? – 3. What is needed to support an OS in a design? – 4. How to select the OS that best fits the requirements? Tools Portability Non-kernel Processor Scheduling Scheme … vxWorks Tornado IDE, SingleStep debugger, … BSP Device Drivers w/ BSP, graphics, networking, … Hard Real-Time, Prioritybased … … Linux Depends on vendor for development IDE, gcc, … Depends on vendor, some with no BSP Device Drivers graphics, networking, … Depends on vendor, some are hard real-time, others softreal time … … Jbed Jbed IDE , Sun Java compiler, … BSP Device Drivers – the rest depends on JVM specification (graphics, networking, …) x86, MIPS, 68K, ARM, strongARM, PPC … Depends on vendor (x86, PPC, MIPS, …) PPC, ARM, … EDF Hard Real Time Scheduling … … … … … … … … … Name of University - Class Title Selecting a Master Processor Tools Java-specific Features OS Support … JEMBuilder, Charade debugger, J2ME/CLDC JVM NOT Needed … Tornado tools, Jbed Tools, Sun tools, Abatron BDM… Implemented in software (Jbed, PERC, CEE-J, …) Coming Soon -Linux, vxWorks, Jbed, Nucleus Plus, OSE, … … Hitachi Camelot Superscaler SoC(Instruction Level Parallel ISA) Tornado Tools, QNX Tools, JTAG, … Coming Soon -Implemented in software (IBM, OTI, Sun VMs ..) Coming Soon -QNX, vxWorks, WinCE, Linux, .... … … … … … … aJile aj100 Java Processor (Application Specific ISA) Motorola PPC823 (General Purpose ISA) Select processor on requirements and its impact on the remainder of the system (especially software). Why ? – The master processor essentially impacts what enhancements are implementable in software, and what constraints are placed upon the software Name of University - Class Title Stage 4 : Define the Architectural Structures Module Logical “4+1” Model Component & Connector Process Allocation Development Deployment Validation - Logical Scenarios - Process Scenarios - Development Scenarios - Deployment Scenarios Name of University - Class Title Stage 5 : Document the Architecture Step 1 : A document outlining the entire architecture. Step 2 : A document for each structure. User Embedded Device User opens application via user interface OS task spawned loading application into memory and begins to execute User selects option X in application ……. Rough/Informal Sequence Diagram UML Sequence Diagram UML Use Case Diagram Step 3 : An architecture glossary. Name of University - Class Title Stage 6 : Analyze and Evaluate Architecture Step 1- Members of the evaluation team obtain copies of the architecture documentation from the responsible architect (s), and it explained to the various team members the evaluation process, as well as, the architecture information within the documentation to be evaluated. Step 2 - A list of the architectural approaches and patterns is compiled based upon feedback from the members of the evaluation team after they have analyzed the documentation. Step 3 – The architect (s) and evaluation team members agree upon the exact scenarios derived from the requirements of the system (the team responding with their own inputs of the architect’s scenarios : changes, additions, deletions, etc.), as well as, the priorities of the various scenarios are agreed upon in terms of both importance and difficulty of implementation. Step 4 - The (agreed upon) more difficult and more important scenarios are where the evaluation team spends the most time on evaluating, because these scenarios introduce the greatest risks. Step 5 – Results of evaluation team should include (at the very least) the 1) uniformly agreed upon list of requirements/scenarios, 2) benefits (i.e. the ROI – Return-On-Investment aka. the ratio of benefit to cost), 3) risks, 4) strengths, 5) problems, and 6) any of the recommended changes to the evaluated architectural design.