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Introduction
CEG 4131 Computer Architecture III
Miodrag Bolic
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Four levels of computer description
Gate level
– Specify operations at the individual bit level
– Gates are primitive elements
– Very cumbersome to do manually (logic minimization, etc.)
Register level
– Specify internal operation of processor-level components at
the word level
– Primitives:
» Registers
» Counters
» Memories
» ALUs
» Clocks
» Combinational logic
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Four levels of computer description
Processor level
– Architectural Features specified
» Interfaces
» Instruction sets
» Data Representation
– More detailed individual component specification
Global system structure
– Overall system structure is defined
– Major components identified
» Processors
» Control modules
» Memory modules
» Interconnection structure
– Mostly a static description -- “black box” approach
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Basic parallel techniques [1]
• Pipelining (time)
– a number of functional units are employed in sequence to
perform a single computation
– a number of steps for each computation
• Replication (space)
– a number of functional units perform computation simultaneously
• more processors
• more memory
• more I/O
• Replication at the following levels:
–
–
–
–
Processor (multiple functional units)
Chip (multiple processors and/or hardware blocks)
Board (multiple processors and/or hardware systems)
Multiple computers
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Course Content - Interconnection Networks
• Topologies of static networks
–
–
–
–
–
fully connected,
rings, meshes,
torii,
hypercubes,
k-ary n-cubes
• Dynamic networks
– Buses
– Multistage intercon. networks
– Crossbar switch networks
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Course Content – Shared Memory Arch.
• Shared memory models
– Communication occurs implicitly as result of loads and stores
• Cache coherence
• Programming shared memory systems
Shared memory
I/O1
Interconnection
network
I/On
PE1
PEn
Processors
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Course Content – Message Passing Arch.
• Message passing models
– direct access only to private address
space (local memory),
– communication via explicit messages
(send/receive)
• Routing
• Programming message passing
systems
• Easier to scale than shared memory
systems
Interconnection
network
PE1
PEn
M1
Mn
P1
Pn
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Course Content – Single Processor Parallelism
• Vector processors
• VLIW processors
• Superscalar processors
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What will you learn from Labs?
• New approaches to design from the system level
perspective
– System-on-chip architectures
– Design using IP (Intellectual Property) cores
– Configurable instruction set architectures
• Altera tools
– SOPC builder
– NIOS IDE
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System-on-chip architectures
• Single-processor architectures
Nios Processor
Tri-State
Bridge
Address (32)
Read
Data In (32)
Data Out (32)
IRQ
IRQ #(6)
Compact
Flash
PIOs
SDRAM
Controller
Write
Avalon Bus
32-Bit
Nios
Processor
Tri-State
Bridge
ROM
(with Monitor)
LED PIO
UART
General
Purpose
Timer
Periodic
Timer
LCD PIO
7-Segment
LED PIO
Reconfig
PIO
Button PIO
• Multiprocessor architectures
• Cache coherence solutions for multiprocessors
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References
1. Desco Sima, Terence Fountain and Peter Kascuk,
Advanced Computer Architectures – A Design Space
Approach, Pearson, 1997.
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