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16.317 Microprocessor Systems Design I Instructor: Dr. Michael Geiger Spring 2013 Lecture 21: Exam 2 Preview Lecture outline Announcements/reminders Lab 2 due 4/5 Exam 2: Wednesday, 3/27 Today’s lecture: Exam 2 Preview 5/24/2017 Set on condition instructions Jump instructions Loop instructions Subroutines Protected mode HLL assembly Microprocessors I: Exam 2 Preview 2 Exam 2 notes Allowed One 8.5” x 11” double-sided sheet of notes Calculator No other notes or electronic devices (phone, laptop, etc.) Exam will last 50 minutes Covers all lectures after Exam 1 (13-20) Format similar to previous exam 5/24/2017 1 multiple choice question 2-3 short problems to solve/code sequences to evaluate Microprocessors I: Exam 2 Preview 3 Review: set on condition, jump, loop SETcc D Sets single byte destination to 1 (01H) if condition true; all 0s (00H) if condition false Can be used to build up complex conditions Two general types of jump Unconditional: JMP <target> Conditional: Jcc <target> Always go to target address Go to target address if condition true Loop instructions Combines CX decrement with JNZ test May add additional required condition 5/24/2017 LOOPE/LOOPZ: loop if ((CX != 0) && (ZF == 1)) LOOPNE/LOOPNZ: loop if (CX != 0) && (ZF == 0)) Microprocessors I: Exam 2 Preview 4 Review: subroutines Subroutines: low-level functions When called, address of next instruction saved Return instruction ends routine; goes to that point May need to save state on stack 80386 specifics CALL <proc>: call procedure RET: return from procedure Saving state to stack: push instructions 5/24/2017 <proc> can be label (16-/32-bit imm), reg, mem Store data “above” current TOS; decrement SP Basic PUSH stores word or double word Directly storing flags: PUSHF Storing all 16-/32-bit general purpose registers: PUSHA/PUSHAD Restoring state: POP/POPF/POPA/POPAD Microprocessors I: Exam 2 Preview 5 Review: protected mode memory accesses Determine if access is local or global 1. Use TI bit in selector Segment registers now function as selectors TI == 0 global access TI == 1 local access Find the starting address of the appropriate descriptor table 2. Global access uses GDT Local access uses current LDT 5/24/2017 GDTR holds base/limit of GDT LDTR cache holds base/limit of LDT Microprocessors I: Exam 2 Preview 6 Review: protected mode memory accesses Find the right descriptor in GDT/LDT 3. Index field in selector chooses entry in GDT/LDT Tables are 0 indexed 1st descriptor = descriptor #0 Starting address of descriptor = (table base) + (index * 8) Descriptor holds base/limit for segment Use the segment base address found in the descriptor to calculate the physical address 4. 5/24/2017 Physical address = (segment base) + (EA) Microprocessors I: Exam 2 Preview 7 Review: local descriptor table Each task has its own local descriptor table LDT changes every time you change tasks Base/limit of that table changes LDTR cache holds LDT base (32 bits) and limit (16 bits) LDT base/limit for each task is stored in a descriptor in the GDT LDTR: selector pointing to GDT entry describing LDT for current task 5/24/2017 TI == 0 in LDTR Index point to descriptor with LDT base/limit for current task On task switch, LDTR changed and LDT base/limit reloaded Microprocessors I: Exam 2 Preview 8 Review: HLL assembly Data accesses Global variables static; allocated in data segment Other variables dynamic; allocated on stack Stack frame for each function contains (from top) Conditional statements (if-then-else) Saved variables within function Local variables for function (starting at EBP – 4) Saved EBP Saved EIP Function arguments (starting at EBP + 8) Evaluate condition (CMP instruction(s)) Conditional jump (often to “else” case) “If” case ends with unconditional jump to skip “else” Loops 5/24/2017 Initialize variable at start Test loop condition (similar to if) Change loop variable Microprocessors I: Exam 2 Preview 9 Final notes Next time: Exam 2 Allowed calculator, one 8.5” x 11” note sheet Will be provided list of instructions/condition codes Please be as close to on time as possible Reminders: 5/24/2017 Lab 2 due 4/5 Microprocessors I: Exam 2 Preview 10