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The Effects of Pipelining on Signal Accuracy and Propagation Delay Ammon Hardcastle Advisor Dr. Ken Stevens Overview ► Problem Passive circuit noise Active circuit noise ► Test circuit qualifications ► Circuit design ► Simulation setup ► Results ► Conclusion Passive Circuit Noise ► Passive circuit elements: resistors, capacitors and inductors ► Clean signal ► Resistor ► Resistor, and capacitor (RC) capacitor and inductor (RLC) Active Circuit Noise ► Active circuit elements: ► Saturation transistors current ► Triode current ► Non-ideal transistor switching Signal integrity Signal propagation Proposed Test ► Design a pipelined Fibonacci simulator Used to test the accuracy of the model order reductions of the two phase algorithm ►3 desired qualities RLC separate from circuit ►Passive vs. Active noise Pipelined ►Signals can be evaluated throughout the circuit ►Signal locations are known throughout the circuit Testable ►Signals are predictable Circuit Design ► Fibonacci: Starting at stage 6 (8 13 21 34...) ► 4 circuit designs: 1 Stage (8 21) 4 Stages (8 89) 8 Stages (8 610) 16 Stages (8 28, 657) Power In 13 8 16-Bit Adder 16-Bit Register Micron Single Layer Package 21 89 610 Power Out 28,657 Simulation Setup ► Purpose of simulations Determine accuracy of propagating signals Compare differences between simulators ►3 test simulation Control ►HSPICE ►Ideal power 1.2V (No Noise) Single voltage source through package ►HSPICE and HSimPlus Independent voltage sources through package ►HSPICE and HSimPlus Results Independent Single Ideal voltage voltagevoltage source source sources ►HSimPlus HSPICE multiple single vs. HSPICE vs. Single vs. Ideal Results - Continued ► Delay variation from control simulation 575 525 Delay (pS) 475 425 HSPICE Single 375 HSPICE Mult 325 275 225 175 125 75 25 -25 0 2 4 6 8 Stages 10 12 14 16 18 575 525 475 Delay (pS) 425 375 325 HSIM Single 275 225 HSIM Mult 175 125 75 25 -25 0 2 4 6 8 Stages 10 12 14 16 18 Conclusion ► Power IC designs sensitive to current fluctuations ► 1st stage has the largest current 1st stage has largest signal delays ► Mean variation delay caused by noise decreases as the signal propagates Multiple supplies have little affect on this circuit ► Worst case improvement of only .5% ► 6 cases with no improvement ► Signal Propagation Golden model underestimates actual delay ► Variations ► HSimPlus up to 544pS (HSPICE) vs. HSPICE 1st stage delay only 50% of HSPICE ► Largely underestimates noise affects for this circuit