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Transistor Structure DMT 241 – Introduction to IC Layout Outline – Transistor structure BJT PMOS NMOS CMOS BJT • Bipolar Junction transistor is a 3 – terminal elements that obtains its electrical characteristics from the properties of pn junctions. • 2 types of BJT – npn – pnp • The current flowing through an npn transistor is due mostly to electrons, while that through a pnp devices is due to hole BJT- symbol BJT • Reverse active bias – VBE > 0 and VBC<0 – Allows amplification – Used for analog circuit • Saturation – VBE > 0 and VBC>0 – Large current can flow through the devices but the transistor does not control the value • Cutoff – VBE < 0 and VBC<0 – Small leakage currents can flow – Model as open swotch • Forward active bias – VBE < 0 and VBC>0 – Used only a few special cases MOS transistor • MOS: Metal – Oxide – Semicomductor • Majority carrier device in which the current in a conducting channel between the source and drain is controlled by a voltage applied to gate • nMOS: majority carrier are electrons • pMOS: majority carrier are holes Chapter 6 page 263 MOS Behavior • Examined an isolated MOS structure with a gate and body but no source and drain • Top layer : polysilicon • Middle layer: silicon dioxide • Bottom layer: silicon body polysilicon gate silicon dioxide insulator Vg < 0 + - p-type body (a) 0 < V g < Vt + - depletion region (b) V g > Vt + - (c) inversion region depletion region MOS Behavior • Accumulation – Negative voltage is applied to gate – Mobility positively charged hole are attracted to the region beneath the gate • Depletion – Low positive voltage is applied to gate – Resulting some positive charge on the gate – The hole in the body are repelled from the region directly beneath the gate, resulting in a depletion region forming below the gate polysilicon gate silicon dioxide insulator Vg < 0 + - p-type body (a) 0 < V g < Vt + - depletion region (b) V g > Vt + - (c) inversion region depletion region MOS Behavior • Inversion – A higher positive potential exceeding a critical threshold voltage applied, attracting more positive charge to the gate – The holes a repelled further and a small number of free electrons in the body are attracted to the region beneath the gate polysilicon gate silicon dioxide insulator Vg < 0 + - p-type body (a) 0 < V g < Vt + - depletion region (b) V g > Vt + - (c) inversion region depletion region nMOS transistor • Four terminals: gate, source, drain, body • Gate – oxide – body stack looks like a capacitor – Gate and body are conductors – SiO2 (oxide) is a very good insulator – Called metal – oxide – semiconductor (MOS) capacitor Source Gate Drain – Even though gate is no longer made of metal n+ n+ p bulk Si Polysilicon SiO2 nMOS operation • Mode of operation depends on Vg, Vd, Vs – Vgs = Vg – Vs – Vgd = Vg – Vd – Vds = Vd – Vs = Vgs - Vgd • Three regions of operation – Cutoff – Linear – Saturation nMOS Cutoff • No channel • Vgs < Vt • Ids = 0 Vgs = 0 + - g + - s d n+ n+ p-type body b Vgd nMOS Linear • Channel forms Vgs > Vt + - – Vds = Vgs-Vgd – If Vds=0 (i.e. Vgs=Vgd) + - s d n+ n+ • No electrical field tending to push current fr. d to s. • Small positive potential Vds • Current flows from d to s – e- from s to d • Ids increases with Vds • Similar to linear resistor g Vgd = Vgs Vds = 0 p-type body b Vgs > Vt + - g s + d n+ n+ p-type body b Vgs > Vgd > Vt Ids 0 < Vds < Vgs-Vt nMOS Saturation • Channel pinches off • Ids independent of Vds • We say current saturates • Similar to current source Vgs > Vt + - g + - Vgd < Vt d Ids s n+ n+ p-type body b Vds > Vgs-Vt Nmos region of operation 1. Cutoff region: VGS < VT, any value of VDS ID = 0 2. Linear (or Resistive, or Triode) region: VGS > VT, VDS < (VGS – VT) V I D VGS VT DS VDS 2 W where nCox L 3. Saturation region: VGS > VT, VDS > (VGS – VT) I DSAT 2 VGS VT 2 where n Cox W L “CUTOFF” region: VG < VT pMOS transistor • Similar, but doping and voltages reversed – – – – Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior Source Gate Drain Polysilicon SiO2 p+ p+ n bulk Si pMOS operation • Behave as nMOS but with the signs reverse and I-V characteristic in the third quadrant • Mobility of holes in silicon is typically lower than electrons. This means pMOS transistor provide less current than nMOS transistor of comparable size and hence are slower CMOS inverter Outline nMOS Operation Cutoff Vgsn < Vtn Vin < Vtn Linear Vgsn > Vtn Vin > Vtn Vdsn < Vgsn – Vtn Vout < Vin - Vtn Vgsn = Vin Saturated Vgsn > Vtn Vin > Vtn Vdsn > Vgsn – Vtn Vout > Vin - Vtn VDD Vdsn = Vout Vin Idsp Idsn Vout pMOS Operation Cutoff Linear Vgsp > Vtp Vgsp < Vtp Vin > VDD + Vtp Vin < VDD + Vtp Vdsp > Vgsp – Vtp Vout > Vin - Vtp Vgsp = Vin - VDD Vdsp = Vout - VDD Saturated Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp – Vtp Vout < Vin - Vtp VDD Vtp < 0 Vin Idsp Idsn Vout Operating Regions (Summary) Region nMOS pMOS Output A Cutoff Linear Vout = VDD B Saturation Linear Vout > VDD/2 C Saturation Saturation Vout drops sharply D Linear Saturation Vout < VDD/2 E Linear Cutoff Vout = 0 NMOS off PMOS res 2.5 Vout 2 NMOS s at PMOS res 1 1.5 NMOS sat PMOS sat 0.5 NMOS res PMOS sat 0.5 1 1.5 2 NMOS res PMOS off 2.5 Vin The end