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Midterm Presentation
Michelle Berger
John Curtin
Trey Griffin
Aaron King
Michael Nordfelt
Jeffrey Whitted
PDACS
Getting Started
• Finalized components
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–
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Harris Semiconductor 8-bit A/D Converter (ADC804 )
Texas Instruments 8-bit D/A Converter (TLC7524)
National Semiconductor 16550 UART
Maxim 232 Chip
Atmel Serial DataFlash Memory (AT45D161)
• Established electronic log and expenditures files
PDACS
Team Assignments
After we obtained our components and our collective
group decisions were made, we split ourselves up into
three distinct teams:
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•
•
•
A/D - D/A Team (Michelle & Aaron)
Serial / GUI Team (Mike & Trey)
Memory Team (John & Jeffrey)
Compression (Michelle, John, & Aaron)
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D/A - A/D Team
Progress:
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•
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A/D handled by ADC0804
Test circuit indicates A/D provides expected response
D/A handled by TLC7524
Test circuit indicates D/A provides expected response
A/D - D/A test circuit built and provides expected response
Numerous problems encountered with D/A before settling
on TLC7524 chip
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D/A Problems
• The DAC0830 worked correctly but its conversion
rate was too slow to keep up with the A/D.
• The DAC0800 was a troublesome chip.
– Five separate test circuits built with the 0800
– Example: one test circuit behaved correctly until the
output voltage approached 0.7 volts; beyond that point
the output voltage was unpredictable
– Result: none of the test circuits worked correctly, so we
moved to another chip
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D/A Solutions
These are possible solutions we considered for D/A:
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•
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•
Work with resistor values to get the 0800 to work
Try another chip we had just received: the TLC7524
Reduce sampling rate so the 0830 is fast enough
Build our own D/A converter using discrete components
We chose to try the TLC7524, which proved to be a
viable solution.
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A/D-D/A Test Circuit
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Memory Subsystem
• Atmel 16-Megabit 5-volt Serial DataFlash
Memory
Flash Memory Array
Page (528 Bytes)
Buffer 2 (528 Bytes)
Buffer 1 (528 Bytes)
I/O Interface
SI
SO
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Memory Subsystem
Verilog module flow:
• Determine read, buffer write, or main memory
program and set matching opcode
• Clock in the necessary bits one at a time
• Update control variables and test the edge
conditions
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Memory Subsystem
• Read command
Opcode
(10 bits)
Page address
(12 bits)
Byte address
(10 bits)
Don’t Care [X]
(32 bits)
• Buffer write command
Opcode Don’t Care [X]
(10 bits) (12 bits)
Buffer address
(10 bits)
• Main memory program command
Opcode Page address Don’t Care [X]
(10 bits) (12 bits)
(10 bits)
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Memory Subsystem
Problems:
• Large number of values to track
• SCK pin
To do:
• Test read functionality
• Test write functionality
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Serial Subsystem
Specs:
• Consists of two chips(16550 UART and Max232)
and a 9-pin serial jack
• Pin count to the Xilinx stands at 18
Progress:
• Logical layout for pins and chips determined
• Ordering of signals for communication determined
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Serial Subsystem
To do:
• Xilinx control module for the 16550 UART
• Physical layout
• Testing
– Interfacing with memory access module
– Interfacing with the GUI
PDACS
A0 A1 A2
PC16550DN
MR
XILINX
D0
D1
D2
D3
D4
D5
D6
D7
_______
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
Serial Subsystem
Vdd
__
RI
____
DCD
____
DSR
____
CTS
Vcc
Picture goes here, maybe a communications diagram
RXRDY
_______ __
INTR TXRDY RD
__
WR
CLK
SIN
SOUT
CS0
CS1
___
CS2
__________
INTR
______
BAUDOUT
RXRDY
XIN
A0
A1
XOUT
___
A2
____
WR
ADS
WR
______
TXRDY
Vss
Vcc
C1+
Vcc
V+
GND
T1out
C1-
MAX232
C0+
C2+
V-
RX
TX
T2out
R2in
R1in
MR
_____
OUT1
____
DTR
____
RTS
_____
OUT2
DDIS
GND
DSR
GND
RD
__
RD
GND
DTR
R1out
T1in
T2in
R2out
PDACS
Serial Subsystem
Memory
XILINX
16550
Master Reset
Max232 Application
DSR
DTR (Computer
Ready)
Interrupt
Check MSR
DSR Active
Notify GetData
Data
Last Block
Data
Data
Data
Data
Set DTR
DTR (Data finished)
DSR
PDACS
GUI
• Allows user to access the serial port and download
the data from the device.
• The GUI was developed in Visual Basic (to allow
rapid development)
• Visual Basic allows read/writing to all control
lines for serial communication.
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GUI
Future considerations:
• Decompresses sound files through software,
output to a .wav file
• Allow user to play a
compressed file
through the Windows
soundplayer.
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Serial/GUI Integration
• Used a Basic Stamp II to simulate serial port
activity.
• GUI effectively captures all serial port traffic and
dumps it to a binary file.
• GUI is capable of setting and reading all of the
necessary control lines.
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Compression Algorithms
• Companding Algorithm
– written in Verilog
– achieves 2:1 compression ratio
– very lossy
• DCT Algorithm
– Experimented with in C
– In progress
PDACS
Breakdown of Work
Division of Labor to date
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Michelle Berger - Compression & A/D & D/A systems
John Curtin - Compression & Memory systems
Trey Griffin - GUI & Serial Interface systems
Aaron King - A/D & D/A systems
Michael Nordfelt - GUI & Serial Interface systems
Jeffrey Whitted - Memory system
PDACS
Schedule of Work
• Weeks 1-3
– A/D and D/A
– Compression Research
– Finalize Components
• Weeks 4-6
– Serial Port Interface Researched/GUI Developed
– Memory Module Finalized/Hardware Wrapped
– A/D and D/A Developed
PDACS
Schedule of Work
• Weeks 7-10
– Compression Research/XILINX Implementation
– A/D and D/A Finalization
– Serial Hardware Finalization
• Weeks 11-12
– Final System Integration
– Testing
– Final Presentation and Product Delivery
PDACS
Ratings
• Level of difficulty
– 1
• Coordination among team members
– 1
• Support from the lab
– 1
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And Remember…
Xilinx is cool, but it’s
occasionally bogus.
-Scott
PDACS