Download Presentation Part A - High Speed Digital Systems Laboratory

Final Presentation
Project name: Synchronization for Quantum
Encryption System
Project supervisor
: Yossi Hipsh .
Project performed by : Omer Mor,
Oded Belfer.
Quantum Encryption System -Synchronization
Project Goal

The Synchronization system is an integral part
of a quantum encryption system. The system
will allow transferring messages in a safe way
that a third unauthorized person would not be
able to decipher .
 The Synchronization system is needed to
control the detector so it would be able to
identify a single photon in an optic cable at a
given time .
Quantum Encryption System -Synchronization
System requirements

Locate and place a single photon with 0.5nSec
accuracy resolution, in a 3nSec window.
 The system should be a “stand alone” system and
not depended on other components of the
encryption system. For that we will need to
simulate the other systems.
 The system should be capable to work with very
fast pulses.
 The system will receive an Optic Sync signal and
transfer it to a delayed electric signal, according
to the photon arrival.
Quantum Encryption System -Synchronization
General Block scheme
PC
End
Transmitter
Optic Sync
Start
Electric 3nSec
Sync pulse
Syncronization
System
Receiver
Feedback
Our part
Optic Data (Photon)
Quantum Encryption System -Synchronization
Synchronization system –
General Block scheme
5V
Surface
Quantum Encryption System -Synchronization
3.3V
Surface
General Block scheme –
5V Surface
Ref – Test point
Pulse width 35nSec
Pulse
stretcher
Splitter
TTL
NB3L553
5V Surface
Synchronization board.
Optic sync
From transmitter
Optic Detector
Board
Ref – T.P
To
3.3V
τ ≤ 0.5μSec
D.D.L
TTL
D.D.L
TTL
3D7408_1
3D7408_1
D.D.L
TTL
Photon
TTL To
ECL
Splitter
TTL
NB3L553
Sync
3D7408_1
Computer
FPGA
Quantum Encryption System -Synchronization
MC100ELT20
General Block scheme –
3.3V Surface
30pSec ≤ τ ≤ 10nSec
From 5V
Surface
D.D.L
ECL
Pulse width 3nSec
PECL To
LVPECL
Mono
Stable
Splitter
ECL
3.3V Surface
Balanced to
Unbalanced
Splitter
ECL
MC100EP195 MC100EP11
D.D.L
ECL
MC100EP11
MC100LVEL92
Ref – Test
point
To
Receiver
Splitter
ECL
MC100EP195 MC100EP11
Synchronization board.
Balanced to
Unbalanced
Ref – Test
point
Quantum Encryption System -Synchronization
Special components –
Optic Detector Board
Balanced
9V Input
Regulator
3.3V
Optic
Detector
Unbalanced
Transformator
Optic Sync. Input
From transmitter
Quantum Encryption System -Synchronization
Pulse
stretcher
Special components –
Stretcher
From
'0'
Optic Detector
'1'
TTL To
ECL
MC100ELT20
S
Q
D
Flip Flop
CLK
_
Q
ECL To
TTL
MC100ELT21
Splitter
TTL 1:4
NB3L553
R
MC100EP31
TTL To
ECL
D.D.L
ECL
MC100ELT20
3D7408_1
Quantum Encryption System -Synchronization
Special components –
Mono Stable
From
TTL To ECL Splitter
ECL 1:2
MC100EP11
D.D.L
ECL
'0'
S
'1'
D
Q
Flip Flop
R
CLK
_
Q
MC100EP195
D.D.L
ECL
MC100EP195
Quantum Encryption System -Synchronization
MC100EP31
Special components – Bal-UN
Balanced to Unbalanced
IN
OUT
140Ω
+
-
100nF
140Ω
100nF
68Ω
68Ω
68Ω
VTT
Quantum Encryption System -Synchronization
68Ω
Special components –
FPGA Input Output
Computer
Sync END
“Photon” – from splitter #1
“Sync” – from splitter #2
ADD1
Enable
ADD2
ValidEnable
photon 1
Valid photon 2
Sync START
10 Bit Bus
D.D.L
TTL
X4
D.D.L
ECL
X4
LEN
FPGA
STR1
STR2
* ’Valid photon’ will be used
only if STR is not available.
Quantum Encryption System -Synchronization
LEN
Optic Detector Board

The optic detector board will receive optic
signal and translate it to a balanced electric
pulse.
 The board will supply the working needs for
the Optic detector.
 Input : Optic signal (Laser).
 Output : Balanced electric pulse.
Quantum Encryption System -Synchronization
Aspects in choosing components

Technological compatibility - (TTL/ECL, input and
output voltage) – most of the components we chose works
in TTL technology because we needed width pulse for the
computer and to the long delay device.
 System compatibility - (with the transmitter, receiver
and computer) – the transmitter output is an optic pulse so
we needed to add an optic detector. The receiver input is in
ECL technology so we need to convert the output
technology to ECL and to low voltage .
 Short Trise and Tfall – because we deal with a short an
accurate pulses.
 Available for purchase.
Quantum Encryption System -Synchronization
System Inputs

Optic Sync pulse from the transmitter – we will
simulate this pulse with a laser to test our system before
integration with the transmitter.

STR1 & STR2 pulses from the receiver –
feedback to check the photon arrival. We simulated this
pulse as Valid Photon 1&2 in the FPGA to test our system
before integration with the receiver.
 SYNC_START from the PC – starting the
calibration sequence. We also assigned a switch on the
board to simulate SYNC_START command.

FPGA Control
Quantum Encryption System -Synchronization
System Outputs
Delayed electric Sync to the receiver – the pulse will be
delayed according to the photon arrival, we will be able to
test this pulse with a scope in the reference test points.
 D.D.L control from FPGA – controlling the D.D.L delay
– a binary word that will translated to delay in the D.D.L.
 MIX_Enable from FPGA – MIX Enable=‘1’ while
calibrating the system, MIX Enable=‘0’after calibration is
over - reactivate the MIX in receiver.
 Sync_end form FPGA – Informing the computer that the
calibration is over.

Quantum Encryption System -Synchronization
Hardware specification & Needs

The Pulse input for the board should be at least 2V
high, because the optic detector board output levels are
low we need an Amplifier between the him and the
board input.
The chosen amplifier needs a 24V transformer .
 The optic detector board needs 9V transformer .
 50 PIN flat cable for connecting the FPGA to our board
 Scope for checking the system performance .
Quantum Encryption System -Synchronization
Power Supply's specification



The board needs 5V power supply.
The 5V input is inserted into 3 Voltage regulators that
will create the needed voltages for the 3 others voltage
surfaces.
Every regulator has a variable resistor connected to
him, so we will have a tolerance to the voltages we can
supply to the rest of the board.
Quantum Encryption System -Synchronization
Power Supply's Distribution
5V
5V Input
5V Surface VIA
Variable Resistor 500 Ω
Voltage
Regulator
3.3V
3.3V Surface VIA
PTH04000W
Voltage
Regulator
3V
3V Surface VIA
Variable Resistor 500 Ω
PTH04000W
Voltage
Regulator
1.3V
Variable Resistor 2K Ω
PTH04000W
Quantum Encryption System -Synchronization
1.3V Surface VIA
The Board Design



The board has 4 layers of power/GND, 3 different
layers in each part of the board, a surface for the
FPGA control lines, and on top the transmission lines.
The two parts of the board are separated completely
from one to another.
the two GND surfaces is connected to one another in
the power input connector of the board, that way we
will decrease the GND noise.
The data pulse is being converted to 3.3V levels before
entering the 3.3V side surface.
The FPGA I/O lines are 3.3V LVTTL and can control
all the component in our board (including the ones that
work with 5V).
Quantum Encryption System -Synchronization
Board surfaces

The board has a total of 7 layers, two of them are divided to two parts for
different voltage levels so we have a total of 9 different surfaces.
 Each part contains the same layers but connects to the right layers with
via holes..
 The two parts of the board are suppurated completely from one to
another.
 The surfaces are:
– 5V VCC surface
– 3V VTT surface
– 5V GND surface
– 3.3V VCC surface
– 1.3V VTT surface
– 3.3V GND surface
– Transmission Lines on top surface
– Control lines 1
– Control lines 2
Quantum Encryption System -Synchronization
Board surfaces From HyperLynx
Quantum Encryption System -Synchronization
Board surfaces
Quantum Encryption System -Synchronization
The Board Design
Quantum Encryption System -Synchronization
The Board Design
Quantum Encryption System -Synchronization
The Board Design
Quantum Encryption System -Synchronization
The Board Design - consideration



Every Component Voltage input is protected and filtered
with two capacitors to stable the input voltage and
protecting it.
Technological matching was made so every component
will connect correctly to the one before him and the one
after him, in special cases a pull-up resistor or a voltage
level converter was inserted.
Power and currents levels was calculated according to the
components specifications.
– The total power that was calculate id: 5.54W
– The total current needed from the power supply is: 1.5A (min)
Quantum Encryption System -Synchronization
The Board Design –
High Speed consideration

In order to eliminate the high frequency noise we used
transmission lines on all the hi speed components.
 The transmission lines width were determined to be
200μm because of 2 reasons:
1.
2.

The line will be about 50Ω Z0 impedance, and the connectivity to the
components will be possible.
The line should be small enough to be able to connect to the components
legs.
The dielectric surface around the transmission line
were chosen to be 115μm also to make sure the Z0 is
about 50Ω (received the results from the HyperLynx)
Quantum Encryption System -Synchronization
The Board Design –
High Speed consideration

All the transmission lines needed to be shorter the a
quarter of a wave length (L<λ/4) .
 It was decided that the Tr of the board will be 0.5nSec at
the worst case. All of the chosen ECL fast components
fulfilling this decision and even much faster.
 Tr = 0.5nSec, BW = 1/(Tr*π) => BW = 640MHz
λ=T*C = 1.57*10^-9 * 3*10^10 ~ 47cm
 To insure that L<< λ we designed the board to have
transmission line the size if L = λ /10 = 4.7cm
Quantum Encryption System -Synchronization
The Board Design –
High Speed consideration
In order to make our board smaller than 4.7cm we
inserted all the hi speed components and the
transmission lines ware inserted to a
32 mm X 22mm (approximately) “Metal Cage” .
The Cage was created by inserting VIA’s to the ground
around the wanted area,
we inserted a via hole every 3.8mm so the distance
between 2 holes will be far smaller then λ .
Inside every cage the wave length requirement is met.
Quantum Encryption System -Synchronization
The Board Design
ECL ZOOM –
Transmission lines
~3.8mm
Quantum Encryption System -Synchronization
The Board Design –
High Speed Hyperlink Simulation

In order to see the Transmission lines behavior in our
high speed system we simulated the high speed part of
the board.
 We simulated each transmission line separately and
seen the change from the input of the line to the output
of the line.
 The result show that because we selected our high
speed part to be smaller than the wave length and all
our transmission lines are short, we don’t have a
significant change in our pulse and we can assume the
there is no loss or change in our data.
Quantum Encryption System -Synchronization
The Board Design – High Speed Hyperlink Simulation
Transmission line simulation example
Quantum Encryption System -Synchronization
The Board Design – High Speed Hyperlink Simulation
Transmission line simulation example
Vin *
Quantum Encryption System -Synchronization
The Board Design – High Speed Hyperlink Simulation
Transmission line simulation example
Input to transmission line
Output from transmission line
1562.5 PS
* Oscillator simulation 640MHz
Quantum Encryption System -Synchronization
The Board Design – High Speed Hyperlink Simulation
Transmission line simulation example
Input to transmission line
Output from transmission line
* Edge simulation
Quantum Encryption System -Synchronization
Synchronizer Board BOM
Quantum Encryption System -Synchronization
Synchronizer Board BOM
Quantum Encryption System -Synchronization
Logic design of the FPGA software
Sync_start
Count = 0
Delay = 0
Mix_enable = ‘1’
Count = 0
Delay = Delay + 1nSec
NO
YES
IF
Valid_photon
YES
Count = Count + 1
IF
Count = N
Accurate Delay in
10pSec
Next page
Quantum Encryption System -Synchronization
NO
Placing the photon in the first 10pSec of the window
Count=0
Pulse_start=0
Count = 0
Pulse_start=1
Delay = Delay + 10pSec
Delay = Delay – 10pSec
Count = Count + 1
NO
IF
Valid_photon
YES
Count = Count + 1
NO
YES
IF
Count = N
NO
NO
IF
Count = N
YES
IF
Pulse_start=1
YES
 We
can set N - the number of iteration according to probability
statistics for increasing the correctness of the system.
Sync_Delay = Delay
Mix_enable = ‘0'
Sync_Delay
Sync_END
Quantum Encryption System -Synchronization
VHDL Implementation
sync_lib
Clock_gen
U_2
sync_lib
Photon_gen
U_3
clk
Photon
clk
Photon
rst
push_button1
Photon
rst
push_button1
Valid_Photon1
Valid_Photon2
Valid_Photon1
Valid_Photon2
START_COMP
START_COMP
sync_lib
Sync_main
U_0
LED1
LED11
LED14
LED15
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
DDL : (9:0)
DDL_TTL1_AE
DDL_TTL2_AE
DDL_TTL3_AE
DDL_Strecher_AE
DDL_ECL1_LEN
DDL_ECL2_LEN
DDL_MONO1_LEN
DDL_MONO2_LEN
Strecher_EN
Splitter2_EN
Splitter1_EN
DDL_ECL1_EN
DDL_ECL2_EN
DDL_MONO1_EN
DDL_MONO2_EN
Sync_End
LED1
LED11
LED14
LED15
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
DDL : (9:0)
DDL_TTL1_AE
DDL_TTL2_AE
DDL_TTL3_AE
DDL_Strecher_AE
DDL_ECL1_LEN
DDL_ECL2_LEN
DDL_MONO1_LEN
DDL_MONO2_LEN
Strecher_EN
Splitter2_EN
Splitter1_EN
DDL_ECL1_EN
DDL_ECL2_EN
DDL_MONO1_EN
DDL_MONO2_EN
Sync_End
Quantum Encryption System -Synchronization
sync_lib
Sync_main_tester
U_1
VHDL Implementation
Quantum Encryption System -Synchronization
VHDL Implementation - INIT
Idle
rst
clk
Idle
rst = '0'
Idle
clk'EVENT AND clk = '1'
push_button1='1' OR START_COMP='1'
Initial_v alues
Clock_counter = 3 -- 20nsec
Sav e_v alue
Clock_counter = 21 -- 20nsec
18 -- 50nsec
Clock_counter = 12 -- 20nsec
1
2
3
Mono_3nSec
9 -- 50nsec
Strecher_35nSec
27 -- 50nsec
End_Init
Sync_End = '1'
End_Sync
Quantum Encryption System -Synchronization
– Long Delay
VHDL Implementation
clk
clk'EVENT AND clk = '1'
Idle
Idle
rst
rst = '0'
Idle
Init_End = '1'
Photon = '1' AND Init_End = '1' AND
Long_Delay_End_int ='0' AND Error_delay ='0'
Check_Photon
Valid_Photon1 = '1' AND
Valid_Photon2 = '1'
Clock_counter >= 60 -- 0.6uSec
The photon is not in the window
The photon is in the window
Not_Valid_counter
Valid_counter
No_Photon_counter >= 5
Valid_Photon_counter >= 5
Need to Delay the signal
Change_Delay
1
2
DDL_long1 >= "0011111111"
The first DDL is in Max
Increase the secound DDL
End_Long
DDL_long1 < "0011111111"
Increase the first DDL
Inc_TTL2
Inc_TTL1
New _delay2
New _delay1
DDL_long2 >= "0011111111"
Error
Clock_counter >=3 -- 20nsec
Clock_counter >=3 -- 20nsec
Sav e_delay
Quantum Encryption System -Synchronization
– Short Delay CH1
VHDL Implementation
Idle
clk
clk'EVENT AND clk = '1'
Idle
rst
rst = '0'
Long_Delay_End = '1'
Idle
Photon = '1' AND Long_Delay_End = '1' AND Short_Delay1_End_int <= '0'
Check_Photon
Clock_counter >= 60 -- 0.6uSec
Valid_Photon1 = '1'
The photon is not in the window
The photon is in the window
Not_Valid_counter
Valid_counter
No_Photon_counter >= 5
Valid_Photon_counter >= 5 AND wanted_position1 /= '1'
Need to change the Delay
The photon is in the beginning of the window
Need to change the Delay
Valid_Photon_counter >= 5 AND wanted_position1 = '1'
The photon is in the beginning of the window
More_Delay
Less_Delay
Write_delay
Clock_counter >= 3 -- 20nsec
Sav e_delay
Quantum Encryption System -Synchronization
End_Short1
– Short Delay CH2
VHDL Implementation
Idle
clk
clk'EVENT AND clk = '1'
Idle
Short_Delay1_End='1'
rst
rst = '0'
Idle
Photon = '1' AND Short_Delay1_End='1' AND Sync_End_int <= '0'
Check_Photon
Clock_counter >= 60 -- 0.6uSec
Valid_Photon2 = '1'
The photon is not in the window
The photon is in the window
Not_Valid_counter
Valid_counter
Valid_Photon_counter >= 5 AND wanted_position2 /= '1'
No_Photon_counter >= 5
Need to change the Delay
Need to change the Delay
The photon is in the beginning of the window
Valid_Photon_counter >= 5 AND wanted_position2 = '1'
The photon is in the beginning of the window
Less_Delay
More_Delay
Write_delay
Clock_counter >= 3 -- 20nsec
Sav e_delay
Quantum Encryption System -Synchronization
End_Short2
VHDL design verification – Init block
•
•
•
Initializing all DDL to minimum delay (at 60-120 nSec).
Initializing the DDL stretcher to 35nSec (at 160-220 nSec).
Initializing the DDL mono to 3nSec (at 250-320 nSec).
Quantum Encryption System -Synchronization
VHDL design verification – Long delay
The long delay block finishes his process when the photon is inside
the window (5 times in a row) the window is 3nSec and the next
figure shows the long delay finish state.
Quantum Encryption System -Synchronization
VHDL design verification – Short delay channel 1
The short delay channel 1 start his process after the long delay finished working => the photon is
inside the window. As shown in the next figure the process finishes his work when the
wanted_delay1 is equal to the total_delay1 => the photon is in the beginning of the window.
Quantum Encryption System -Synchronization
VHDL design verification – Short delay channel 2
The short delay channel 2 start his process after the short delay channel 1 finished working => the photon in
channel 1 is inside the beginning of the window. As shown in the next figure the process finishes his work
when the wanted_delay2 is equal to the total_delay2 => the photon is in the beginning of the window. The
system can sync the 2 channels to a different delay so each of them will arrive at the beginning of the window.
At the end of this process the system send a signal to the computer (sync_end) indicates the end of the
synchronization and Enables the ADD function in the receiver.
Quantum Encryption System -Synchronization
VHDL design verification – Error reporting
When the system cannot insert the photon inside the window or there is a problem in the sync – all the red
LEDs on the FPGA board will light and the process will stop with an error signal.
Quantum Encryption System -Synchronization
Added value



The project gave us a glimpse of how a big project in the industry
might take place. We had to take under consideration all the time
that we are part of a big project and have to make our system
compatible with the other system.
The project gave us experience in board design, taught us some of
the designing aspects we need in order to make a good board. Also
gave us some experience working with design and simulation tools
such as Orcad and HyperLynx
The project gave us experience in FPGA design and digital way of
designing a system that needs to control other system digitally
(with the FPGA board)
Quantum Encryption System -Synchronization
Improving point & future continuing options



The project was mostly theoretical ,by experimenting the
components in an early stage we could have seen their actual
behavior and be sure of our design, in order to make these
experiments possible, a generic board needs to be designed and
manufactured. The board will supply the components working
needs and samples has to be ordered in an early stage.
Part of the project was to design the layer properties of the board,
and to give instructions to the editor. A meeting with an editor and
consulting him would make our instructions better, and more
focused.
For continuing the project a board needs to be manufactured and
the VHDL design needs to be tested on the real system, in order to
make sure that the design fully functions.
Quantum Encryption System -Synchronization