* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Download Retine artificielle
Three-phase electric power wikipedia , lookup
Electrical ballast wikipedia , lookup
Quantization (signal processing) wikipedia , lookup
Control theory wikipedia , lookup
Flip-flop (electronics) wikipedia , lookup
Power inverter wikipedia , lookup
Electrical substation wikipedia , lookup
Time-to-digital converter wikipedia , lookup
History of electric power transmission wikipedia , lookup
Pulse-width modulation wikipedia , lookup
Current source wikipedia , lookup
Variable-frequency drive wikipedia , lookup
Distribution management system wikipedia , lookup
Immunity-aware programming wikipedia , lookup
Surge protector wikipedia , lookup
Resistive opto-isolator wikipedia , lookup
Alternating current wikipedia , lookup
Control system wikipedia , lookup
Stray voltage wikipedia , lookup
Voltage optimisation wikipedia , lookup
Voltage regulator wikipedia , lookup
Power electronics wikipedia , lookup
Buck converter wikipedia , lookup
Integrating ADC wikipedia , lookup
Schmitt trigger wikipedia , lookup
Mains electricity wikipedia , lookup
Switched-mode power supply wikipedia , lookup
~ GADC ~ Multipurpose 10bit ADC Denis Fougeron, Fabrice Gensolen, Mohsine Menouni, Laurent Perrot CPPM - CNRS - Université de la méditerranée - Marseille ATLAS pixel chip upgrade meeting – FEI4_A design March 3rd, 2010 1 Outline Purpose and specifications General architecture I/Os interface Final layout Simulation results Summary of performances 2 Purpose and specifications The bloc GADC (General Analog to Digital Converter) is a general purpose 10 bits ADC used to digitize different analog voltages of the FEI4 chip. The input voltages of the GADC will be: - the TEMPSENS bloc output voltage to monitor the temperature of the chip, - an image of the power supplies, - the detector leakage current driven by the FEND bloc. Initial specifications were : Specification 3 Value Resolution 10 bits Conversion time ~ 1 us Input voltage range to convert 0 to Vref (with Vref ≥ 900 mV) General architecture Input voltages Analog 8to1 mux GADCsel<2:0> Selected voltage GADCcompIbias GADCvref Comparator DAC SAR Control Logic GADCstart GADCout <9:0> 4 GADCclk GADCstatus GADCdisable Analog I/Os interface Pin Name Output TO INOUT? Description Specs if any FEND Mirrors 5X the detector DC leakage current. Vtemp TEMPSENS Voltage for temperature measurement GADCvref Voltage reference Input voltage reference for the DAC 900 mV GADCcompIbias FEI4_A_ DACS Bias current for the comparator 10 uA IleakIn 5 Input From Comments and requests I/V conversion of this detector leakage current via a 100kΩ resistor Digital I/Os interface Pin Name GADCsel GADCstart Input From 6 Description Specs if any Comments and requests Input voltage selection via the analog Mux 3 bits selection for the 8 to 1 analog multiplexor Control When “high”: ask for a conversion The conversion starts only when GADCstart is “high” Control Control Control “high” when the conversion is on-going, “low” when it is done. 40 MHz clock for control logic CLKGEN GADCout GADCdisable INOUT? Control GADCstatus GADCclk Output TO 10 bits GADC output value Active “high”. GADC bloc is “ON” when GADCdisable is “low” and “OFF” when “high”. Internal GADC clock is 1.25 MHz (it is generated dividing the 40 MHz input clock by 32) Final layout SAR DAC COMP AREA = 434 x 228 um2 7 Typical and worse case simulation results Linearity error in LSB* vs. Input voltage Error (LSB) 4 TT 27°C SS 40°C 3 2 1 0 0 200 400 600 800 VthIn (mV) * 8 linearity error = GADC_output_code - Ideal_output_code 1000 1200 1400 Quantization error of the DAC DAC10b's quantization error Error (V) 5,00E-04 4,00E-04 ¼ LSB = 0.366 mV 3,00E-04 2,00E-04 1,00E-04 0,00E+00 0 128 256 384 512 640 768 896 1024 -1,00E-04 -2,00E-04 -3,00E-04 Corner TT T=25°C Corner SS T=40°C Corner FF T=-40°C -4,00E-04 9 Summary of performances Parameter 10 Value Resolution 10 bit Conversion time 10.4 us (Fclock= 1.25 MHz = 40/32) Input voltage range to convert 0 to 1.5 V (Vref = 1.5V here) Linearity error 1 LSB Power consumption (when ON) 120 uA @ 1.5 V DAC output voltage mismatch < 800 uV p-p Area 434 x 228 = 100 000 um²