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Nanoimprint Lithography for
Hybrid Plastic Electronics
Michael C. McAlpine, Robin S. Friedman, and Charles M. Lieber
Harvard UniVersity
Chieh Chang
EE 235 – Presentation I
March 20, 2007
Introduction
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Efficient fabrication of integrated circuits
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Photolithography
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Reliable
High-throughput processing
Feature resolution: 100nm
Complex and costly fabrication equipment
Alternatives of nanoscale patterning
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Electron beam
Scanning probe
Extreme ultraviolet
Dip pen
Nanoimprint
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Scalable, parallel, cost-effective
Feature resolution: sub-25nm
Nanoimprint
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Thermoplastic NIL
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Heating process limits the application to flexible plastic
substract.
NIL @ room temperature on plastic substrate with
nanometer scale resolution
Combined with inorganic semiconductor nanowires to
generate nanoscale transistor
Schematic
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Plastic substrates coated
with SiO2 and Lift-off
resistor (LOR) were
imprinted using a Si/SiO2
stamp.
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The NIL pattern was
transferred to the
substrate in successive
RIE
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Metal deposition, and liftoff steps
Key Issues
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The deposition of a resistor for room
temperature imprinting
Reproducibly imprinted at room temperature
 Cleanly removed from the inorganic stamp
without antiadhesion agents
 Etched at controlled rates by RIE
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The SiO2
Improve metal adhesion
 Not affect flexibility
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Results
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(A) Optical image of S-D array
and interconnect wires; scale
bar, 100 um
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(B) Optical image of 200 nm SD lines and 1 um interconnect
lines; scale bar, 25 um
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(C) SEM image of S-D array of
2um pitch, and 500nm gap;
scale bar ,20 um
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(Inset) SEM image of 200 nm
width channel lines; scale bar,
200nm
Results
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(D) Optical image of patterned
Mylar substrate
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(E) Optical image of
hierarchically patterned arrays
of gate electrodes; scale bar,
100 um
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(Inset) SEM image of a gate
array block, where corner
squares are alignment marks;
scale bar, 5 um
Bottom-up + Top-down
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A solution of p-type
SiNWs were flowaligned in a direction
perpendicular to the
gate electrode arrays
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FET: 20 nm p-SiNW
crossing an imprintpatterned metal gate
Measurement
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Current versus S-D voltage
(I-Vsd) data recorded on a
typical crossed-junction pSiNW FET.
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The S-D contacts are ohmic.
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As Vg is increased, the
slopes of the individual I-Vsd
curves decrease as expected
for a p-type FET.
Measurement
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Plots of the conductance versus
Vg. Vsd is 1V
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The transconductance of this
device is 750 nS
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This value is within a factor of 2 of
that recently reported for
core/shell nanowire devices that
were fabricated on conventional
singlecrystal Si/SiO2 substrates.
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The device performance could be
improved by decreasing the dopant
concentration and/or minimizing
trap states in the dielectric
Summary
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This paper has demonstrated NIL of nanometer through
millimeter-scale features on flexible plastic substrates over large
areas at room temperature.
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The ambient temperature NIL patterning technique has been
shown to produce uniform features in a parallel and repeatable
manner
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Moreover, NIL has been combined with bottom up assembly to
fabricate SiNW FETs on flexible plastic substrates with device
performances similar to nanowire FETs fabricated on conventional
single-crystal substrates.
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The development of simple and reproducible high-resolution
patterning of plastics using NIL combined with the versatile
function of nanowire building blocks could open up exciting
opportunities over many length scales for plastic electronics and
photonics.