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Digital to Analogue Conversion Analogue Digital Conversion Analog and digital data were briefly mentioned at the start A digital signal is an approximation of an analog one Levels of signal are sampled and converted to a discrete bit pattern. Digital signal processing is used, for example, to enhance and compress images, to process sounds to generate speech, etc, etc. Step (discrete) Approximation “stair-step” approximation of original signal sample level more samples give greater accuracy time hold time for sample Objectives To understand how a digital value can be converted to an analogue value To draw circuits and explain the operation of two digital to analogue converters: the binary weighted resistor network and the R-2R ladder network To draw the block diagram and explain the operation of three analogue to digital converters: flash, counter ramp and successive approximation To be able to calculate the conversion time for an analogue to digital converter To be able to explain the sampling rule To be able to describe the basic design of a sample and hold circuit and explain how it works The binary weighted resistor network Comprises of a register and resistor network Output of each bit of the register will depend on whether a 1 or a 0 is stored in that position e.g. for a 0 then 0V output for a 1 then 5V output Resistance R is inversely proportional to binary weight of each digit R MSB 2R 4-bit register LSB 4R 8R RL VL Buffering the resistor network Best solution is to follow the resistor network with a buffer amplifier Has high impedance, practically no current flows All input currents sum at S and go through Rf Vo = -IfRf R MSB LSB 4-bit register Rf I1 2R I2 If 4R I3 S I 8R I4 + Vo Vo = - If R f = -(I1 + I2 + I3 + I 4 ) Rf Digital-to-Analogue Example Calculate the output voltage for an input code word 0110 if a logic 1 is 10V and a logic 0 is 0V, and R = RF=1k I1 = I4 = 0 I2 = 10v / 2R = 10 / 2k = 5 mA I3 = 10v / 4R = 10 / 4k = 0.25 mA Vo = -If x Rf = -(0.0075) x 1000 = -7.5 volts Vo = - If Rf = -(I1 + I2 + I3 + I4) Rf The binary weighted resistor network Seldom used when more than 6 bits in the code word to illustrate the problem consider the design of an 8-bit DAC if the smallest resistor has resistance R what would be the value of the largest resistor? what would be the tolerance of the smallest resistor? Very difficult to manufacture very accurate resistors over this range The R-2R Ladder Resistor Network Has a resistor network which requires resistance values that differ 2:1 for any sized code word The principle of the network is based on Kirchhoff's current rule The current entering N must leave by way of the two resistors R1 and R2 I R2 N R1 • The R-2R Ladder Resistor Network Works on a current dividing network A I B R I1 2R 2R I1 I2 2R Resistance to right of B = 1/(1/2R + 1/2R) Resistance to right of A = R +2R/2 = 2R Current divides I1 = I/2 I2 = I/4 divides again The R-2R Ladder Resistor Network The network of resistors to the right of A have an equivalent resistance of 2R, and so the right hand resistance can be replaced by a copy of the network I I/2 2R R I/4 2R I1=I/2 bit 3 R I/8 2R I2=I/4 bit 2 2R I3=I/8 bit 1 bit 0 Bit 3 2 1 0 Current I/2 I/4 I/8 I/16 The R-2R Ladder Resistor Network R 2R 2R I/2 R 2R I/4 The state of the bits is used to switch a voltage source 2R I/8 2R I/16 Rf + Vo 4-bit register MSB Vs R LSB I Vo = -R f (b 3 I 2 + b2 I 4 + b1 I 8 + b 0 I 16) Example R I Vs 2R R 2R I/2 R 2R I/4 2R I/8 2R I/16 Rf + Vo LSB MSB 4-bit register Vo = -R f (b 3 I 2 + b2 I 4 + b1 I 8 + b 0 I 16) For the circuit shown above with I = 10 mA and Rf = 2k, calculate the output voltage V0 for an input code word 1110. Example I = 10mA Rf = 2k input code word 1110 Vo = -2000( 0.01/2 + 0.01/4 + 0.01/8 + (0 x 0.1)/8 ) = - 2000 * (0.04 + 0.02 + 0.01) / 8 = 17.5 volts Quantisation Suppose we want to use a D-A converter to generate the sawtooth waveform (graph shown on the left) The 16 possible values of the D-A converter output are called the quantisation levels The difference between two adjacent quantisation levels is termed a quantisation interval voltage voltage time ... 1111 0000 End up with stair-case waveform (graph shown on the right) 0000 0001 0010 time Quantisation Error Difference between the two waveforms is the quantisation error Maximum quantisation error is equal to half the quantisation interval One way to reduce the quantisation error (noise) is to increase the number of bits used by the D-A converter quantisation interval 111 110 bands or quanta 1001 101 1000 0111 100 0110 011 0101 0100 010 0011 0010 001 000 0001 0000 samples Quantisation Noise The voltage produced by the DA convertor can be regarded as the original signal plus noise: This is the quantisation noise. Summary We have looked at techniques for converting a digital codeword into an analogue voltage using a weighted resistor network. In particular: the binary weighted network (not suitable for large resolution D-A converters) the R-2R ladder The addition of an amplifier minimises the loading effects on the weighted network The conversion from digital to analogue involves a quantisation process that limits the resolution and introduces the quantisation noise. This quantisation error can be reduced by increasing the number of bits in the converter.