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Chapter 2:
Computer-System
Structures
Topics
Computer System Operation
 I/O Structure
 Storage Structure
 Storage Hierarchy
 Hardware Protection
 General System Architecture

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Computer-System Operation
§2.1
裝置控制器


CPU and device controllers connected through a
common bus that provides access to shared memory.
Each device controller is in charge of a specific type
of device.
disk
cpu
disk
Disk
controller
printer
Tape drives
Printer
controller
Tape-drive
controller
System bus
Memory controller
memory
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Computer-System Operation


The CPU and the device controllers can execute
concurrently, competing for memory cycles.
A memory controller synchronizes access to the
同步化
memory.
disk
cpu
disk
Disk
controller
printer
Tape drives
Printer
controller
Tape-drive
controller
System bus
Memory controller
memory
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Bootstrap
program
拔靴帶(啟動帶引程式)

When powered up or reboot, an initial
program, called bootstrap program,
initializes the system, including:
– CPU registers
– Device controllers
– Memory contents
– Load the OS and start it
The bootstrap program
locate and load the OS
kernel into memory.
Interrup
The OS starts
executing the
t as “init,”
first process, such
and waits for some event to
occur. 5
Interrupt




中斷
Hardware may trigger an interrupt at any
time by sending a signal to the CPU, usually
by way of the system bus.
Software may trigger an interrupt by
executing a special operation called a
system call.
For example: the completion of an I/O
operation, division by zero, invalid memory
access, and a request for some OS service.
Different service routines are provided for
different type of interrupts.
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Interrupt Handling
When the CPU is interrupted, it stops
what it is doing and immediately
transfers execution to a fixed location.
 The fixed location usually contains the
starting address where the service
routine for the interrupt is located.
 The interrupt service routine executes;
on completion, the CPU resumes the
interrupted computation.

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Interrupt Time Line For a Single
Process Doing Output
CPU
User
Process
executing
I/O interrupt
processing
I/O
device
Idle
transferring
I/O
request
Transfer
done
I/O
request
Transfer
done
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Common Functions of
Interrupts





Interrupts transfers control to the interrupt service
routine, generally through the interrupt vector, 中斷向量
which contains the addresses of all the service
routines.
Interrupt architecture must save the address of the
interrupted instruction for returning to normal
execution.
功能解除
Incoming interrupts are disabled while another
interrupt is being processed to prevent a lost
interrupt. 陷阱
A trap is a software-generated interrupt caused
either by an error or a user request.
An operating system is interrupt driven.
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I/O Structure
§2.2
Depending on the controller, there may
be more than one attached device.
 For example: the small computersystems interface (SCSI) controller
can have seven or more devices
attached to it.
 The device controller maintains some
local buffer storage and a set of
special-purpose registers.

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I/O Interrupts

To start an I/O operation:
– CPU loads appropriate registers within
the device controller
– Device controller then examines the
contents of these registers to determine
what action to take.
– Once the action is complete, the device
controller informs the CPU that it has
finished its operation by triggering an
interrupt.
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Device Controller
Controller
B
U
S
Character
Transmitted
Data buffer register
Control
bits
Device
|
|
|
|
|
|
|
|
Device
Control/status register
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Example Control/Status
Register
. . . . .0/1 . . . .0/1 . . . .0/1
"OPERATION
COMPLETE" flag - 1
means operation is
complete
. . . . .
"WRITE" flag1 means controller
should write a character
to the device
"READ" flag1 means controller
should read a character
from the device
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I/O Methods

Once the I/O is started, two courses of
action are possible:
Synchronous I/O
user
kernel
Asynchronous I/O
Requesting process
waiting
Requesting process
Device driver
Device driver
Interrupt handler
Interrupt handler
hardware
hardware
Data transfer
Data transfer
user
kernel
time
time
(a)
(b)
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Synchronous I/O

After I/O starts, control returns to user
program only upon I/O completion.
– Waiting for I/O may be accomplished by:
 wait
instruction idles the CPU until the next
interrupt
 wait loop
Loop:jmp Loop
– At most one I/O request is outstanding at
a time, no simultaneous I/O processing.
– Also excludes the possibility of
overlapping useful computation with I/O.
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Asynchronous I/O

After I/O starts, control returns to user
program without waiting for I/O
completion. The I/O then can continue
while other system operations occur.
– A System call (request to the operating system),
is needed to allow user to wait for I/O completion.
– In order to keep track of many I/O requests at
the same time, Device-status table contains
entry for each I/O device indicating its type,
address, and state.
– Operating system indexes into I/O device table
to determine device status and to modify table
entry to reflect the occurrence of the interrupt.
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Device-Status Table
device: card reader 1
Status: idle
Device: line printer 3
Status: busy
Device: disk unit 1
Status: idle
Request for
line printer
address:38546
Length:1372
Device disk unit 2
Status: idle
Device: disk unit 3
Status: busy
Request for
disk unit 3
Request for
disk unit 3
File: xxx
Operation: read
Address: 43046
Length: 20000
File: yyy
Operation: write
Address: 03458
Length: 500
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Input Device
Interactive systems may allow users to
type ahead.
 Interrupts may occur, signaling the
arrival of characters from the terminal,
while the device-status block indicates
that no program has requested input
from this device.
 A buffer must be provided to store the
typeahead characters until some
program wants them.

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Direct Memory Access (DMA)
Structure
Used for high-speed I/O devices able
to transmit information at close to
memory speeds.
 Device controller transfers blocks of
data from buffer storage directly to
main memory without CPU
intervention.
 Only one interrupt is generated per
block, rather than the one interrupt per
byte.

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Storage Structure


§2.3
Main memory (RAM)– only large storage
media that the CPU can access directly.
It is not possible for programs and data to
reside in main memory permanently
– Main memory is usually too small
– Main memory is a volatile storage device


Secondary storage – extension of main
memory that provides large nonvolatile
storage capacity.
Magnetic disks – provide storage of both
programs and data. Most programs are
stored on a disk until they are loaded into
memory.
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Von Neumann Machine
抓取
A typical instruction-execution cycle
will first fetch an instruction from
memory and will store it in the
instruction register. 解碼
 It is then decoded and cause operands
to be fetched from memory and stored
in some internal register.
 After the instruction on the operands
has been executed, the result may be
stored back to memory.

21
Cycle and Clock
Cycle: A basic unit of computation, one
period of a computer clock.
 Each instruction takes a number of
clock cycles.
 Clock rate: The fundamental rate in
cycles per second at which a computer
performs its most basic operations
such as adding two numbers or
transfering a value from one register to
another.

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Main Memory



§2.3.1
Main memory and the registers built into the
processor itself are the only storage that the
CPU can access directly.
To allow convenient access to I/O devices,
memory-mapped I/O set aside ranges of
memory addresses and mapped to the
device registers.
Read and writes to these memory
addresses cause the data to be transferred
to and from the device registers.
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記憶體對照
Memory-mapped I/O
Real
memory Driver moves
Physical
address
space
character to
fixed location
in the address
space
'X'
'X'
'X*
Character sent to the
bus and then to the
controller register
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Memory-mapped I/O

Appropriate for devices that have fast
response times, such as video
controllers.
– In PC, each screen location is mapped to
a memory location. Displaying text on the
screen is almost as easy as writing the
text into the appropriate memory-mapped
locations.
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Memory-mapped I/O

Also convenient for devices such as
the serial and parallel ports used to
connect modems and printers.
– CPU transfers data through these kinds
of devices by reading and writing a few
device registers, called an I/O port. 埠
– CPU writes data to the data register and
uses control register to signal the
readiness of the data
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Pseudocode for Writing X
Assume: X is in location m
Data buffer register is in location d
Control/status register is in location d+1
LOOP:
Move contents of location m to location d.
Set WRITE flag in location d+1 to 1.
Move contents of location d+1 to a CPU register.
Test the OPERATION COMPLETE flag in the register.
If flag is 0, branch to LOOP: {WRITE operation is not
complete}
.... next instruction....{WRITE operation is complete}
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Writing X Using Memory Mapped I/O
1. Moves 'X'
to location d
Physical
address
space
Location m
'X*
Real
memory
Data
Bus
Data buffer
register
Location d
'X*
Location d+1
'X*
3. 'X' goes
to the bus
2.Set
"WRITE"
flag to 1
6.Test "OPERATION
COMPLETE" flag
4. 'X' goes
to the data
buffer register
5. 'X'
goes to
the
device
Device
Control/Status
register
...0/1...0/1..
...0/1...0/1..
Driver sees
these flags as
part of memory
Controller
Any reference to
location d+1 is a
reference to the
control/status
register
"WRITE" flag set to 1
as a result of step 1
7. "OPERATION COMPLETE"
flag is set to 1 after 'X'
goes to the device
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Busy-waiting
The biggest drawback: the driver must
continually test a flag -- monopolizes
the CPU for status checking.
 Unacceptable when other processes
are waiting

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程式控制
Programmed I/O (PIO)

The CPU uses polling to watch the
control bit, constantly looping to see
whether the device is ready
Interrupt中斷驅動
driven I/O

The CPU does not poll the control bit,
but instead receives an interrupt when
the device is ready for the next byte.
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Activities with programmed I/O
Controller
writes character
t2
t1
Time
Process requests
controller to write
character
CPU spends all
this time checking
the control/status
register - no
other process
makes progress
Process detects
that character has
been written
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Activities with interrupt
driven I/O
Controller
writes character
t1
t2
Time
CPU spends this
Controller interrupts
Process requests time working on
CPU, indicating that
controller to write another process
character has been
character
written
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Interrupt Line
A CPU can detect a controller interrupt
through an interrupt line
 Normally the CPU tests the interrupt
line during the instruction cycle

CPU
Controller
interrupt line
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Magnetic Disks




§2.3.2
Tracks, Sectors, Cylinders.
1 Kilobyte = 1024 bytes
1 Megabyte = 10242 bytes
1 Gigabyte = 10243 bytes
Transfer rate = the rate at which data flow
between the drive and the computer.
Positioning time (random-access time) =
time to move the disk arm to the desired
cylinder (seek time) + time for the desired
sector to rotate to the disk head (rotational
latency).
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Moving-Head Disk
Mechanism
actuator
Track t
spindle
Read-write
head
Sector s
Cylinder c
platter
arm
rotation
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Storage Hierarchy

§2.4
Storage systems organized in hierarchy
according to
– Speed
– Cost
– Volatility

The design of a complete memory system
must balance all these factors: uses only as
much expensive memory as necessary,
while providing as much inexpensive,
nonvolatile memory as possible.
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Storage-Device Hierarchy
37
Caching
緩衝儲存
§2.4.1
Needed information is copied into
faster storage system – the cache–
temporarily.
 Main memory can be viewed as a fast
cache for secondary storage.
 When a piece of information is needed,
first check whether it is in the cache. If
it is, use it directly. If it is not, use info
from the main storage system and put
a copy in the cache for later usage.

38
Caching



Internal programmable registers, such as
index registers, provide a high-speed cache
for main memory.
The programmer implements the registerallocation and replacement algorithms to
decide which info to keep in registers and
which to keep in main memory.
There are also caches implemented totally
in hardware.
– Instruction cache
– Data cache
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Caching
The movement of information between
levels of a storage hierarchy may be
either explicit or implicit.
 For instance,

– data transfer from cache to CPU and
registers is usually a hardware function,
with no OS intervention.
– Transfer of data from disk to memory is
usually controlled by the OS.
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Coherency
凝聚性、一貫性


§2.4.2
In a hierarchical storage structure, the same
data may appear in different levels of the
storage system.
For example: integer A in file B is to be
incremented by 1.
– Disk –> main memory –> cache –> internal
register.

In multitasking environment, must ensure
that, if several processes wish to access A,
then each of these processes will obtain the
most recently updated value of A.
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Coherency
It is more complicated in multiprocessor
environment where a copy of A may
exist simultaneously in several CPU’s
local cache.
 Must make sure that an update to the
value of A in one cache is immediately
reflected in all other caches where A
resides – cache coherency.

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Hardware Protection
§2.5
OS sharing system resources among
several programs simultaneously may
cause processes to be adversely
affected by a bug in one program.
 OS must ensure that an incorrect (or
malicious) program cannot cause other
programs to execute incorrectly.
 If a user program fails, the hardware
will trap to the OS.

43
Dual-Mode
Operation
雙模式


§2.5.1
Sharing system resources requires
protecting the operating system and all
other programs and their data from any
malfunctioning program.
Provide hardware support to differentiate
between at least two modes of operations.
1. User mode – execution done on behalf of a user.
2. Monitor mode (also supervisor mode or system
mode) – execution done on behalf of operating
system.
44
Dual-Mode Operation


Mode bit added to computer hardware to
indicate the current mode: monitor (0) or
user (1).
When an interrupt or fault occurs
hardware switches to monitor mode.
Interrupt/fault
monitor
user
set user mode
享有特權的
Privileged instructions can be issued only in monitor mode.
45
Dual-Mode Operation

The lack of a hardware-supported
dual mode can cause serious
shortcomings in an OS.
– MS-DOS was written for Intel 8088,
which has no mode bit, and therefore
no dual mode.
– Pentium provide dual-mode operation.
As a result, NT and OS/2 provide
greater protection for the OS.
46
I/O Protection
§2.5.2
By defining I/O instructions to be
privileged instructions, users cannot
issue I/O instructions directly; they
must do it through the OS.
 Must ensure that a user program could
never gain control of the computer in
monitor mode (Ex: a user program that,
as part of its execution, stores a new
address in the interrupt vector).

47
Memory Protection


Must provide memory protection at least for
the interrupt vector and the interrupt service
routines.
In order to have memory protection, add two
registers that determine the range of legal
addresses a program may access:
– base register – holds the smallest legal physical
memory address.
– Limit register – contains the size of the range

Memory outside the defined range is
protected.
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A Base And A limit Register Define A
Logical Address Space
0
monitor
256000
Job 1
300040
300040
Job 2
Base register
120900
420940
Job 3
Limit register
880000
Job 4
1024000
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Protection Hardware
Base limit
base
address
CPU
yes
≧
no
＜
yes
no
Trap to operating system
Monitor – addressing error


memory
When executing in monitor mode, the
operating system has unrestricted
access to both monitor and user’s
memory.
The load instructions for the base and
limit registers are privileged instructions.50
CPU Protection

§2.5.4
Timer – Prevent a user program form getting
stuck in an infinite loop, the computer will be
interrupted after specified period to ensure
operating system maintains control.
– Timer is decremented every clock tick.
– When timer reaches the value 0, an interrupt
occurs.


Timer commonly used to implement time
sharing by calculating the time slice before
each context switch (see Chapter 4).
Time also used to compute the current time.
51
General-System Architecture
§2.6


Given that the I/O instructions are privileged,
how does the user program perform I/O?
System call – the method used by a process
to request action by the operating system.
– Usually takes the form of a trap to a specific
location in the interrupt vector.
– Control passes through the interrupt vector to a
service routine in the OS, and the mode bit is set
to monitor mode.
– The monitor verifies that the parameters are
correct and legal, executes the request, and
returns control to the instruction following the
system call.
52
Use of A System Call to
Perform I/O
Case n
Trap to
monitor
read
Resident
monitor
Perform I/O
Return
To user
System call n
User
program
53