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Computer-System Architecture
Transfer is done one WORD at a time . For each transfer of word
(32 Bits in case of Win32), there is a contention for System Bus because
More than one devices might be requiring the transfer.
Computer-System Operation
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I/O devices and the CPU can execute
concurrently.
Each device controller is in charge of a particular
device type.
Each device controller has a local buffer.
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Buffer is a memory space for storing temp incoming or
outgoing data.
CPU moves data from/to main memory to/from
local buffers
I/O is from the device to local buffer of controller.
Device controller informs CPU that it has finished
its operation by causing an interrupt.
What is an Interrupt?
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An interrupt is an exception condition in a
computer system caused by an event external to
the CPU.
Used in I/O operation by device interface
(controller) to notify the CPU that it has
completed an I/O operation.
Device interface sends a signal to CPU via an
interrupt request line (or System Bus)
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Simply the device controller sets a bit up telling CPU
that it needs to be serviced.
This signal remains active till the time CPU
handles it or device controller removes it.
Interrupts are also called EVENTS in event driven programming / OS
How CPU reacts to an Interrupt?
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CPU checks periodically to determine if an
interrupt signal is pending.
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Check is done after the end of each
instruction
When CPU detects an interrupt it saves
the current program (process) state in
RAM, handles the interrupt and then gets
back to execution of the program.
Common Functions of Interrupts
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Interrupt transfers control to the interrupt service routine
(ISR) generally, through the interrupt vector, which
contains the addresses of all the service routines.
Interrupt architecture must save the address of the
interrupted instruction.
A trap is a software-generated interrupt caused either by
an error or a user request.
An operating system is interrupt driven.
Interrupt Types
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OS determines which type of interrupt has
occurred:
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Polling
 Queries
the device controllers to determine which
device caused an interrupt.
 Goes to the memory location where the interrupt
handler or Interrupt Service Routine (ISR) is stored
and executes that code.

vectored interrupt system (more efficient)
 Device
identifies itself when it generates an
interrupt.
 Sends the vector (pointer) to tell its ISR location
Simplified view of interrupt Processing 1
Vector Table:
12,IRQ 1 : ISR Location 100
…
5432, IRQ 7 : ISR Location 550
Area reserved to store CPU Status
PC:
AX:
BX:
etc.
CPU
PC: 12321
550
AX: 100
BX: 200
Device controller
For Sound Card Interrupts
IRQ 7
Unique No. For Card: 5432
e.g More data for MP3
ISR for Sound Card
(Might be some routine written by OS
Or a programmer like You! )
Program Running before Interrupt Occurred
A=100
B=200
C= ???
Simplified view of interrupt Processing 2
Vector Table:
12,IRQ 1 : ISR Location 100
…
5432, IRQ 7 : ISR Location 550
Area reserved to store CPU Status
PC:12321
AX: 100
BX: 200
etc.
CPU
PC: 4544
550
AX: 45445
BX: 2004564
Device controller
For Sound Card Interrupts
IRQ 7
Unique No. For Card: 5432
e.g More data for MP3
ISR for Sound Card
(Might be some routine written by OS
Or a programmer like You! )
Program Running before Interrupt Occurred
A=100
B=200
C= ???
Simplified view of interrupt Processing 3
Vector Table:
12,IRQ 1 : ISR Location 100
…
5432, IRQ 7 : ISR Location 550
Area reserved to store CPU Status
PC:
AX:
BX:
etc.
CPU
PC: 12321
550
AX: 100
BX: 200
ISR for Sound Card
(Might be some routine written by OS
Or a programmer like You! )
Program Running before Interrupt Occurred
A=100
B=200
C= ???
Interrupt Priorities
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Several interrupts may be
found pending when CPU
checks for interrupts at the end
of each instruction.
Priorities may be assigned to
device interfaces to determine
in which order the interrupt of
that particular device be
entertained.
Higher priorities (0,1) are
entertained first and lower (e.g
11,12) would be entertained if
no higher priority interrupt
exists.
To disable interrupts increase
the CPU priority to highest.
Summary
If a device interface needs servicing, it
sends an interrupt signal on the bus to
CPU and holds the signal until it is
serviced.
 The CPU periodically checks for interrupts,
typically at the end of each instruction. If it
detects an interrupts, it checks for its
priority. Would entertain only if the interrupt
priority is higher than that of CPU.
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Summary … cont
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When the CPU detects an interrupt signal, it
saves its (CPU) state and determines the device
interface which caused the interrupt.
To service the interrupt the ISR (a program in
RAM) relevant to that interrupt is executed.
If several interrupts are pending then one with
highest priority is serviced.
When interrupt handler (ISR) finishes its
execution, previous state of CPU and its
software which was executing before the
interrupt occurred are restored and program
continues its operation as if nothing happened!
I/O Structure
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Whenever I/O operation is required from a
device its registers are filled with
appropriate information by the CPU.
I/O Structure
Two methods for I/O Handling
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After I/O starts, control returns to user program only upon
I/O completion (Synchronous).
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Wait instruction idles the CPU until the next interrupt
Wait loop (contention for memory access).
At most one I/O request is outstanding at a time, no simultaneous I/O
processing.
After I/O starts, control returns to user program without
waiting for I/O completion (Asynchronous).
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System call – request to the operating system to allow user to wait
for I/O completion.
Device-status table contains entry for each I/O device indicating its
type, address, and state.
Operating system indexes into I/O device table to determine device
status and to modify table entry to include interrupt.
Two I/O Methods
Synchronous
Asynchronous
Device-Status Table
Direct Memory Access Structure
Used for high-speed I/O devices able to
transmit information at close to memory
speeds.
 Device controller transfers blocks of data
from buffer storage directly to main
memory without CPU intervention.
 Only on interrupt is generated per block,
rather than the one interrupt per byte.
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Chapter 2: Computer-System
Structures
Computer System Operation
 I/O Structure
 Storage Structure
 Storage Hierarchy
 Hardware Protection
 General System Architecture
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Moving-Head Disk Mechanism
Storage Hierarchy
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Storage systems organized in hierarchy.
Speed
 Cost
 Volatility
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Caching – copying information into faster
storage system; main memory can be
viewed as a last cache for secondary
storage.
Storage-Device Hierarchy
Caching
Use of high-speed memory to hold
recently-accessed data.
 Requires a cache management policy.
 Caching introduces another level in
storage hierarchy. This requires data that
is simultaneously stored in more than one
level to be consistent.
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Migration of A From Disk to
Register
Hardware Protection
Dual-Mode Operation
 I/O Protection
 Memory Protection
 CPU Protection
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Why Hardware Protection
Operating systems share system resources
among several programs. This causes
convenience as well as problems
 If memory is not protected then a program
may change the contents of some other
program in memory causing data
consistency problem.
 MS-DOS had no such protection. But latest
OS are all using protection mechanism.
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Dual-Mode Operation
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Sharing system resources requires operating
system to ensure that an incorrect program
cannot cause other programs to execute
incorrectly.
Provide hardware support to differentiate
between at least two modes of operations.
1.
2.
User mode – execution done on behalf of a user.
Monitor mode (also kernel mode or system mode) –
execution done on behalf of operating system.
When system is loading OS it is in Monitor
Mode.
Dual-Mode Operation (Cont.)
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Mode bit added to computer hardware to indicate
the current mode: monitor (0) or user (1).
When an interrupt or fault occurs hardware
switches to monitor mode.
Interrupt/fault
monitor
user
set user mode
Privileged instructions can be issued only in monitor mode.
I/O Protection
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All I/O instructions are privileged
instructions.
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Not in older OS like MS-DOS
 OutPort(0x378,
0xFF) sets all bits of Printer port to
High, Not allowed in Windows 2000/XP in user
mode.
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Must ensure that a user program could
never gain control of the computer in
monitor mode (i.e., a user program that, as
part of its execution, stores a new address
in the interrupt vector).
Memory Protection
Must provide memory protection at least
for the interrupt vector and the interrupt
service routines.
 In order to have memory protection, add
two registers that determine the range of
legal addresses a program may access:
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Base register – holds the smallest legal
physical memory address.
 Limit register – contains the size of the range
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Memory outside the defined range is
protected.
Use of A Base and Limit
Register
Hardware Address Protection
Hardware Protection
When executing in monitor mode, the
operating system has unrestricted access
to both monitor and user’s memory.
 The load instructions for the base and limit
registers are privileged instructions.
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CPU Protection
Can you guess how does Windows
determine that a certain program is stuck
and is not responding?
 When a program is not responding it
means that it might be stuck in an endless
loop.
 Operating system determines this by se of
a TIMER.
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CPU Protection
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Timer – interrupts computer after specified
period to ensure operating system maintains
control.
Timer is decremented every clock tick.
 When timer reaches the value 0, an interrupt
occurs.
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Timer commonly used to implement time
sharing. (Divide time between processes or
users)
Time also used to compute the current time.
Load-timer is a privileged instruction.
Network Structure
Local Area Networks (LAN)
 Wide Area Networks (WAN)
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Do it your self. 
Local Area Network Structure
Wide Area Network Structure
End of Chapter 2
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