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A DC
C-Cou
upled Negati
N
ve Indductancce Cirrcuit w
with
Integrrated B
Bias
Varun S. Kshatri, John
n M. C. Covin
ngton III, Josshua W. Shehhan, Thomas P
P. Weldon, annd Ryan S. Addams
Departm
ment of Electriical and Compputer Engineeriing
University
U
of North Carolina aat Charlotte
Charllotte, NC, USA
A
[email protected]
Abstract—Negative inductancce circuits offerr the potential for
f
increased bandwid
dth in a variety
y of applicationss such as artificcial
uctors and metamaterials
m
with negative
maagnetic condu
perrmeability. To address
a
such ap
pplications, a CMOS
C
dc-couplled
neggative inductan
nce circuit wiith integrated bias circuits is
preesented. The dc-coupled inpu
ut is tailored to operate at low
volttages and accom
mmodate applications having an inductive lo
oad
in sseries with a lo
ow resistance. An
A integrated bias circuit is ussed
to aallow operation
n with a singlee power supply and to elimina
ate
thee need for a seeparate input bias.
b
In addition, the parasiitic
pacitance of th
he CMOS tra
ansistors in th
he basic negative
cap
imp
pedance inverteer is used to seet the negative inductance of the
t
oveerall circuit. Results are presented that show a negative
ind
ductance of -110
0 nH in a 0.5 miicron CMOS prrocess.
Keywords—neg
gative inductance; negative im
mpedance invertter;
CM
MOS; integrated circuit
I.
INTR
RODUCTION
The potential for increased
d bandwidth haas motivated the
t
invvestigation of negative
n
inducctance circuits for a number of
new
w applications. In artificial magnetic cond
ductors, negatiive
indductors are ussed to mitigaate natural ressonances of the
t
inhherently narrow
wband periodicc grid of metaallic patches th
hat
com
mprise these devices
d
[1], [2
2]. In metamaaterials, negatiive
indductors are used in place of
o capacitors to eliminate the
t
inhherent narrowb
band resonances of a claassical split-riing
resonator while enabling
e
broadb
band negative permeability [3
3][5]. In such app
plications, the negative indu
uctor results in
n a
nonn-Foster circu
uit that is no
ot constrained
d by the Fosster
reaactance theorem
m [6].
To serve such
h applications, a dc-coupled CMOS negatiive
indductance with integrated
i
bias circuits is pro
oposed. Althou
ugh
neggative inductaance circuits commonly employ bipo
olar
trannsistors, a CMOS impllementation provides bro
oad
com
mpatability wiith common system-on-a-ch
s
hip processes. A
moodified Linvill circuit is chossen, using a 0.5 micron CMO
OS
proocess [7]-[9]. The
T proposed dc-coupled
d
neg
gative inductan
nce
circcuit is designed
d to cancel or neutralize
n
an external
e
ground
ded
possitive inductivee load in seriess with a low reesistance. This dc
couupling provides circuit bias without
w
need for an addition
nal
extternal bias pow
wer supply. The
T proposed CMOS negatiive
indductor design consists of a Negative Imp
pedance Inverrter
(NIII) comprised of a pair of crross-coupled CMOS
C
transisto
ors
This material is based
b
upon work supported
s
by the National
N
Science
Fouundation under Graant No. ECCS-110
01939.
that invverts the impeddance of a loadd reactance. In addition, the
circuit uses the parassitic capacitancce of the transsistors as the
load cap
apacitance that is converted too a negative indductance.
In the next sectiion, the analyysis of the baasic negative
inductaance circuit is first presenteed, including the expected
parasitiic capacitance resulting duee to the CMOS
S transistors.
The suubsequent secttion describess the detailed design and
layout of the proposeed circuit, andd the final secttion provides
simulattion results tthat demonstrrate performaance of the
proposeed negative indductance circuiit with integrateed bias.
II.
PRO
OPOSED CIRCUIIT AND ANALYS
SIS
Thee negative induuctance circuit is shown in Fiig. 1 and is a
CMOS implementation based on a form of Linnvill negative
impedaance inverter [7], [8]. In thhis circuit, thhe input port
impedaance Zin is a fu
function of thee load impedannce ZL, as in
prior bbipolar transisstor implemenntations. In tthe topology
shown, transistors M
M1 and M2 proovide feedbackk to the input
Zin, whhere resistors R1 and R2 estabblish a scaling ffactor for the
inversioon of the load iimpednce ZL.
Fig. 1. Basic Negativee Impedance Inveerter (NII) circuitt for analysis
purpooses.
Fig. 2. Schem
matic of the proposed negative ind
ductor circuit for
annalysis purposes.
To find the in
nput impedancce Zin for the circuit in Fig. 1,
firsst consider inpu
ut current ii:
,
(1)
whhere i1 is the drain
d
current of
o transistor M2,
M and g2 is the
t
trannsconductance of transistor M2. Since v1 = i1R1
iiR1,
subbstituting for v1 in (1) and rearrranging yieldss
.
(2)
Next, solve fo
or vL in terms of
o vi. To beg
gin, vL = iLZL and
a
iL = -i2, so vL = -i2ZL. Since i2 = g1 (vi - v2),
.
Fig. 3 Schematic of propposed negative indductance circuit, inncluding
bias ciircuit detail. RL inn circuit above corrresponds to RL inn (11), and
R2 aboove corresponds too R2 in (11).
Furtherrmore, the propposed circuit usses the parasiticc capacitance
of the tr
transistors as thhe capacitive looad ZL.
Thee analysis of thhe proposed cirrcuit in Fig. 2 ffollows along
similar lines to Fig. 1, but with iimportant diffferences. To
begin, tthe input currennt from (2) beccomes
since reesistor R1 has cchanged, with R1 = 0.
In addition, the load impedannce ZL now haas a parallel
resistorr RL that is parrt of the bias ciircuit. So, let the new load
impedaance be Z’L = ZL||RL. Then, the load voltaage vL in (5)
becomees
(3)
whhere ZL is the lo
oad impedancee in Fig. 1. Sin
nce iL = -i2, th
hen
vL/Z
ZL = -v2/R2, and v2 = -vLR2/ZL. Substituting
g this result forr v2
in ((3) then gives
.
.
.
(5)
Finnally, combinin
ng (2) and (5) reesults in,
,
,
(10)
From ((10), the circuiit of Fig. 2 is also seen to bbe a negative
impedaance inverter, w
with input impeedance Z’in prroportional to
-1/Z’L. Since RL and ZL comprising Z’L are in paraallel, the input
impedaance can also be written as
(6)
whhere Zin is the desired
d
expresssion for the inp
put impedance of
thee circuit in Fig
g. 1. From (6
6), the circuit is seen to bee a
neggative impedan
nce inverter, sin
nce Zin is propo
ortional to -1/ZL.
(9)
Combinning equations (8) and (9) andd rearranging ggives the new
input im
mpedance Z’in ffor the proposeed circuit of Figg. 2.
(4)
Reaarranging to so
olve for vL gives
(8)
,
.
(11)
The finnal proposed circuit includding bias circuuit details is
shown in Fig. 3.
The result in (6) can be approximated for the case wheere
g2R1 >> 1 and g1R2 >> 1, wheree (6) becomes
.
(7)
Next, the prroposed circuiit is shown in Fig. 2, and
a
corrresponds to th
he circuit of Fig.
F 1, but with
h R1 = 0, and so
diff
ffers from mo
ore common implementatio
ons of negatiive
indductance. In addition,
a
an in
nherent loadin
ng resistor RL is
shoown in Fig. 1, since
s
it is part of
o the proposed
d biasing schem
me.
III.
SIMULATION
N RESULTS
Thee proposed neegative inductaance circuit off Fig. 3 was
designeed in 0.5 microon CMOS and simulated in A
Agilent ADS.
In the design, all nMOS transisstors had widdth×length of
50×0.5 µm and all pM
MOS transistors were 100×00.5 µm. This
circuit uses the desiggn values of RL = 250 ohms aand R2 = 100
ohms fo
for (11).
Re(Z)
250
Im(Z)
0
-250
-500
0.00E+00
0
5.00
0E+08
Frequency
y (GHz)
1.00E+09
0.20
Impedance (ohms)
500
F
Fig. 4. Simulation results
r
showing reeal part of input im
mpedance Zin (solid
d
blue line) and imaginary part of Zin (d
dotted red line) for RL = 250 .
The simulation results off Fig. 4 show
w the real and
a
imaaginary parts of
o the input im
mpedance Zin for the propossed
circcuit of Fig. 3. Here,
H
the negattive inductancee is evident in the
t
dow
wnward trajecttory of the im
maginary part of
o Zin (dotted red
r
currve) at low freequencies belo
ow 500 MHz. This downwaard
lineear slope of th
he reactance of
o the negativee inductor is the
t
oppposite of the case for a posittive inductor. In addition, the
t
exppected parasiticc negative resiistance compon
nent from (11)) is
alsoo seen in the plot of the reaal part of the input impedan
nce
(soolid blue curve)).
In simulation,, nMOS transsistor M2 has transconductan
t
nce
g2 = 0.0036 S with
w width×leng
gth of 50×0.5 µm, and pMO
OS
trannsistor M1 has a transcondu
uctance of g1 = 0.0053 S with
w
widdth×length of 100×0.5 µm. From (11), thee predicted inp
put
imppedance is then
n
,
(12)
witth ZL=1/(j C), and where C is the load caapacitance due to
thee parasitic capaacitance of the two transistorss. For the preseent
casse, C is approxiimately 0.38 pF
F, so (12) finallly becomes
. (13)
Figg. 6. Smith chart s howing measured S11 of input impeddance Zin.
ohms rresistance in seeries with a -330.5 nH inducttance. From
Fig. 4, the observed nnegative resistaance is -235 ohhms including
a seriess internal posittive resistance of R3 = 200 ohhms in Fig. 3,
thus im
mplying an inteernal resistancee of -435 ohm
ms seen at the
gate off M1. From Fiig. 5, the obserrved -115 nH inductance is
larger tthan predictedd. Although itt is suspected that the bias
circuitss may contribuute to the diffference, the prresent design
was chhosen because of its simpliccity and the aadvantages of
having the bias circuuit integrated along with the remainder of
the neggative inductancce circuit.
Fig.. 6 shows a Smith chart for S11 (red dotted line)
correspponding to Zin ffor the circuit oof Fig. 3. The plot of S11 is
observeed outside of the usual Smiith chart regioon due to the
negativve resistance coomponent of Zin as predictedd in (13) and
seen in Fig. 4. Finallyy, the layout off the proposed design in 0.5
micronn CMOS is show
wn in Fig. 7, w
where the overaall size of the
layout is 230 230 miicrons. The deesign is currenttly scheduled
for fabrrication.
Inductance (nH)
From the form
m of (13), thee input impedance is a -320
0.8
0.00
-20.00
-40.00
-60.00
-80.00
-100.00
120.00
Ind
ductance
0.00
0
1.00
Freequency(GHz)
2.00
F
Fig. 5. Simulation results
r
showing inp
put inductance obsserved at Z’in for
RL = 250 .
Fig. 77. Layout of Negattive Inductance Ciircuit with bias shoown.
IV.
CONCLUSION
A negative inductor circuit is designed and analyzed. The
circuit incorporates bias circuits, employs transistor parasitic
capacitance as a load, and sets resistor R1 = 0. The bias
arrangement also introduces a load resistance in parallel with
the capacitive load that is accounted for in the analysis. The
theoretical analysis of the circuit predicts a parasitic negative
resistance in series with the desired negative inductance.
Results are in fair agreement with the negative resistance
component, while larger than expected negative inductance
may be caused by surrounding bias circuits. Despite the
increased inductance, the circuit offers useful negative
inductance with the advantage of an integrated bias circuit.
ACKNOWLEDGMENT
This material is based upon work supported by the National
Science Foundation under Grant No. ECCS-1101939.
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