Download VCSEL’s Bonded Directly to Foundry Fabricated GaAs Smart Pixel Arrays

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IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 9, NO. 12, DECEMBER 1997
VCSEL’s Bonded Directly to Foundry
Fabricated GaAs Smart Pixel Arrays
Rui Pu, E. M. Hayes, Student Member, IEEE, R. Jurrat, C. W. Wilmsen, Senior Member, IEEE,
K. D. Choquette, Member, IEEE, H. Q. Hou, and K. M. Geib
Abstract— This letter reports the flip-chip bonding of an 8 2
8 array of free standing VCSEL’s to a foundry fabricated GaAs
metal–semiconductor field-effect transistor (MESFET) smart
pixel array. The VCSEL’s have oxide defined apertures and are
co-planar bonded directly to smart pixels which perform the
selection function of a data filter. The Vth and series resistance
of the VCSEL’s were on average approximately 2.1 V and 250
, respectively, which indicates that good electrical contact was
obtainable with this process. The Ith ranged between 2–4 mA,
with a corresponding output power of between 400 W and
>1.0 mW depending on aperture size.
Index Terms— Hybrid integration, smart pixel arrays, VCSEL’s.
I. INTRODUCTION
P
ARALLEL optoelectronic processing requires large arrays of smart pixels that are both fast and have uniform
characteristics across the arrays. Smart pixels are composed
of electronic circuits with optical input and optical output. Si
CMOS and GaAs metal–semiconductor field-effect transistor
(MESFET) foundries can easily provide the electronic circuits,
however, suitably mating these electronic technologies with
VCSEL’s and photodetectors has not been adequately developed. Bryan et al. [1] discussed three methods of electrically
connecting VCSEL’s to electronic chips; wire bonding, bridge
bonding, and flip chip bonding of the whole VCSEL chip to
a separate area on the electronic chip. Unfortunately none of
these techniques are suitable for large arrays ( 200 pixels)
since they involve an excessive number of electrical lead
wires or thin-film traces which occupy a large area of the
chip and add significantly to the parasitic capacitance and
inductance of the circuit. Monolithically integrating VCSEL’s
with GaAs MESFET circuits is also possible and several
successful attempts have been reported [2]–[4] for simple
amplifier circuits. And while these have shown good characteristics, they require specialized growth and processing facilities.
Single top-emitting VCSEL’s have been bonded to silicon
wafers [5] or to silicon integrated circuits [6], [7]. Recently,
Mathine et al. [8] have reported an applique technique in which
individual VCSEL’s are epitaxially lifted off and placed on
Manuscript received July 17, 1997; revised August 19, 1997. This work was
supported in part by the National Science Foundation under Grant 9408371
and in part by the NSF/ERC under Grant 9485502.
R. Pu, E. M. Hayes, R. Jurrat, and C. W. Wilmsen are with the Department
of Electrical Engineering, Colorado State University, Fort Collins, CO 80523
USA.
K. D. Choquette, H. Q. Hou, and K. M. Geib are with the Sandia National
Laboratories, Albuquerque, NM 87185 USA.
Publisher Item Identifier S 1041-1135(97)08496-6.
an NMOS driver circuit. This technique uses top and bottom
electrical contacts.
Previously, Goossen et al. [9] reported a co-planar flipchip process for the attachment of SEED devices to CMOS
chips. They showed that this process is both scaleable and
reliable [10]. We have adapted this co-planar technique for
the attachment of arrays of VCSEL’s directly to bonding
pads located in the smart pixel. This technique reduces the
lead capacitance and inductance while maintaining a planar
chip interconnect structure and in addition this technique
is suitable for the simultaneous bonding of arrays. In this
letter, we describe the attachment of 8 8 VCSEL arrays to
foundry fabricated GaAs MESFET smart pixel arrays using
this co-planar contact bonding technique. We chose GaAs
circuits for this demonstration in order to take advantage
of the high-speed MSM photodetectors available with the
standard MESFET integration process, however, the VCSEL
bonding process is equally compatible with Si complementary
metal–oxide–semiconductor (CMOS).
II. DESIGN
AND
FABRICATION
The fabrication of co-planar bonded VCSEL smart pixels
requires the design of three related, but separate components:
the electronic chip, the VCSEL wafer and the VCSEL bonding
process. For the smart pixel arrays reported here, the electronic
chip was designed with the Vitesse Semiconductor 1.0- m
E/D MESFET process using direct coupled FET logic circuits.
The integrated circuits were fabricated by Vitesse through
the MOSIS foundry service. The monolithically integrated
MSM photodetectors (PD’s) of these circuits were comprised
of interdigitated Schottky contacts of the standard MESFET
process. The fingers of the MSM are 50 m long, 1 m wide,
and separated by 1.2 m. These MSM PD’s are nonideal
since the regions between the fingers were subjected to the
same high-doping ion implant as the regions between the gate
and the source and between the gate and the drain of the
MESFET’s. Even so, responsivity of 0.05 A/W at 3 V and
840 nm were measured with operation greater than 200
MHz. The smart pixel circuit contained 32 MESFET’s and
3 MSM PD’s which perform the selection function of a data
filter [11], [12] and also provides the current drive for the
VCSEL. A photograph of a fabricated pixel with and without
a co-planer bonded VCSEL is shown in Fig. 1.
The VCSEL’s used in the co-planar bonding process are of
a standard oxide defined design except the p-mirror (27-layer
pairs) is more highly reflecting than the n-mirror (23-layer
1041–1135/97$10.00  1997 IEEE
PU et al.: VCSEL’s BONDED DIRECTLY TO FOUNDRY FABRICATED GaAs SMART PIXEL ARRAYS
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Fig. 3. SEM photomicrograph of VCSEL’s co-planar bonded to a Vitesse
fabricated electronic chip.
Fig. 1. Optical photograph of a Vitesse fabricated smart pixel: (top) without
a co-planar bonded VCSEL and (bottom) with a co-planar bonded VCSEL.
bond to the VCSEL chip. This required cleaning of the pads,
deposition and patterning of Ti–Au–InSn onto the pads, and
then reflowing the InSn to form a solder ball. No other
processing of the chip was required.
The flip-chip bonding of the VCSEL’s was accomplished
by mounting the VCSEL and Vitesse chips onto separate glass
plates with crystal bond, aligning them in a mask aligner using
IR and then bonding the two chips together with pressure
and heat. After removal from the aligner, epoxy was wicked
in between the chips to protect the Vitesse chip from attack
by the subsequent Br–Methanol polish and citric acid/H O
etch used to remove the GaAs substrate. This process leaves
free standing VCSEL mesas bonded to the pixels as shown in
the scanning electron microscope (SEM) photomicrograph of
Fig. 3 and the illustration of Fig. 2.
III. EXPERIMENTAL RESULTS
Fig. 2. Illustration of a co-planar bonded VCSEL to an electronic chip
showing the mesa structure and the bonding metals.
pairs) and an 0.1- m-thick AlAs etch stop layer was placed
between the n-mirror and the GaAs substrate. The oxide
defined VCSEL’s were fabricated by dry etching 40 m
40 m mesas down to the n-mirror and wet oxidizing at
430 C for 27 min. Ti–Pt–Au p-contacts and Ge–Au–Ni–Au
n-contacts were deposited and annealed at 370 C for 45
s. Au was then electroplated on the n-contact to a height
approximately level with the p-contact. An additional 10 m
30 m) was then electroplated on both n
of Au (30 m
and p-contacts in order to enhance the bonding. A 70 m
125 m mesa surrounding this structure was then formed
by dry etching down to the GaAs substrate as illustrated
in Fig. 2. Since the bonding pads of the Vitesse chip are
Al, post processing of the chip was required in order to
Figs. 1(bottom) and 3 show that physical bonding of the
VCSEL’s to the Vitesse chip has been successfully performed.
Note that there is no metal contact or aperture on the top of
the VCSEL’s since both of the n and p electrical contacts are
on the circuit side of the flip-chip bonded VCSEL. Fig. 4 is
a photograph of an 8
8 pixel array of VCSEL’s that were
simultaneously bonded to the Vitesse fabricated pixel array.
This array bonding has been successfully accomplished on
several different Vitesse chips with high-mechanical bonding
yield and with 30%–50% of the VCSEL’s showing good laser
characteristics. Those VCSEL’s that did not lase appears to
either be broken during handling, have a rough top surface
resulting from poor substrate removal etching, or to not make
sufficient electrical contact due to misalignment of the VCSEL
and Vitesse bonding pads. The latter two problems can be
corrected by adding smoothing layers to the VCSEL design
[7] and adjusting the bonding pad tolerance.
The – and – characteristics from one of the bonded
VCSEL’s is illustrated in Fig. 5. For the VCSEL’s on all
of the arrays tested,
ranged from 1.9–2.4 V and the
series resistance ranged from 135–330 . These values are
approximately the same as before bonding, which indicates
and the maximum power out of
good quality bonds. The
the VCSEL’s varied with the size of the oxide defined aperture.
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IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 9, NO. 12, DECEMBER 1997
Fig. 4. Optical photograph of an 8
to an array of pixels.
2 8 array of co-planar bonded VCSEL’s
Fig. 6. CCD camera image of the output of a co-planar bonded VCSEL
with the pixel photo-activated.
NJ, and the dry etching of Arkadi Goulakov of Colorado State
University.
REFERENCES
Fig. 5.
L–I
and I –V characteristics of a co-planar bonded VCSEL.
ranged from 2 to 4 mA and
ranged from 0.4 to
1 mW for 6- and 10- m aperture, respectively. A charge
coupled device (CCD) camera image of a pixel with a bonded
VCSEL turned on is shown in Fig. 6. The bright area above the
VCSEL is the reflection from the fiber used to provide optical
input to one of the MSM’s of the smart pixels. The reflection
is large and not a well-defined spot because the multimode
fiber had to be directed at an angle of 45 to the chip in
order to observe the VCSEL output through the microscope.
IV. CONCLUSION
We have demonstrated co-planar bonding of VCSEL arrays
to foundry fabricated GaAs electronic circuits that are uneffected by the processing required to attach the VCSEL’s. The
VCSEL’s are placed directly in the pixels, thus reducing the
parasitic lead capacitance and inductance. The VCSEL’s are
shown to have good lasing characteristics and low voltage drop
across the co-planar bonds. The technique has the potential for
providing large optoelectronic arrays for parallel processing
applications.
ACKNOWLEDGMENT
The authors would like to acknowledge the helpful discussion with K. Goossen of AT&T Bell Laboratories, Holmdel,
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