Download TECHNICAL QUALIFYING EXAMINATION

MASSACHUSETTS INSTITUTE OF TECHNOLOGY
DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
TECHNICAL QUALIFYING EXAMINATION
May 26, 2010
YOUR NAME__________________________________________________________
Topic Area: 6.012 – Microelectronic Devices and Circuits
General Instructions:
1. Make certain you have all twelve exam pages (12) of this booklet (13 pages
with this cover). Please do all of your work in the spaces provided in these
pages, and place your answers for each question in the spaces provided. If
you need additional sheets, be sure to put your name and the name of the
examination on each sheet.
2. At the end of the examination, please put this booklet and any extra pages
you have used in the envelope provided.
3. Eight (8) pages of formulas are located after the exam pages.
Special Instructions for 6.012
1. Unless otherwise indicated, you should assume a room temperature ambient
and that kT/q is 0.025 V. You should also approximate [(kT/q) ln 10] as
0.06 V.
2. Make reasonable approximations and assumptions, and state and justify any
assumptions and approximations you make.
3. Your are advised to show as much of your work as possible, and to cross out
things you think are wrong, rather than erasing them.
4. Be careful to include the correct units with your answers when appropriate.
5. An effort has been made to make most parts of these problems independent
of each other so if you have difficulty with one item, go on and come back
to it later.
For examiner’s use only:
Satisfactory
______________
Problem 1 (25 points) _____
Marginal
______________
Problem 2 (25 points) _____
Unsatisfactory ______________
Problem 3 (25 points) _____
Problem 4 (25 points) _____
Total:
1 of 21
Page 2 of 13
Problem 1 - (25 points)
Three short problems:
a) [8 pts] Consider the two bars of p-type Si, NA, = 1017 cm-3 illustrated below. They
are 40 µm long with ohmic contacts on each end, and are identical except that
in one the minority carrier lifetime, τmin, is 10-5 s, and in the other it is 10-9 s.
The electron mobility, µe, is the same, 1,600 cm2/V-s, in both bars.
The bars are illuminated with constant radiation generating ML holeelectron pairs/cm2-s uniformly across the plane at x = 0, i.e. gL(x,t) = MLδ(x).
gL(x) = ML δ(x)
gL(x) = ML δ(x)
Ohmic
Contact
Ohmic
Contact
Ohmic
Contact
p-type Si, N A = 10 17 cm-3
p-type Si, N A = 10 17 cm-3
µe = 1,600 cm 2/V-s, τmin = 10-5 s
µe = 1,600 cm 2/V-s, τmin = 10-9 s
x [µm]
-20 µm
0
20 µm
x [µm]
-20 µm
0
20 µm
i) What is the minority carrier diffusion length, Lmin, in each bar?
Longer lifetime bar (τmin = 10-5 s):
Shorter lifetime bar (τmin = 10-9 s):
Lmin =
µm
Lmin =
µm
ii) On the axes provide, sketch the excess minority carrier populations, n’(x), in
each sample for -20 µm ≤ x ≤ 20 µm. Indicate in the spaces provided the approximate functional shape (e.g. sin x, ex, x2, etc.) of each curve, its initial
slope at x = 0+, and its values at x = ± 20 µm.
τmin = 10-5 s
n’(x)
N’ pk
τmin = 10-9 s
Peak value of plot
n’(x)
N’ pk
Peak value of plot
x [µm]
-20 µm
0
20 µm
x [µm]
-20 µm
Functional shape:
0
Functional shape:
n’(±20 µm) =
n’(±20 µm) =
dn’/dx|x = 0+ =
dn’/dx|x = 0+ =
Problem 1a continues on the next page
2 of 21
20 µm
Page 3 of 13
Problem 1a continued
iii)
In which sample is the value of N’pk larger? Explain your answer.
______ τmin = 10-5 s bar,
______ τ min = 10-9 s bar,
______ They are similar
because
b) [8 pts] This question concerns the design and operation of CMOS inverters in
the sub-threshold region.
i) In the space to the right draw the circuit schematic of a CMOS inverter
indicating the type of each transistor
(n-MOS or p-MOS), and labeling the
sources, drains, and gates (S,D,G),
and the input, output, and supply
voltages (vIN, vOUT, and VDD).
ii) Designing CMOS to operate in the
sub-threshold region makes it possible to make very low power, albeit slow, digital integrated circuits. Which of
the options below for designing CMOS to operate in the sub-threshold region
is the most effective in lowering the power dissipation per gate?
_____ Using standard supply voltages, VDD, with transistors that have
threshold voltages of larger magnitude, |VT| than are standard.
_____ Using transistors having conventional magnitude thresholds, but
supply voltages, VDD, that are much smaller than are standardly used.
_____ By using transistors with much longer gate lengths than conventionally used so the drain currents are very small.
Explain your answer:
iii) Write expressions for the drain currents of the transistors in the schematic
you drew in Part b) i) in terms of vIN, vOUT, and VDD assuming they are operating in the sub-threshold region: |iD| = IST exp(|vGS|/Vt) [1 – exp(-|vDS|/Vt)]
where Vt ≡ kT/q.
iDn =
iDp =
Problem 1 continues on the next page
3 of 21
Page 4 of 13
Problem 1 continued
c) [9 pts] A transimpedance amplifier, which is the subject of this question, is an
amplifier that generates a small-signal output voltage proportional to the
small-signal input current. It is also called a current-to-voltage converter.
Typically this circuit has very low input and output resistance to maximize the
current-to-voltage conversion.
i) Three single-transistor stages that can be used to build transimpedance amplifiers are illustrated below. Label each of these stages (i.e., common-base,
source-follower, etc.) on the line provided below each schematic.
+ 1.5 V
RD
iOUT
+
iIN
+
Q
vIN
-
IBIAS
vOUT
-
+ 1.5 V
+ 1.5 V
RD
RG1
iIN
+
vIN
Q
RG2
-
iOUT
+
iIN
+
vOUT
vIN
-
Q
iOUT
+
vOUT
IBIAS
-
-
ii) Use a combination of two (2) of these single-transistor amplifier stages to design a two-stage transimpedance amplifier. Indicate your selection of stages,
and draw the full schematic of your amplifier using the template provided.
Stage choices: Stage 1:
; Stage 2:
+ 1.5 V
+
V OUT + vout
iin
iii) Find expressions for the input and output resistances of your circuit in Part
ii).
End of Problem 1
4 of 21
rin =
Ω
rout =
Ω
Page 5 of 13
Problem 2 (25 points)
The p-n diode structure below is illuminated with light generating M holeelectron pairs per cm2-s in the plane at x = 2W, as indicated in the drawing. The intensity of the illumination is sufficiently low that all of the classic flow-problem assumptions hold: low level injection, quasi-neutrality, negligible minority carrier
drift, and quasi-static excitation. In this diode the minority carrier lifetime is infinite, the hole mobility is 600 cm2/V-s, and the electron mobility is 1600 cm2/V-s.
gL(x) = MA δ(x-2W)
Ohmic
Contact
Ohmic
Contact
vRL
p-type
NA =
1017 cm -3
L -
n-type, ND = 5 x 1016 cm -3
+ R
iR
x
0
W
2W
3W
4W
a) [4 pts] A partial plot of the excess minority carrier concentrations, n’(x) and
p’(x) in this sample is shown below. Complete this plot for all x. Ignore the
depletion region widths on the p- and n-side of the junction, xp and xn, respectively, relative to W. Do not calculate P’.
p’(x), n’(x)
P’
x
0
W
2W
3W
4W
b) [2 pts] What is the boundary condition, BC, on the minority carrier current density, Jh(x), across the plane x = 2W? That is, how is Jh(2W-δ) related to Jh(2W+δ),
where δ is a vanishingly small distance?
BC on Jh @ x = 2W:
Problem 2 continues on the next page
5 of 21
Page 6 of 13
Problem 2 continued
c) [4 pts] On the axes provided, plot and label the minority carrier current densities throughout the structure, i.e. plot and label Je(x) for 0 ≤ x ≤ W, and plot and
label Jh(x) for W ≤ x ≤ 4W.
Je(x), Jh(x)
x
W
2W
Je(x)
3W
4W
Jh(x)
d) [2 pts] What is the boundary condition on the electron current density across
the plane x = 2W? That is, how is Je(2W-δ) related to Je(2W+δ), where δ is a vanishingly small distance?
BC on Je @ x = 2W:
e) [4 pts] What are the boundary conditions on the electron and hole current densities across the junction, x = W? That is, how is Je(W-xp) related to Je(W+xn),
where xp and xn are the depletion region widths on the p- and n-side of the
junction, respectively? Similarly, how is Jh(W-xp) related to Jh(W+xn)?
BC on Je @ x = W:
BC on Jh @ x = W:
Problem 2 continues on the next page
6 of 21
Page 7 of 13
Problem 2 continued
f) [6 pts] On the axes provided plot and label Je(x), Jh(x), and Jtot(x), the total current, for all x.
Je(x)
x
W
2W
3W
4W
W
2W
3W
4W
W
2W
3W
4W
Jh(x)
x
J tot (x)
x
g) [3 pts] What is iR, the current in at Terminal R? The cross section area is A cm2.
iR =
End of Problem 2
7 of 21
Amps
Page 8 of 13
Problem 3 - (25 points)
The finFET is a MOSFET structure that is receiving a large amount of research
and development attention because it offers promise for solving the challenge of
making Si MOSFETs even smaller (i.e., channel lengths under 20 nm). It is basically
a vertical rectangular bar (fin) of silicon sitting on an insulating surface with source
and drain regions on either end and with a gate dielectric and metal formed over its
middle, as illustrated in the cartoon below left. The cross-section of a finFET you
can use for a 6.012-type one-dimensional electrostatic analysis is shown on the right.
D
D
n+- Si
t ox
n+-Si
Plane of cross-section
S
G
p-Si,NA =
1016 cm-3
L
G
t ox (7 nm)
t fin (20 nm)
S
-(t fin /2 + t ox )
-t fin /2 0
t fin /2 + t ox
x
t fin /2
Looking at the cross-sectional figure, note several features: there is no body contact, B; the structure is symmetrical left to right; and the channel inversion layer
forms along the left-hand, right-hand, and upper oxide-semiconductor interfaces.
a) [2 pts] Is the finFET illustrated above NMOS or PMOS? Explain your answer.
NMOS
PMOS
because
b) [6 pts] Consider first a conventional MOS capacitor fabricated on the p-type silicon in the finFET fin, i.e. p-Si with NA = 1016 cm-3.
i) In this structure, how wide would the depletion region be at the threshold of
strong inversion, vGS = VT?
xD @ vGS = VT:
Problem 3 continues on the next page
8 of 21
µm
Page 9 of 13
Problem 3 continued
ii) The width of the fin in a typical finFET, tFIN, is 20nm. How does this compare
with your answer in part i), and what does it indicate about the finFET at
threshold?
iii) What is the difference in the electrostatic potential at the silicon-dielectric interface, x = ±tFIN/2, and that at x = 0 when the depletion region width is tFIN/2?
φ(x = ±tFIN/2) - φ(x = 0) =
V
c) [x pts] On the axes provided below plot the net charge density, ρ(x), electric field,
E(x), and electrostatic potential, φ(x), in a finFET that is biased at flatband, vGS =
VFB, and find VFB.
Assume that the electrostatic potential metal relative to intrinsic, φm, is -0.3 V.
E(x)
ρ(x)
x
x
-(tox + tfin/2) -tfin/2
0
-(tox + tfin/2) -tfin/2
tfin/2 tox + tfin/2
0
tfin/2 tox + tfin/2
φ(x)
x
-(tox + tfin/2) -tfin/2
0
tfin/2 tox + tfin/2
VFB =
Problem 3 continues on the next page
9 of 21
V
Page 10 of 13
Problem 3 continued
d) [7 pts] On the axes provided below plot the net charge density, ρ(x), electric field,
E(x), and electrostatic potential, φ(x), in a finFET that is biased such that the fin is
just fully depleted. Define this gate bias, vGS, as the full depletion voltage, VFD,
and find VFD – VFB.
E(x)
ρ(x)
x
x
-(tox + tfin/2) -tfin/2
0
-(tox + tfin/2) -tfin/2
tfin/2 tox + tfin/2
0
tfin/2 tox + tfin/2
φ(x)
x
-(tox + tfin/2) -tfin/2
0
tfin/2 tox + tfin/2
VFD – VFB =
V
e) [3 pts] What is the threshold voltage, VT, of this finFET?
VT – VFB =
End of Problem 3
10 of 21
V
Page 11 of 13
Problem 4 - (25 points)
This problem will study the amplifier shown below with two npn BJTs (Q1 and
Q2), three p-MOSFETs (M3, M4, and M5), and three n-MOSFETs (M6, M7, and M8).
In this amplifier the device dimensions are as follow: (W/L)3 = (W/L)4 = (W/L)5 =
(W/L)6 = (W/L)7 = 50µm/4µm, and IREF = 100 µA. In addition, we know the following device parameters:
MOSFETs:
µe Cox = 50 µA/V2
µh Cox = 25 µA/V2
VTn = -VTp = 1 V
Cox = 2.3 fF/µm2
Cov = 0.5 fF/µm
VAn = -VAp = 20 V @ L = 2 µm
npn BJTs:
IBS = 10-17 A
βF = 100
Cπ ≈ 15 fF
Cµ ≈ 10 fF
VCE,sat = 0.3 V
VA = 25 V
+ 2.5 V
M3
IREF
RS
vs
M6
+
Q1
M5
M4
+
vOUT
Q2
RS
-
M8
M7
- 2.5 V
a) [3 pts] Determine the width to length ratio of n-channel MOSFET M8, (W/L)8, so
that the amplifier is biased with all the devices operating in the saturation region and IC1 = IC2 = 50 µA.
(W/L)8:
Problem 4 continues on the next page
11 of 21
Page 12 of 13
Problem 4 continued
b) [4 pts] What are the largest possible positive and negative output voltage
swings, vOUT(max) and vOUT(min)?
VOUT(max) =
V
VOUT(min) =
V
c) [6 pts] In the space below, draw the difference- and common-mode small signal
linear equivalent half circuits of this amplifier and identify the value of each
component.
Difference mode:
Common-mode:
d) [4 pts] Find mid-band voltage gain, Av = vout/vs of this amplifier when the
source resistance, RS, is = 5kΩ.
Av =
Problem 4 continues on the next page.
12 of 21
Page 13 of 13
Problem 4 continued
e) [4 pts] Calculate the quiescent (resting) power dissipation, i.e. when vs = 0 V in
this amplifier.
Quiescent power dissipation =
f) [4 pts] Design the current source IREF.
End of Problem 4; end of 6.012 TQE
13 of 21
W
1
6.012 Microelectronic Devices and Circuits
Formula Sheet for the EECS TQE, Spring 2010
Parameter Values:
Periodic Table:
q = 1.6x10−19 Coul
εo = 8.854 x10−14 F/cm
εr,Si = 11.7, εSi ≈ 10−12 F/cm
n i [ [email protected] ] ≈ 1010 cm −3
kT /q ≈ 0.025 V; ( kT /q) ln10 ≈ 0.06 V
1µm = 1x10−4 cm
Drift/Diffusion:
€
Conductivity :
σ = q(µ e n + µ h p)
∂C
Fm = −Dm m
∂x
Dm kT
=
q
µm
The Five Basic Equations:
Electron continuity :
€
€
sx = ±µ m E x
Einstein relation :
IV
V
C
Si
N
P
Ga
In
Ge
Sn
As
Sb
Electrostatics:
Drift velocity :
Diffusion flux :
III
B
Al
Hole continuity :
Electron current density :
Hole current density :
Poisson's equation :
dE(x)
= ρ (x)
dx
dφ (x)
−
= E(x)
dx
d 2φ (x)
−ε
= ρ (x)
dx 2
ε
E(x) =
1
ε
∫ ρ(x)dx
φ (x) = − ∫ E(x)dx
φ (x) = −
1
ε
∫∫ ρ(x)dxdx
∂n(x,t) 1€∂Je (x,t)
−
= gL (x,t) − [ n(x,t) ⋅ p(x,t) − n i2 ] r(T)
∂t
q ∂x
∂p(x,t) 1 ∂Jh (x,t)
+
= gL (x,t) − [ n(x,t) ⋅ p(x,t) − n i2 ] r(T)
q ∂x
∂t
∂n(x,t)
J e (x,t) = qµ e n(x,t)E(x,t) + qDe
∂x
∂p(x,t)
J h (x,t) = qµ h p(x,t)E(x,t) − qDh
∂x
∂E(x,t) q
= [ p(x,t) − n(x,t) + N d+ (x) − N a− (x)]
∂x
ε
Uniform doping, full ionization, TE
n - type, N d >> N a
€
no ≈ N d − N a ≡ N D ,
kT N D
ln
ni
q
po = n i2 n o ,
φn =
n o = n i2 po ,
φp = −
p - type, N a >> N d
po ≈ N a − N d ≡ N A ,
kT N A
ln
q
ni
Uniform optical excitation, uniform doping
€
n = n o + n'
p = po + p'
Low level injection, n',p' << p o + n o :
n' = p'
dn'
= gl (t) − ( po + n o + n') n' r
dt
dn'
n'
+
= gl (t)
dt τ min
14 of 21
with τ min ≈ ( po r)
−1
2
Flow problems (uniformly doped quasi-neutral regions with quasi-static excitation and low
level injection; p-type example):
n'(x)
1
d 2 n'(x)
−
= −
gL (x)
Le ≡ De τ e
Minority carrier excess :
2
2
Le
De
dx
Minority carrier current density :
Majority carrier current density :
Electric field :
Majority carrier excess :
dn'(t)
dx
J h (x) = JTot − J e (x)
J e (x) ≈ qDe
⎤
1 ⎡
Dh
J e (x)⎥
⎢J h (x) +
De
qµ h po ⎣
⎦
E x (x) ≈
p'(x) ≈ n'(x) +
ε dE x (x)
q dx
Short base, infinite lifetime limit:
d 2 n'(x)
1
1
Minority carrier excess :
≈ −
gL (x), n'(x) ≈ −
2
De
De
dx
€
∫∫ g (x)dxdx
L
Non-uniformly doped semiconductor sample in thermal equilibrium
d 2φ (x)
q
= {n i [e qφ (x ) kT − e−qφ (x ) kT ] − [ N d (x) − N a (x)]}
2
dx
ε
n o (x) = n ie qφ (x ) kT , po (x) = n ie−qφ (x ) kT , po (x)n o (x) = n i2
€
Depletion approximation for abrupt p-n junction:
€
⎧ 0
⎪
⎪−qN Ap
ρ(x) = ⎨
⎪ qN Dn
⎪⎩ 0
w(v AB ) =
for
x < −x p
for −x p < x < 0
for 0 < x < x n
for
xn < x
N Ap x p = N Dn x n
φb ≡ φn − φ p =
2εSi (φ b − v AB ) ( N Ap + N Dn )
q
N Ap N Dn
2q (φ b − v AB ) N Ap N Dn
εSi
(N Ap + N Dn )
E pk =
qDP (v AB ) = −AqN Ap x p (v AB ) = −A 2qεSi (φ b − v AB )
Ideal p-n junction diode i-v relation:
n2
n2
€ n(-x p ) = i e qv AB / kT , n'(-x p ) = i (e qv AB / kT −1);
N Ap
N Ap
iD
⎡ D
De ⎤ qv AB / kT
h
= Aq n i2 ⎢
+
-1]
⎥ [e
⎣ N Dn w n,eff N Ap w p,eff ⎦
-x p
qQNR,p -side = Aq
∫ n'(x)dx,
-w p
p(x n ) =
w m,eff
⎧
⎪
= ⎨
⎪
⎩
kT N Dn N Ap
ln
n i2
q
N Ap N Dn
(N
Ap
+ N Dn )
n i2 qv AB / kT
n2
e
, p'(x n ) = i (e qv AB / kT −1)
N Dn
N Dn
wm − x m
if L m >> w m
Lm tanh [( w m − x m ) Lm ] if L m ~ w m
Lm
if L m << w m
wn
qQNR,n -side = Aq ∫ p'(x)dx,
xn
15 of 21
Note : p'(x) ≈ n'(x) in QNRs
3
Large signal BJT Model in Forward Active Region (FAR):
(npn with base width modulation)
iB (v BE ,vCE ) = IBS (e qv BE / kT −1)
iC (v BE ,v BC ) = β F iB (v BE ,vCE ) [1+ λvCE ] = β F IBS (e qv BE / kT −1) [1+ λvCE ]
IES
Aqn i2 ⎛ Dh
De ⎞
≡
=
+
⎜⎜
⎟,
(β F + 1) (β F + 1) ⎝ N DE w E ,eff N AB w B,eff ⎟⎠
with :
IBS
Also,
(1− δB )
αF =
(1+ δE )
and β F ≈
When δB ≈ 0 then α F ≈
(1− δB )
αF
, and
(1− α F )
and β F ≈
λ≡
1
VA
w B2 ,eff
and δB =
2 L2eB
w
D N
with δE = h ⋅ AB ⋅ B ,eff
De N DE w E ,eff
(δE + δB )
1
(1+ δE )
βF ≡
1
δE
MOS Capacitor:
€
[Δφ = 0
Flat - band voltage : VFB ≡ vGB at which φ (0) = φ p−Si
in Si]
VFB = φ p−Si − φ m
[Δφ = 2φ
Threshold voltage : VT ≡ vGC at which φ (0) = − φ p−Si − v BC
VT (v BC ) = VFB − 2φ p−Si +
1
2εSi qN A 2φ p−Si − v BC
*
Cox
{
[
Depletion region width at threshold :
x DT (v BC ) =
*
Cox
=
Oxide capacitance per unit area :
− v BC
]
in Si
1/ 2
]}
[
2εSi 2φ p−Si − v BC
]
qN A
εox
t ox
[ε
= 3.9,
r,SiO2
εSiO2 ≈ 3.5x10−13 F /cm]
*
q*N = −Cox
[vGC − VT (v BC )]
Inversion layer sheet charge density :
*
q*P = −Cox
[vGB − VFB )]
Accumulation layer sheet charge density :
€
p−Si
Gradual Channel Approximation for MOSFET Characteristics:
(n-channel; strong inversion; with channel length modulation; no velocity saturation)
Only valid for vBS ≤ 0, vDS ≥ 0.
iB (vGS ,v DS ,v BS ) = 0
iG (vGS ,v DS ,v BS ) = 0,
⎧
⎪
0
for
⎪⎪
K
2
iD (vGS ,v DS ,v BS ) = ⎨
[vGS − VT (v BS )] [1+ λ(v DS − v DS,sat )] for
⎪ 2α
⎧
v DS ⎫
⎪
K
v
−
V
(v
)
−
α
for
⎨
⎬ v DS
GS
T
BS
⎪⎩
⎩
2 ⎭
with VT (v BS ) ≡ VFB − 2φ p−Si +
K≡
W
*
µe Cox
,
L
*
Cox
≡
1
2εSiqN A 2φ p−Si − v BS
*
Cox
εox
,
t ox
{
[
[vGS − VT (v BS )] < 0 < α v DS
0 < [vGS − VT (v BS )] < α v DS
0 < α v DS < [vGS − VT (v BS )]
1/ 2
]}
, v DS,sat ≡
⎧
1 ⎪
εSiqN A
α ≡ 1+ * ⎨
Cox ⎪ 2 2φ p−Si − v BS
⎩
[
16 of 21
1
[vGS − VT (v BS )]
α
1/ 2
]
⎫
⎪
⎬ ,
⎪⎭
λ≡
1
VA
4
Large Signal Model for MOSFETs Operated below Threshold (weak inversion):
(n-channel) Only valid for for vGS ≤ VT, vDS ≥ 0, vBS ≤ 0.
iG (vGS ,v DS ,v BS ) = 0,
iB (vGS ,v DS ,v BS ) ≈ 0
iD,s−t (vGS ,v DS ,v BS ) ≈ IS,s−t e
q { vGS −VT (v BS )} n kT
with Vt ≡
(1− e
−qv DS / kT
)
⎛ kT ⎞ 2 2εSiqN A
W
K o Vt2 γ
where IS,s−t ≡
µe ⎜ ⎟
=
2 L ⎝ q ⎠ 2φ p − v BS
2 2φ p − v BS
2εSiqN A
γ
kT
W
*
, K o ≡ µe Cox
, γ≡
, n ≈ 1+
*
Cox
q
L
2 2φ p − v BS
Large Signal Model for MOSFETs Reaching Velocity Saturation at Small vDS:
(n-channel) Only valid for vBS ≤ 0, vDS ≥ 0. Neglects vDS/2 relative to (vGS-VT).
€
Saturation model : sy (E y ) = µe E y if E y ≤ E crit , sy (E y ) = µe E crit ≡ ssat if E y ≥ E crit
iG (vGS ,v DS ,v BS ) = 0,
iB (vGS ,v DS ,v BS ) = 0
⎧
⎪
0
for
(vGS − VT ) < 0 < v DS
⎪
*
iD (vGS ,v DS ,v BS ) ≈ ⎨W ssat Cox [vGS − VT (v BS )][1+ λ(v DS − Ε crit L)] for 0 < (vGS − VT ), Ε crit L < v DS
⎪
W
*
µe Cox
for 0 < (vGS − VT ), v DS < Ε crit L
[vGS − VT (v BS )]v DS
⎪
⎩
L
with λ ≡ 1 VA
CMOS Performance
Transfer characteristic:
€
In general : VLO = 0,
V
Symmetry : VM = DD
2
V HI = VDD ,
ION = 0,
and NM LO = NM HI
⇒
IOFF = 0
K n = K p and VTp = VTn
Minimum size gate : Ln = L p = Lmin , W n = W min , W p = (µn µ p )W n
€
[or W = (s
Switching times and gate delay (no velocity saturation):
2CLVDD
τ Ch arg e = τ Disch arg e =
2
K n [VDD − VTn ]
*
*
CL = n (W n Ln + W p L p )Cox
= 3nW min Lmin Cox
τ Min.Cycle = τ Ch arg e + τ Disch arg e =
assumes µe = 2µh
12nL2minVDD
2
µe [VDD − VTn ]
Dynamic power dissipation (no velocity saturation):
2
DD
Pdyn @ f max = CLV
€
PDdyn @ f max =
2
µ W ε V [V − VTn ]
CLVDD
f max ∝
∝ e min ox DD DD
τ Min.Cycle
t ox Lmin
Pdyn @ f max
InverterArea
∝
Pdyn @ f max
W min Lmin
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€
2
µ ε V [V − VTn ]
∝ e ox DD 2DD
t ox Lmin
2
p
sat,n
ssat, p )W n
]
5
Switching times and gate delay (full velocity saturation):
τ Ch arg e = τ Disch arg e =
CLVDD
*
W min ssat Cox
[VDD − VTn ]
*
*
CL = n (W n Ln + W p L p )Cox
= 2nW min Lmin Cox
τ Min.Cycle = τ Ch arg e + τ Disch arg e =
assumes ssat,e = ssat,h
4nLminVDD
ssat [VDD − VTn ]
Dynamic power dissipation per gate (full velocity saturation):
€
2
f max ∝
Pdyn @ f max = CLVDD
PDdyn @ f max =
2
s W ε V [V − VTn ]
CLVDD
∝ sat min ox DD DD
τ Min.Cycle
t ox
Pdyn @ f max
InverterArea
∝
Pdyn @ f max
W min Lmin
∝
ssatεoxVDD [VDD − VTn ]
t ox L2
Static power dissipation per gate
€
Pstatic = VDD ID,off ≈ VDD
PDstatic =
W min
ε qN
µe Vt2 Si A e{−VT } nVt
Lmin
2 VBS
Pstatic
V
ε qN
−V
nV
∝ 2DD µe Vt2 Si A e{ T } t
Inverter Area
Lmin
2 VBS
CMOS Scaling Rules - Constant electric field scaling
€ Scaled Dimensions : Lmin → Lmin s
Scaled Voltages : VDD → VDD s
Consequences :
*
*
Cox
→ sCox
τ →τ s
W →W s
VBS → VBS s
K → sK
Pdyn → Pdyn s
PDstatic → s2 e( s−1)VT
s n Vt
t ox → t ox s
NA → s NA
VT → VT s
2
PDdyn @ f max → PDdyn @ f max
PDstatic
Device transit times
w B2
w B2
=
Short Base Diode transit time : τ b =
2Dmin,B 2µmin,BVthermal
€
Channel transit time, MOSFET w.o. velocity saturation : τ Ch =
2
L2
3 µCh VGS − VT
Channel transit time, MOSFET with velocity saturation : τ Ch =
L
ssat
€
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6
Small Signal Linear Equivalent Circuits:
•
p-n Diode (n+-p doping assumed for Cd)
gd ≡
∂iD
∂v AB
=
Q
q
q ID
IS e qVAB / kT ≈
,
kT
kT
Cd = Cdp + Cdf ,
2
qεSi N Ap
q I [w p − x p ]
, and Cdf (VAB ) = D
= gd τ d
where Cdp (VAB ) = A
2 (φ b − VAB )
kT
2De
• BJT (in FAR)
q
qI
g
q IC
gm =
β o IBS e qVBE kT [1+ λVCE ] ≈ C ,
gπ = m =
kT
βo
β o kT
kT
⎛
I ⎞
go = β o IBS [e qVBE kT + 1] λ ≈ λ IC ⎜ or ≈ C ⎟
VA ⎠
⎝
€
w B2
,
Cπ = gm τ b + B-E depletion cap. with τ b ≡
2De
•
p
− xp]
2De
Cµ : B-C depletion cap.
MOSFET (strong inversion; in saturation, no velocity saturation)
gm = K [VGS − VT (VBS )] [1+ λVDS ] ≈
€
with τ d
[w
≡
go =
K
2
[VGS − VT (VBS )] λ ≈ λ ID
2
gmb = η gm = η 2K ID
2K ID
⎛
ID ⎞
⎜ or ≈
⎟
VA ⎠
⎝
with η ≡ −
∂VT
∂v BS
=
Q
1
*
Cox
εSiqN A
qφ p − VBS
2
*
Cgs = W L Cox
,
Csb ,Cgb ,Cdb : depletion capacitances
3
*
*
Cgd = W Cgd
, where Cgd
is the G-D fringing and overlap capacitance per unit gate length (parasitic)
•
€
MOSFET (strong inversion; in saturation with full velocity saturation)
*
gm = W ssat Cox
,
go = λ ID =
*
ox
Cgs = W L C ,
ID
,
VA
gmb = η gm
with η ≡ −
∂VT
∂v BS
=
Q
1
*
Cox
εSiqN A
qφ p − VBS
Csb ,Cgb ,Cdb : depletion capacitances
*
*
Cgd = W Cgd
, where Cgd
is the G-D fringing and overlap capacitance per unit gate length (parasitic)
•
€
MOSFET (operated sub-threshold; in forward active region; only valid for vbs = 0)
gm =
q ID
,
n kT
∗
Cgs = W L Cox
go = λ ID =
1+
ID
VA
∗2
2Cox
(VGS − VFB ) ,
εSiqN A
Cdb :
drain region depletion capacitance
*
*
, where Cgd
is the G-D fringing and overlap capacitance per unit gate length (parasitic)
Cgd = W Cgd
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€
2
7
Single transistor analog circuit building block stages
Voltage
gain, Av
BIPOLAR
Current
gain, Ai
β gl
−
[go + gl ]
gm
≈ −gm rl' )
(
[ go + gl ]
gm
≈ gm rl' )
Common base
(
[ go + gl ]
[gm + gπ ]
Emitter follower
≈1
[gm + gπ + go + gl ]
r
Emitter degeneracy
≈− l
RF
[g − GF ] ≈ −g R
Shunt feedback
− m
m F
[ go + G F ]
Common emitter
−
Common source
−
[gm + go + gl ]
Source degeneracy
(series feedback)
Shunt feedback
≈−
−
rπ
[β + 1]
≈ [β + 1] ro
rt + rπ
[β + 1]
≈β
≈ rπ + [β + 1] RF
≈ ro
gl
GF
1
⎛
1 ⎞
ro || RF ⎜ =
⎟
⎝ go + GF ⎠
−
gπ + GF [1− Av ]
Current
gain, Ai
Input
resistance, R i
∞
∞
≈1
≈1
rl
RF
[ gm − G F ]
[go + GF ]
≈
rπ + [β + 1] rl'
gm
= −gm rl' )
(
[ go + gl ]
[gm ]
Source follower
rπ
Output
resistance, R o
⎛ 1 ⎞
ro ⎜= ⎟
⎝ go ⎠
β gl
≈β
[go + gl ]
≈ [ gm + gmb ] rl'
Common gate
Input
resistance, R i
≈1
Voltage
gain, Av
MOSFET
€
Note: gl ≡ gsl + gel,; gl’ ≡ go + gl
≈ −gm RF
−
≈
1
[ gm + gmb ]
Output
resistance, R o
⎛ 1 ⎞
ro ⎜= ⎟
⎝ go ⎠
⎧ [ g + gmb + go ] ⎫
≈ ro ⎨1+ m
⎬
gt
⎩
⎭
1
1
≈
[gm + go + gl ] gm
∞
∞
∞
∞
≈ ro
gl
GF
1
GF [1− Av ]
⎛
⎞
1
ro || RF ⎜=
⎟
⎝ [ go + GF ] ⎠
OCTC/SCTC Methods for Estimating Amplifier Bandwidth
€
-1
OCTC estimate of ω HI:
ω HI
-1
⎡
⎡
⎤
⎤
−1
≤ ⎢∑ [ω i ] ⎥ = ⎢∑ RiCi ⎥
⎣ i
⎣ i
⎦
⎦
with Ri defined as the equivalent resistance in parallel with Ci with all other parasitic
device capacitors (C 's, Cµ's, Cgs's, Cgd's, etc.) open circuited.
π
€
SCTC estimate of ω LO:
ω LO ≥
∑ω = ∑ [ R C ]
j
j
j
−1
j
j
with Rj defined as the equivalent resistance in parallel with Cj with all other baising
and coupling capacitors (C 's, CO's, CE's, CS's, etc.) short circuited.
Ι
€
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8
Difference- and Common-mode signals
Given two signals, v1 and v2, we can decompose them into two new signals, one (vC)
that is common to both v1 and v2, and the other (vD) that makes an equal, but opposite
polarity contribution to v1 and v2:
v D ≡ v1 − v 2
and
vC ≡
[v1 + v 2 ]
2
⎯
⎯→
v1 = vC +
Short circuit current gain unity gain frequency, fT
€
⎧
gm Cgs = 3µCh (VGS − VT ) 2L2 = 3sCh 2L
⎪
*
*
gm Cgs = W ssat Cox
ω t ≈ ⎨
W LCox
= ssat L
⎪
2
⎩ gm (Cπ + Cµ ) ; limI c →∞ gm (Cπ + Cµ ) ≈ 2Dmin,B w B
[
]
vD
2
and
v1 = vC −
vD
2
MOSFET, no vel. sat.⎫
⎪
1
MOSFET, w. vel. sat.⎬ =
τ tr
⎪
BJT, large I C
⎭
€
Revised 4/5/10
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