Download Lecture 6: Dynamic Power

ELEC 5970-001/6970-001(Fall 2005)
Special Topics in Electrical Engineering
Low-Power Design of Electronic Circuits
Dynamic Power
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal
[email protected]
Fall 06, Sep 19, 21
ELEC5270-001/6270-001 Lecture 6
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CMOS Dynamic Power
Dynamic Power
=
Σ 0.5 αi fclk CLi VDD2
All gates i
≈ 0.5 α fclk CL VDD2
≈ α01 fclk CL VDD2
where
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α
α01
fclk
CL
VDD
average gate activity factor
= 0.5α, average 0→1 trans.
clock frequency
total load capacitance
supply voltage
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Example: 0.25μm CMOS Chip

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f = 500MHz
Average capacitance = 15 fF/gate
VDD = 2.5V
106 gates
Power = α01 f CL VDD2
= α01×500×106×(15×10-15×106) ×2.52
= 46.9W, for α01 = 1.0
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Signal Activity, α
T=1/f
α01= 1.0
Clock
α01=
0.5
Comb.
signals
α01= 0.5
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Reducing Dynamic Power

Dynamic power reduction is
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Quadratic with reduction of supply voltage
Linear with reduction of capacitance
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0.25μm CMOS Inverter, VDD =2.5V
Gain = dVout /dVin
2.5
Vout (V)
2.0
1.5
1.0
0
-4
-8
-12
0.5
-16
0
0
0.5
1.0
1.5
2.0
2.5
-20
0
Vin (V)
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ELEC5270-001/6270-001 Lecture 6
0.5
1.0
1.5
2.0
2.5
Vin (V)
6
0.25μm CMOS Inverter, VDD < 2.5V
Similar to analog amplifier
2.5
0.2
Vout (V)
Vout (V)
2.0
1.5
1.0
0.5
0.15
0.1
0.05
Vth = 0.4 V
0
0
0
0.5
1.0
1.5
2.0
Vin (V)
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2.5
0
Gain = -1
ELEC5270-001/6270-001 Lecture 6
0.05
0.1
0.15
0.2
Vin (V)
7
Low Voltage Operation (VDD > Vth)

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Reduced dissipation, increased delay.
Operation sensitive to variations in device
parameters like Vth .
Reduced signal swing reduces internal
noise (crosstalk), increases sensitivity to
external noise.
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ELEC5270-001/6270-001 Lecture 6
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Impact of VDD on Performance
Inverter delay
=
CLVDD
K ─────── , Power ~ CLVDD2
(VDD – Vth )α
Delay (ns)
40
30
20
Power
10
Delay
0
0.4V
VDD=Vth
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1.45V
ELEC5270-001/6270-001 Lecture 6
2.5V
VDD
9
Optimum Power × Delay
Power × Delay, PD =
VDD3
constant × ───────
(VDD – Vth)α
For minimum power-delay product, d(PD)/dVDD = 0
(VDD – Vth)α 3VDD2 – VDD3 α (VDD – Vth)α – 1
———————————————————— = 0
(VDD – Vth)2α
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3VDD – 3Vth
=
VDD
=
α VDD
3 Vth / (3 – α)
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Optimum Power × Delay (Cont.)
For minimum power-delay product, d(PD)/dVDD = 0
VDD
=
3Vth
───
3–α
For long channel devices, α = 2, VDD = 3Vth
For very short channel devices, α = 1, VDD = 1.5Vth
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Very Low Voltage Operation
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VDD < Vth
Operation via subthreshold current.
Small currents have long charging and
discharging times – very slow speed.
Increasing sensitivity to thermal noise.
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Lower Bound on VDD

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For proper operation of gate, maximum gain (for
Vin = VDD/2) should be greater than 1.
Gain = - (1/n)[exp(VDD / 2ΦT) – 1] = - 1
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n = 1.5
ΦT = kT/q = 25 mV at room temperature
VDD = 48 mV
VDDmin > 2 to 4 times kT/q or ~ 50 to 100 mV at
room temperature (27oC)

Ref.: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital
Integrated Circuits, A Design Perspective, Second Edition, Upper
Saddle River, New Jersey: Pearson Education, 2003, Chapter 5.
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ELEC5270-001/6270-001 Lecture 6
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Capacitance Reduction

Transistor sizing for
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Performance
Power
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Basics of Sizing (S = Scale Factor)

Sizing a gate by factor S means all
transistors in that gate have their widths
W changed to WS. Lengths (L) of
transistors is left unchanged.



On resistance of the scaled transistor is
reduced as 1/S
Gate capacitance is scaled as S
Next we consider the delay and power of
the original and scaled gates.
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A Standard Inverter, S = 1
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Cg = input capacitance
Req = on resistance
Cint = intrinsic output capacitance ≈ Cg
Cg
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Cint
ELEC5270-001/6270-001 Lecture 6
CL
16
Transistor Sizing for Performance

Problem: If we increase W/L to make the
charging or discharging of load
capacitance faster, then the increased W
increases the load for the driving gate
Slower charging
More power
Req /S
Faster charging
CL+SCg
Cin=Cg
Increase W for
faster charging of CL
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Delay of a CMOS Gate
Gate capacitance
Cg
CMOS
gate
Intrinsic capacitance
Cint
CL
Propagation delay through the gate:
tp
= K 0.69 Req (Cint + CL)
≈ K 0.69 ReqCg (1 + CL /Cg)
= tp0 (1 + CL /Cg)
where K depends upon VDD, Vth, etc.
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Req , Cg , Cint , and Width Sizing
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Req : equivalent resistance of “on”
transistor, proportional to L/W; scales as
1/S, S = width sizing factor
Cg : gate capacitance, proportional to
CoxWL; scales as S
Cint : intrinsic output capacitance ≈ Cg , for
submicron processes
tp0 : intrinsic delay = K 0.69ReqCg ,
independent of sizing
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Effective Fan-out, F

Effective fan-out is defined as the ratio
between the external load capacitance
and the input capacitance:
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F
=
CL /Cg
tp
=
tp0 (1 + F )
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Sizing Through an Inverter Chain
1
Cg1
2
N
Cg2
CL
Cg2 = f2 Cg1
tp1 = tp0 (1 + Cg2/Cg1)
tp2 = tp0 (1 + Cg3/Cg2)
N
tp
=
Σ tpj =
j=1
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N
tp0
Σ (1 + Cgj+1/Cgj)
j=1
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Minimum Delay Sizing
Equate partial derivatives of tp with respect
to Cgj to 0, for all j
1/Cg1 – Cg3 /Cg22 = 0, etc.
or
Cg22 = Cg1× Cg3, etc.
or
Cg2/Cg1 = Cg3 /Cg2, etc.
i.e., all stages are sized up by the same
factor f with respect to the preceding stage:
CL/Cg1 = F = f N, tp = Ntp0(1 + F1/N )
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Minimum Delay Sizing
Equate partial derivatives of tp with respect
to N to 0:
dNtp0(1 + F1/N)
───────── = 0
dN
i.e., F1/N – F1/N(ln F)/N = 0, or ln (f N) = N
or
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ln f = 1 → f = e = 2.7 and N = ln F
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Further Reading
B. S. Cherkauer and E. G. Friedman, “A Unified Design
Methodology for CMOS Tapered Buffers,” IEEE Trans.
VLSI Systems, vol. 3, no. 1, pp. 99-111, March 1995.
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Sizing for Energy Minimization
Main idea: For a given circuit, reduce
energy consumption by reducing the
supply voltage. This will increase delay.
Compensate the delay increase by
transistor sizing.
Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić,
Digital Integrated Circuits, Second Edition, Upper Saddle
River, New Jersey: Pearson Education, 2003.
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Sizing for Energy Minimization
Minimum
sized gate
Cg1
tp
F
f
1
Req
Cg1
fCg1
Req /f
fCg1
CL
= tp0 [(1+ f ) + (1+ F/f )] = tp0(2 + f + F/f )
= CL/Cg1 , effective fan-out
tp0 ~
VDD /(VDD – Vth) for short channel
Energy dissipation, E = VDD2Cg1(2 + 2f + F )
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Holding Delay Constant

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Reference circuit: f = 1, supply voltage = Vref
Size the circuit such that the delay of the
new circuit is smaller than or equal to the
reference circuit:
tp
tp0 (2+f+F/f )
VDD Vref - Vth 2+f+F/f
── = ──────── = ── ──── ───── = 1
tpref tp0ref (3 +F ) Vref VDD- Vth 3+F
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Supply Voltage Vs. Sizing
3.5
Vref = 2.5V
Vth = 0.5V
F=1
VDD (volts)
3.0
2
2.5
5
fopt ≈ √F
2.0
1.5
10
1.0
1
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2
3
4
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6
f
28
Energy
E
VDD2 2 + 2f + F
── = ─── ──────
Eref
Vref2
4+F
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Normalized Energy Vs. Sizing
Normalized Energy
1.5
2
1.0
fopt ≈ √F
5
0.5
10
1
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Vref = 2.5V
Vth = 0.5V
F=1
2
3
4
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6
f
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Summary
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Device sizing combined with supply voltage
reduction reduces energy consumption.
For large fan-out energy reduction by a factor of
10 is possible.
An exception is F = 1 case, where the minimum
size device is also the most effective one.
Oversizing the devices increases energy
consumption.
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