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Digital Design Concepts
Xilinx Distributor
Certification Program
Module 1
Digital Design Concepts
Congratulations! You now sell programmable
logic semiconductors.
Any idea what they are?
Be sure to view this presentation in PowerPoint
“Notes Page” to see speaker notes.
Agenda
Keywords you will learn
semiconductor
silicon
transistor
integrated circuit
discrete semiconductor
transistor
digital device
gate
flip flop
interconnect
standard logic
PLD
CPLD
FPGA
gate array
standard cell
full custom
ASIC
I/O
gate vs I/O limited
propagation delay
system frequency
 Semiconductors
 Integrated Circuits
 Digital Logic Basics
 Logic Device History
 Basic Concepts
 Quiz
Semiconductors
Total Semiconductors
$160.1B (1999)
Actual 1999 worldwide semiconductor sales:
Source: Dataquest
Semiconductors: scientific
semiconductors:
Can be conductor OR insulator,
located at boundary of the two
Metals: Conduct electricity
Insulators:
Do not conduct electricity
The Transistor
Apply current here
ON
And the switch
is on!
Defn: 3 terminal semiconductor device that acts as a digital switch.
Semiconductor Categories
Total Semiconductors
$160.1B (1999)
ICs
130.2
Discretes
29.9
 Discrete Devices
 A single transistor or diode
 Customized for special needs (e.g. power)
 Optoelectronics included in this category
 Integrated Circuit (IC)
 A bunch of transistors on a single piece of silicon
 More complex functions (e.g. a Pentium has 10
million transistors)
Integrated Circuits
Total Semiconductors
$160.1B (1999)
1
0
ICs
130.2
Discretes
29.9
Digital Devices
108.9
 Digital Devices
 Operate at only 2 levels: 0 or 1
 Very precise way to store & manipulate data
 Easy to miniaturize
Analog
21.3
 Analog Devices
 Operate using a wide dynamic range of voltages
 More difficult to control compared to digital
 Susceptible to noise
 Necessary for interface to the real world
Digital Devices
Total Semiconductors
$160.1B (1999)
ICs
130.2
Discretes
29.9
Digital Devices
108.9
Analog
21.3
Logic
28.3
Memory
28.3
Micros
52.3
 Memory
 DRAM
 SRAM
 FLASH
 MicroComponents
 Microprocessors
 Microcontrollers
 Peripherals
 Digital Logic!
1 byte
address
data stored or retrieved
What’s a gate?
 Fundamental building block for digital logic
 Simple gates consist of 4 to 6 transistors
 A measure of a digital device’s capacity
 How a 3-input gate works ...
If your customer places an order AND ...
ON
Then you will get
your commission!
ON
Xilinx ships the product AND ...
ON
1
1
0
0
ON
1
1
1
... your boss doesn’t fire you
ON
OFF
1
Xilinx Gates
AND2
AND2B1
AND2B2
AND3
AND3B1
AND3B2
AND3B3
AND4
AND4B1
AND4B2
AND4B3
AND4B4
AND5
AND5B1
AND5B2
AND5B3
AND5B4
AND5B5
AND6
AND7
AND8
AND9
OR2
OR2B1
OR2B2
Types of
gates
Gates come in all different flavors:
AND gate
OR gate
NAND gate
XOR gate
There are over 800 different gates in the Xilinx library!
What’s a flip-flop?
Xilinx Flip Flops
FD
FD4
FD8
FD16
FD_1
FD4CE
FD4RE
FD8CE
FD8RE
FD16CE
FD16RE
FDC
FDC_1
FDCE
FDCE_1
FDCP
FDCPE
FDP
FDP_1
FDPE
FDPE_1
FDR
FDRE
FDRS
FDRSE
 A circuit used to store digital information
 Consists of 6 - 9 gates
 Used in counters, registers and state machines
 Number of flip-flops in a device is important for
designers during the selection process
Simple Flip-Flop
DATA input
D
CLOCK input
>
Q
output (no idea why Q)
How a flip-flop works
Xilinx Flip Flops
FDS
FDSE
FDSR
FDSRE
FJKC
FJKCE
FJKCP
FJKCPE
FJKP
FJKPE
FJKRSE
FJKSRE
FTC
FTCE
FTCLE
FTCP
FTCPE
FTCPLE
FTP
FTPE
FTPLE
FTRSE
FTRSLE
FTSRE
FTSRLE
Flip-Flop Timing Diagram
1
DATA
CLOCK
0
D
Q
0
OUTPUT
>
transition A
transition B
1
DATA
0
go!
1
CLOCK
0
1
OUTPUT
0
time
go!
Digital Logic History
Standard Logic Devices
Total Semiconductors
$160.1B (1999)
ICs
130.2
Discretes
29.9
Digital Devices
108.9
Analog
21.3
Logic
28.3
Memory
28.3
Micros
52.3
 Introduced in the late 60’s
 Multiple gates in a single package!
 Aliases: SSI, MSI, TTL, LS, DTL, RTL
 Major players today: Philips, TI, National
 Gives design flexibility to connect individual
“chips” off the shelf saving lots of time
 Big opportunity for distributors to sell lots of
different parts!
the black outline
is the IC package,
this one 16 pin Dual
Inline Package (DIP)
Std Logic
2.6
4 - 50 gates
Logic Interconnect
 Method to hook-up gates inside a single device
 Need to have enough to connect most gates
 Too much will mean a big die size & high cost
vertical interconnect
A
B
horizontal
interconnect
used
interconnect
path
gates
Digital Logic History
S PLD - Simple Programmable Logic Device
Total Semiconductors
$160.1B (1999)
ICs
130.2
Discretes
29.9
Digital Devices
108.9
 Developed in the late 70’s
 Major players today: AMD, Lattice, Cypress
 First device that needs software
 First device that needs a programmer
interconnect
gates
Analog
21.3
flip flops
D Q
>
D Q
Logic
28.3
Micros
52.3
>
Memory
28.3
D Q
>
Std Logic
2.6
S PLD
0.16
D Q
>
50 - 200 gates
A very common
low cost IC package
has pins on all 4 sides
called a Plastic-Leaded
Chip Carrier (PLCC)
Digital Logic History
Gate Array
Total Semiconductors
$160.1B (1999)
ICs
130.2
Defn: An integrated circuit with an array of
transistors which can be connected by metal
interconnect during the fabrication process.
interconnect
Discretes
29.9
Digital Devices
108.9
Analog
21.3
Logic
28.3
Memory
28.3
Micros
52.3
Std Logic
2.6
S PLD
0.16
gates
To increase the number
of I/Os, the pin thickness
and spacing (pitch) are
dramatically reduced in
this Thin Quad FlatPack
package (TQFP).
Gate Array
3.0
1,000,000+ gates
Digital Logic History
Gate Array
Total Semiconductors
$160.1B (1999)
ICs
130.2
Discretes
29.9
Digital Devices
108.9
Analog
21.3
Logic
28.3
Memory
28.3
Micros
52.3
Std Logic
2.6
S PLD
0.16
 The ultimate lego set for digital designers
 Advantages
 Very dense (today over 1,000,000 gates)
 Fast performance
 Very low unit cost
 Disadvantages
 Long turn around time (8-10 weeks)
 $20-100k engineering charges/design
 Risk, if it’s wrong you start again, pay again!
 Major players: Fujitsu, NEC, Toshiba, LSI
Gate Array
3.0
Digital Logic History
Standard Cell
Total Semiconductors
$160.1B (1999)
ICs
130.2
Discretes
29.9
Digital Devices
108.9
Analog
21.3
Logic
28.3
Memory
28.3
Micros
52.3
Std Logic
2.6
S PLD
0.16
 Similar to gate array but much more flexible
 Advantages:
 More optimized die size compared to GA
 Cheaper device price compared to GA
 Can add analog functions
 Disadvantages:
 No standard, more $ engineering ($50k+/design)
 Requires 100k+ units/year
 Much longer development time
 Much higher risk
 Major players: Lucent, LSI, TI
Gate Array
3.0
Standard Cell
12.1
Digital Logic History
FPGA - Field Programmable Gate Array
Total Semiconductors
$160.1B (1999)
Defn: An array of logic cells with general
interconnect that is under the user’s control.
interconnect
ICs
130.2
logic cells
Discretes
29.9
Digital Devices
108.9
Analog
21.3
Logic
28.3
Memory
28.3
Micros
52.3
Std Logic
2.6
S PLD
0.16
FPGA
1.6
Gate Array
3.0
2k - 125k gates
Digital Logic History
FPGA - Field Programmable Gate Array
Total Semiconductors
$160.1B (1999)
ICs
130.2
Discretes
29.9
Digital Devices
108.9
Analog
21.3
Logic
28.3
Memory
28.3
Micros
52.3
Std Logic
2.6
S PLD
0.16
LUT
flip flop
2 types of FPGAs
 Reprogrammable (SRAM-based)
 Xilinx, Altera Flex, Lucent, Atmel
SRAM logic cell
 SRAM determines interconnect
 SRAM defines logic in Look Up Table (LUT)
0110
1011
1100
0001
1010
1111
 One-time Programmable (OTP)
 Actel, Quicklogic
 Interconnect is anti-fuse
 Logic is traditional gates
FPGA
1.6
Gate Array
3.0
Standard Cell
12.1
0
0
1
1
0
1
gates
flip flop
OTP logic cell
Digital Logic History
CPLD - Complex Programmable Logic Device
Defn: A hybrid of PLD blocks and gate array
interconnect for mid-size logic designs.
Total Semiconductors
$160.1B (1999)
interconnect
ICs
130.2
macrocells
Discretes
29.9
Digital Devices
108.9
Analog
21.3
Logic
28.3
Memory
28.3
Micros
52.3
Std Logic
2.6
S PLD
0.16
CPLD
0.8
FPGA
1.6
Gate Array
3.0
500 - 5k gates
Digital Logic History
CPLD - Complex Programmable Logic Device
Total Semiconductors
$160.1B (1999)
ICs
130.2
Discretes
29.9
Digital Devices
108.9
Analog
21.3
Logic
28.3
Memory
28.3
Micros
52.3
Std Logic S PLD
2.6
0.16
CPLD
0.8
 Technology introduced late 80’s by PlusLogic
 Vendors: Altera (MAX), Lattice, Cypress, Vantis, Xilinx
 2 Primary Technologies
 EEPROM (old technology)
 FLASH (new technology - used by Xilinx CPLDs)
 FPGAs vs CPLDs
 FPGAs have much greater capacity
 CPLDs are faster for some small applications
 Both are easy to design
 The customer’s design will dictate the logic solution
FPGA
1.6
Gate Array
3.0
Standard Cell
12.1
Digital Logic History
Summary
Design Capacity
(gates)
1M+
FPGA
125k
CPLD
5k
SPLD
200
Standard
Logic
Logic
28.3
Std Logic
2.6
3%
Gate
Array
Programmable
Logic
hours
SPLD
0.16
-8%
CPLD
0.8
13%
Standard
Cell
Full
Custom
FPGA
1.6
28%
Gate Array
3.0
-17%
Development Time
days
Standard Cell
12.1
22%
weeks
months
years
Full Custom
8.2
-28% 1999-2004 CAGR
Basic Concepts
I/Os - Inputs and Outputs
Types of I/O Buffers
Input
Output
Tri-state
Bi-directional
Input Latch
Output Latch
Input Register
Output Register
Input Pullup
Output Pullup
Hi Slew Output
TTL Input
TTL Output
CMOS Input
CMOS Output
 All signals on & off chip must go through I/O buffer
 User can choose many I/O buffer options
O
I/O buffer
I
package pin
silicon die
Basic Concepts
Gate vs I/O limited
I/O limited
Log
ic
Gate limited
Log
ic
Logic
Logic
All I/Os are used by the
design but not all gates
All logic is used by the
design but not all I/Os
Basic Concepts
Propagation Delay (tPD)
Fractions of a second
.001 = 1 mili (ms)
.000001 = 1 micro (us)
.000000001 = 1 nano (ns)
Defn: The time required for a signal to travel from A
to B, measured in nanoseconds (ns).
Gate Delay
Net Delay
tPD = 3ns
tPD = 1ns
Basic Concepts
Path Delay
Defn: The sum of all the gate and net delays from
starting to ending point.
fanount=2
tPD = 3ns
tPD = 1.2ns
tPD = 3ns
tPD = 1.8ns
tPD = 3ns
Path Delay = sum of all gate + net delays
= 3ns + 1.2ns + 3ns + 1.8ns + 3ns
= 12ns
Basic Concepts
Maximum System Performance (fMAX)
Circuit Events per Second
1 = 1 Hertz (Hz)
1,000 = kilo (kHz)
1,000,000 = mega (MHz)
1,000,000,000 = giga (GHz)
Defn: The fastest speed a circuit containing flip-flops
can operate, measured in Megahertz (MHz).
fMAX =
D
1
longest flip-flop path delay
Q
>
tCQ = 2.5ns
fMAX
tPD = 1ns
tPD = 2ns
tPD = 0.5ns
tPD = 2ns
= 1/(flip-flop delay + gate delays + net delays)
= 1/(2.5 + 1 + 2 + 0.5 + 2)ns
= 1/(8ns)
= 125 MHz
Module 1 Quiz
Xilinx Distributor
Certification Program
Congratulations!
Module 1
Digital Design Concepts
You now should have mastered
the basics of digital design.
To complete this module, you
need to visit your local Rep
office and do the Module 1 quiz.
It is a closed-book, multiple
choice quiz of 25 questions. If
you understand the material
presented here, it will be a
snap.
If you’re not certain
about some areas, ask the
instructor for clarification now!
A
B
C
D
E