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Pixel Sensors for a Linear Collider from Physics Requirements to Beam Test Validation M Battaglia UC Berkeley and LBNL with P Denes, D Bisello, D Contarato, P Giubilato, L Glesener, B Hooberman, C Vu KEK, January 30, 2008 Requirements for ILC Vertexing ILC Vertexing ip a b / pt a (mm) b (mm GeV) LEP 25 70 SLD 8 33 LHC 12 70 RHIC II 14 12 5 10 ILC Mokka+MarlinReco Towards multi-TeV Requirements for the Vertex Tracker Asymptotic I.P. Resolution [ a ] Technology (pitch, S/N) Geometry (Rin, Rout) Multiple Scattering Technology (thickness) I.P. Term [ b ] Geometry (Rin, NLayers) Polar Angle Coverage Space / Time Granularity b a pt Technology (r/o electronics) Geometry (zLayers) Technology (pitch, r/o architecture, r/o time) Geometry (Rin) Physics vs. VTX configuration Higgs BRs accuracy vs. I.P. Resolution Effect of VTX performance on accuracy of BR(H0gbb, cc, gg) at 0.35-0.5 TeV already assessed by various studies using parametric simulation: Channel Change Hgbb Hgcc Hggg Geometry: 5 g 4 layer VTX Thickness: 50 mm g 100 mm Rel. Change in Stat. Uncertainty + 0% +15% + 5% point: Hgcc Hgcc 4 mm g 6 mm 4 mm g 2 mm Thickness: 50 mm g 100 mm +10% -10% Yu et al. J. Korean Phys. Soc. 50 (2007); Kuhl, Desch LC-PHSM-2007-001; Ciborowski,Luzniak Snowmass 2005 +10% Physics vs. VTX configuration Charm Tagging vs. I.P. Resolution Study change in efficiency of charm tagging in Z0-like flavour composition Geometry IP (mm) 4 7 / pt c purity=0.7 ec = 0.49 ec = 0.46 4 10 / pt 4 7 / pt Rin 1.2 cm c purity=0.7 ec = 0.49 i 5.5 14 / pt ec = 0.40 2.1 cm 11 15 / pt HPS c purity=0.7 ec = 0.29 Rin 1.2 cm i 1.7 cm Hawking, LC-PHSM-2000-021 Parametrising the Vertex Tracker Response Provide extrap. resolution for various set of parameters (Rin, ladder thickness, ...) and VXD models obtained using G4 + Kalman Filter Fit: extrap vs. p and q for isolated trks and ptcs in jets. Example: extrap vs. p for isolated ms baseline VXD02 , ladder thickness x 2 , Rin = 18 mm : Pair Background and VTX Detector Geometry of innermost layer bound by distribution of incoherent pairs; Study z point of crossing of electrons with cylinder as function of radius R for various magnetic fields B; R z Pair Background and VTX Detector Compare results of GUINEA_PIG + Mokka simulation with R2 scaling: M.B., V Telnov, Proc. 2nd Workshop on Backgrounds at MDI World Sci, 1998 Generate library of background pair hits to overlay to hits to perform detailed simulation of occupancy, rejection and effect on patrec. Beam tests using 0.05 - 1.0 GeV e- beams at LOASIS and ALS to validate simulation. LDRD-2 response to ALS beam halo CMOS Pixels for ILC CMOS pixel sensors with analog, fast r/o attractive for ILC, requirements on particle extrapolation accuracy constrain pixel pitch and readout architecture, significant experience from IPHC group, applications to real experiments before ILC; Power consumption constrains Achieving < 3 mm single point resolution number of bits for ADC accuracy; with pixel pitch ~ 15-20 mm, requires analog readout + charge interpolation: defines Machine induced backgrounds requirement on ADC accuracy to 4-5 bits if constrain readout time; pedestal can be subtracted before digitisation; D. Grandjean/IPHC Requirements and R&D Streams ILC Vertex Tracker: Multiple Scattering Sensor Thickness (~50 mm) + Ladder Support Asymptotic Resolution + Services Cooling [80 mW/cm2] Power Dissipation [<1mW/ADC] Airflow removes 70-100mW/cm2 < 0.5 mW/ADC ( demonstrated) [ R&D in progress] ADC Resolution [~5 bits] 5 hits/BX X 9 (20 mm pixels)/hit = 250 k hits cm-2 Backgrounds + Physics Pixel Size (10-20 mm) S/N S/N + + Cluster Cluster Readout Size Size Speed [25-50 MHz] 25 MHz r/o 25 ms/512 pixel col O(1 %) occupancy Monolithic Pixel Sensor R&D at LBNL Chip Design: P. Denes Analog Pixel Architecture • Charge Interpolation [ ~ a/(S/N)] • In-pixel CDS & On-chip Digitisation • Fast Readout AMS 0.35mm-OPTO LDRD-1 (2005): 10, 20, 40mm pixels LDRD-2 (2006): 20mm pixels, in-pixel CDS 3T and SB pixels LDRD-3 (2007): 20mm pixels, in-pixel CDS on-chip 5-bit ADCs Binary Pixel Architecture • Small Pixels [ = pitch/ 12 ] • In-pixel Discr. & Time Stamping • In-situ Charge Storage OKI 0.15mm FD-SOI LDRD-SOI-1 (2007): 10mm pixels, analog & binary pixels OKI 0.20mm FD-SOI LDRD-SOI-2 (2008): 10-15mm pixels, analog & binary pixels … Multiple Scattering and Sensor Thickness e+e- g HZgbbm+m- at 0.5 TeV Preserving track extrapolation accuracy to bulk of particles at low momentum requires ultra-thin sensors and mechanical support: Mokka+Marlin Simulation of VXD02 Sensor Thickness mm a mm b mm 25 3.5 8.9 50 3.7 9.6 125 3.8 11.7 300 4.0 17.5 b a pt g need thin monolithic pixel sensor. CMOS Sensor Back-thinning Thin sensitive epi-layer makes CMOS Pixel sensors in principle ideally suited for back-thinning w/o significant degradation of performance expected (especially S/N), but questions arise from earlier results; SiO + Metal Epi Si Bulk Si SEM Image of CMOS Pixel Chip Back-thinning of diced CMOS chips by partner Bay Area company: Aptek. Aptek uses grinding and proprietary hot wax formula for mounting die on grinding plate: Backthinning yield ~ 90 %, chip thickness measured at LBNL after processing: “50 mm” = (50 7)mm , “40 mm” = (41 6)mm; three chips fully characterised: Chip mounted on PCB with reversible glue and characterized Chip removed from PCB Back-thinning Chip re-mounted and re-characterized 40 mm Back-thinned Sensor Tests Study change in charge collection and signal-to-noise before and after back-thinning: Mimosa 5 sensors (IPHC Strasbourg), 1 M pixels 17 mm pitch, 1.8x1.8 cm2 surface 55Fe Collimated Laser 1.5 GeV e- beam Determine chip gain and S/N for 5.9 keV X rays Compare charge collection in Si at different depths Determine S/N and cluster size for m.i.p. S/N NIM A579 (2007) 675 CMOS sensors back-thinning feasible LDRD-2 Chip LDRD-2 Chip: Chip features analog pixel cell with 20 transistors in 20x20mm2 pixel pitch providing in-pixel CDS, power cycling, different bias options, 3 and 5 mm diode sizes, rolling-shutter operation with two parallel outputs of 48 x 96 pixels each. Size: 1.5x1.5 mm2 6 matrices of 20x20 mm2 pixels; AMS 0.35-OPTO process ~ 14 mm epitaxial layer LDRD-2: In-Pixel CDS Digitisation at end of pixel column limited in precision by speed and power dissipation: advantageous to subtract pedestal level in-pixel with correlated double sampling. Stored reference and pixel level with pulsed laser light: diode Cref - Cpixel 20 mm = pedestal subtracted signal LDRD-2: In-Pixel CDS Example of observed response with 1.2 GeV e- electrons Pedestal Pixel Reference Pixel Level w/ beam = LDRD-2: 1.2 GeV e- Beam Test Cluster Event Display LDRD-2 tested on ALS 1.2 GeV e- beams; Noise ~ 45 ENC LDRD-2: 120 GeV p Beam Test T966 Preliminary 5 mm diode LDRD-2 tested at FNAL MTest with T966 CMOS Pixel Telescope on 120 GeV proton beam: Preliminary results @ 21oC at 1.25 MHz <Nb. of Pixels in Cluster> 4-5 <S/N> ~16 T966 Preliminary 3 mm diode LDRD-2: 25 MHz readout test LDRD-2 55Fe Operate LDRD-2 at different r/o speed Results show no appreciable degradation of response up to maximum tested frequency of 25 MHz (r/o time 184 ms) LDRD-2 1.35 GeV e- beam Cluster S/N LDRD-3 Chip LDRD-3 Chip: Third generation chip features same pixel cell as LDRD-2 with in-pixel CDS and 5-bit successive approximation fully differential ADCs at end of columns. CDS subtraction performed at digitisation level; Size: 4.8x2.4 mm2 matrix of 96x96 of 20x20 mm2 pixels; AMS 0.35-OPTO process, received October 2007, ADC currently under test. LDRD-SOI-1 Chip SOI process offers appealing opportunity for monolithic pixel sensors, removing limitations from commercial CMOS; (courtesy Arai/KEK) SOI appealing to industry for low-power devices, ultra-low power stand-by; Specialised 0.15mm FD SOI process with high resistivity bulk and vias offered through KEK within R&D collaborative effort; Chip with 10x10 mm2 pixels, both 3T analog and digital architectures; TCAD Simulation p p Guardring Floating | p LDRD-SOI-1 Analog Pixels: Lab Tests Charge collection properties tested with fast pulsed IR laser focused to 20mm: signal loss for long integration times Significant backgating effect observed interpreted as combined effect of in single transistor test, expect analog backgating and leakage current: chip section functional for Vd < 20 V LDRD-SOI-1 Analog Pixels: Lab Tests Study Depletion Thickness vs. SubstrateVoltage using 1060nm laser spot curves represents d Vd Study Leakage vs. Temperature w/ 1.384 ms integration time and CDS LDRD-SOI-1 Analog Pixels: p & n Irradiation First irradiation performed with 30 MeV protons (2.5x1012 p/cm2) shows evidence of charge build-up in BOX from T tests; Exposure to 1-20 MeV neutrons (1011 n/cm2) shows no appreciable degradation of noise: LDRD-SOI-1 Analog Pixels: Beam Test ALS 1.35 GeV e- Cluster Display Vd (V) Clusters/Evt w/ beam Clusters/Evt <Nb Pixels> w/o beam First Beam Signal on SOI Pixel Chip ALS 1.35 GeV e- Signal MPV (ADC) S/N 8.9 1 9.7 0.05 3.31 132 5 14.0 0.12 3.39 242 14.9 10 7.8 0.20 3.31 316 15.0 15 3.9 0.01 2.45 301 13.6 to appear in NIM A (2007) LDRD-SOI-1 Digital Pixels: Beam Test ALS 1.35 GeV e- Vd (V) Clusters/Evt w/ beam Clusters/Evt <Nb Pixels> w/o beam 20 3.62 0.04 1.78 25 5.81 0.04 1.32 30 8.31 0.04 1.26 35 1.60 0.01 1.14 Digital pixel consists of 2T + comparator and latch, no internal amplification for minimum power dissipation, total 15 transistors in 10x10mm2 SOI Pixel Chip VTX Simulation, Reconstruction, Analysis Jet Flavour Tagging + CDF Vtx Fit Physics Benchmarks G4/Mokka lcio PixelSim ALS & FNAL Beam Test Data Sensor Simulation Marlin Cluster Reconstruction Track Fit and Extrapolation lcio VTX Pattern Recognition lcio PixelAna Sensor and Ladder Characterization Thin Pixel Pilot Telescope Layout: 4 layers of 50 mm thin MIMOSA 5 sensors (17mm pixels) + reference detector; Sensor spacing: 1.5 cm • First beam telescope based on thin pixel sensors; • System test of multi-layered detector in realistic conditions. Beam: beam 4 3 2 1 1.5 GeV e- from LBNL ALS booster at BTS 120. GeV p at MTest, FNAL TPPT at ALS Run 056 Event 001 Perform detailed studies of ILC VTX particle tracking with various, controllable, levels of track density (0.2-10 tracks mm-2) under realistic conditions; Distance of Closest Hit TPPT layout chosen to closely resemble ILC VTX. TPPT Data e+e- gHZ at 0.5 TeV TPPT at ALS Alignment performed using ATLAS optical survey machine and track alignment; Track Sample = 9.4 mm Residual (mm) 2+3 Hits Tracks 9.4 3 Hits Tracks 8.9 High Density 9.5 Low Density 9.2 Extrapolation Resolution on Layer 1: = 8.5 mm matches ILC requirements. NIM A579 (2007) 675 T-966 Beam Test Experiment at Fermilab Beam Test at FNAL MBTF 120 GeV p beam-line (T-966) (UC Berkeley + LBNL + INFN, Padova + Purdue U. Collaboration) TPPT-2 telescope: 4 layers of 50mm thick MIMOSA-5 sensors, ILC-like geometry, extrapolation resolution on DUT ~ 4-5 mm Study LDRD sensors: • single point resolution & sensor efficiency, • response to inclined tracks, • tracking capabilities in dense environment, • vertex reconstruction accuracy with thin target, Validate simulation, test patrec and reco algorithms. T-966 Beam Test Experiment at Fermilab Experimental Setup DUT 4-layered Telescope 4mm Cu Target 4 layers of 50mm thick MIMOSA-5 chips precisely mounted on PC boards with cut through below chip, DUT on XY stage, finger scintillator coincidence for trigger TPPT-2 DUT T-966 at Fermilab First run June-July 2007: operated in various configurations: TPPT only, w/ LDRD-2, w/ target; Operated at 20oC through forced cold air cooling, significant day/night temperature effects, need repeat track alignment daily, first preliminary results: 1 2 3 4 T-966 at Fermilab Cluster Pulse Height Cluster Pixel Multiplicity Track Alignment of T966 Telescope T-966 at Fermilab Residuals on 1st Plane Data 5.4 mm MC 5.1 mm Preliminary T-966 at Fermilab Residual on 1st Layer vs S/N of Hits Track Extrapolation Resolution e+e- g HZgbbm+m- at 0.5 TeV T966 @ MTest TPPT@ALS MTest ALS LOASIS T-966 at Fermilab Reconstructed 120 GeV p interaction in Cu target T-966 at Fermilab 4mm Cu Target Vertex Reconstruction for 120 GeV p interactions Very Preliminary T-966 at Fermilab Vertex Reconstruction for 120 GeV p interactions R&D program on pixel sensors for ILC is progressing despite significant budget and manpower limitations; Various technologies/architecture being studied, mostly complementary to concurrent efforts in Europe and Asia; R&D at LBNL supported by Lab strategic funding and synergies with existing activities (STAR HFT, ATLAS pixels, pixel R&D for BES); CMOS pixel chip with in-pixel CDS and fast r/o designed and tested, new chip with in-chip 5-bit ADCs under test; First pixel chip in SOI technology successfully tested on e- beam; Experience with beam Telescope based on thin CMOS pixels for tracking and vertexing.