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A Probabilistic Approach to Nanocomputing
J. Chen, J. Mundy, Y. Bai, S.-M. C. Chan,
P. Petrica and R. I. Bahar
Division of Engineering
Brown University
Acknowledgements: NSF
Motivation
Silicon-based techniques are approaching practical
limits
http://www.intel.com/research/silicon/mooreslaw.htm
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Jie Chen, Division of Engineering
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Nanotechnology
Quantum transistors
Computing with molecules, carbon nanotube arrays,
pure quantum computing
DNA-based computation, …
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Carbon-Nanotube Devices
We use carbon nanotubes as the basis for our initial study, which
provides good transistor behaviors
(However, our approach is not specific to these devices !!)
http://www.ibm.com
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Why DNA for Self-assembling?
Are there other ways and other molecules that can do it
too? Yes, there are.
But, DNA is the best understood, plentiful, easy to
handle, robust, near-perfect and near-infinite specificity
Cee Dekar, “Nature 2002”
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Non-silicon Approaches
Nano-scale devices are attractive but have high
probability of failure
Defects may fluctuate in time
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Nano-architecture Approaches
Nanofabrics [Goldstein-Budiu]
Architecture detects faults and reconfigures
using redundant components
Array-based approach [DeHon]
“PLA” logic arrays connected by
conventional logic
Neural Nets [Likharev]
Builds neural networks from single-electron
switches
Needs a training stage for proper operation
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Our Probabilistic-based Approach
“ Device failure should not cause computing systems to
malfunction if they have been designed from the
beginning to tolerate faults” --- Von Neumann
Our Probabilistic-based Design
Dynamically defects tolerant
Adapts to errors as a natural
consequence of probability
maximization
Removes need to actually detect
faults
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Why Markov Random Fields?
MRF has been widely used in pattern recognition & comm.
Its operation does not depend on perfect devices or perfect
connections.
MRF can express arbitrary circuits and logic operation is
achieved by maximizing state probability.
or
Minimizing a form of energy that depends on neighboring
nodes in the network  low-power design sn1
1
P( si |  i )  e
Z


1
Uc ( s )
T cC
1st
Order Clique
Neighborhood of Si
Ni
si
2nd Order Clique
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Jie Chen, Division of Engineering
sn 2
sn 3
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A Half-adder Example
x0
x2
x1
x3
x0
x1
x2
x3
i
x0
x1
x2
State
i
x0
x1
x3
State
0
0
0
0
Valid
0
0
0
0
Valid
1
0
0
1
Invalid
1
0
0
1
Invalid
2
0
1
0
Invalid
2
0
1
0
Valid
3
0
1
1
Valid
3
0
1
1
Invalid
4
1
0
0
Invalid
4
1
0
0
Valid
5
1
0
1
Valid
5
1
0
1
Invalid
6
1
1
0
Valid
6
1
1
0
Invalid
7
1
1
1
Invalid
7
1
1
1
Valid
(a) For Summation
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(b) For Carrier
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Rules to Formulate Clique Energy
Clique energy is the negative sum of all valid states:
U ( x0 , x1 , x2 )   fi ( x0 , x1 , x2 ), where f i  1
i
We use Boolean ring conversion to express each minterm
representing a valid state (i.e. ‘000’):
x0' x1' x2'  (1  x0 )(1  x1 )(1  x2 )
 (1  x0  x1  x0 x1 )(1  x2 )
 1  x0  x1  x2  x0 x1  x0 x2  x1 x2  x0 x1 x2
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Clique Energy for the Summation
Sum over the valid states (000, 011, 101, 110)
U  1  x0  x1  x2  2 x0 x1  2 x0 x2  2 x1 x2  4 x0 x1 x2
Lemma: The energy of correct
logic state is always less than
that of invalid logic state by a
constant.
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x0
x1
x2
U
0
0
0
-1
0
0
1
0
0
1
0
0
0
1
1
-1
1
0
0
0
1
0
1
-1
1
1
0
-1
1
1
1
0
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Structural and Signal Errors
Our implementation does not distinguish between devices
and connections.
Instead, we have structural-based and signal-based faults.
-- Structural-based error: Nano-scale devices contain a large
number of defects or structural errors, which fluctuate on time
scales comparable to the computation cycle.
The error will result in variation in the clique
energy coefficients.
-- The second type of error is directly accounted for process noise
that affects the signals.
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Take Device Errors into Design
Sum over the valid states (000, 011, 101, 110)
U  1  x0  x1  x2  2 x0 x1  2 x0 x2  2 x1 x2  4 x0 x1 x2
If we take the device error into consideration, the energy
can be rewritten as:
U    Ax0  Bx1  Cx2  2Dx0 x1 
2 Ex0 x2  2 Fx1 x2  4Gx0 x1 x2
In the error-free case, A=B=C=D=E=F=G=1
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Take Structural Error into Design
x0
x1
x2
U
U    Ax0  Bx1  Cx2  2 Dx0 x1
0
0
0
-1
 2 Ex0 x2  2 Fx1 x2  4Gx0 x1 x2
0
0
1
0
0
1
0
0
0
1
1
-1
1
0
0
0
1
0
1
-1
1
1
0
-1
1
1
1
0
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U 011    B  C  2F
U100    A
U 011  U100
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The Inequalities for Correct Logic
We have 16 inequality relations total for this function
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Constraints on Clique Coefficients
We obtain the following
constraints on the
coefficients:
2G>D 2F>C 2E>A 2D>B
2G>F 2F>B 2E>C 2D>A
2G>E
Constraints form a polytope
High order coefficients constraints the lower order ones
U    Ax0  Bx1  Cx2  2Dx0 x1  2Ex0 x2  2Fx1 x2  4Gx0 x1 x2
Reliability of high order connections determine design
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Take Signal Errors into Design
Gibbs distribution for an inverter is:
1
P( x0 , x1 )  e
Z
1
 (
T
2 x 0 x1 x 0 x1)
x0
x1
The conditional probability is:
P ( x1 , x0 )
P ( x1 | x0 ) 
P ( x0 )
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Jie Chen, Division of Engineering
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Continuous Errors in Signal
We model signal noise
using Gaussian process
Pgaussian 
1
2

e
( x0   )
2
2
2
Design choice 1 -- Inputs around “0” & “1”
Design choice 2 -- Inputs around “-1” & “1”
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Jie Chen, Division of Engineering
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Tolerance to Temperature Variation
By taking input around ‘1’, we get marginalized
probability:
1
P( x1 )   
1 2
1 2
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
P( x1 | x0 ) e
2
2
(
x

1)
2
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dx0
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Error Rate Calculation
incorrect probability
Error rate 
correct  incorrect probability
Proposed design favors for low T and small σ.
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Signal Error in NAND Design
Gibbs distribution for a NAND is:
1  T1 (2 xa xb xc  xa xb  xc )
P( xa , xb , xc )  e
Z
xa
xc
xb
The marginalized probability P(xc) is:
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Jie Chen, Division of Engineering
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Tolerance to Temperature Variation
Apply inputs “01”
Apply inputs “11”
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Jie Chen, Division of Engineering
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Error Rate Calculation
Proposed design works better at low energy state.
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Jie Chen, Division of Engineering
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Conclusions
Proposed design doesn’t depends on specific techniques!!
Propose a probabilistic approach based on MRF
Dynamically defect tolerant
Adapts to errors as a natural consequence of
probability maximization
Removes need to actually detect fault
For correct operation, energy of valid states must be less
than invalid states
The proposed design favors for lower power operation
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Jie Chen, Division of Engineering
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Future Works
We are currently investigating how this approach can be
extended to more complex logic
Implement design using different Nanotechnologies
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Jie Chen, Division of Engineering
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“ Device failure should not cause computing systems to
malfunction if they have been designed from the
beginning to tolerate faults” --- Von Neumann
Thank you
[email protected]
http://binary.engin.brown.edu