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MIMOSA32: October 2011 Submission in Tower 0.18 µm Process Yavuz DEGERLI [email protected] ALICE-MFT Meeting – March 26th, 2012, Orsay 1 Standard MAPS (Monolithic Active Pixel Sensor) Pixel • Sensing elements and processing electronics on the same substrate using a standard CMOS process • Ionizing particles create e-h pairs in the lowly doped epi-layer • Electrons diffuse thermally to the N-well/P-Epi diode A B Electrical Potential N+ N+ N+ P-Well N-Well N+ P-Well MIPs: 100% Fill Factor e- 80 e-h/µm P- Epitatial Layer e- P++ Substrate B’ Depth eIonising Particle e- (total charge) A-A’ B-B’ A’ Only NMOS transistors can be used in the pixel, since any additional N-well used for PMOS transistors would compete for charge collection [email protected] ALICE-MFT Meeting – March 26th, 2012, Orsay 2 MAPS in Quadruple Well Process (Tower 0.18 µm) Cross-section of a CMOS wafer with the deep P-well implant NMOS N+ Diode N+ P-well N+ NMOS N+ N+ N-well PMOS P-well N-well e- e- P+ P+ Deep P-Well eIonizing particle e- P-Epitaxial Layer P++ Substrate Thanks to the deep P-Well implant, PMOS transistors could be used in the pixel [email protected] ALICE-MFT Meeting – March 26th, 2012, Orsay 3 Tower 0.18µm CIS Process Standard and Pinned Diodes (available in CIS process) Standard 3T pixel: Nwell, deep-Nwell, gated Nwell Pinned: buried diode with a transfer gate (CCD-like) (optimized) layout only supplied by Tower! “Half-pinned”: buried diode with a direct contact [email protected] ALICE-MFT Meeting – March 26th, 2012, Orsay 4 Binary MAPS Principle • In most cases, the voltage drop due to the charges collected on the diode of a pixel is lower than the natural process mismatches of MOS transistors (10 mV for a MIP) • In order to extract the signal and implement efficient on-chip discrimination, one needs high-precision (low-noise & low-FPN) and fast front-end electronics: In-pixel amplification close to sensing element, Addressing Auto-zeroing techniques in every amplification stage of the analogue readout path Pixels Discriminators Zero Suppression & Memory Rolling Shutter Mode Low Power dissipation Suitable for large size imagers, [email protected] ALICE-MFT Meeting – March 26th, 2012, Orsay 5 Pixel with CDS and Amplification Feedback or Vclp Clamp p+/nwell SF VDD RD CS Sel_Pix C n+ PWRON n-well CALIB p-epi p-sub Ib Low-pass filter and negative feedback stabilize the operating point of the amplifier and the baseline of the pixel more robust against process mismatches and ionizing irradiation effects Pixel Column Signal amplification by CS and two “Double Sampling” stages: First DS stage (capacitor-switch) suppresses offsets (FPN) of the CS and polarization device of the charge collection diode, temporal noises (1/f and white) of CS not reduced fCK=100 MHz PWRON RST Clamp RD (1) CALIB (2) Second Correlated DS stage (column circuitry) suppresses offset and 1/f noise of SF, white noise of SF not reduced LATCH T Static power dissipation: ~100 µW/pixel (mainly dominated by the output stage) [MIMOSA26: ~180µW/pixel] Readout time: < 80 ns/row possible according to simulations [MIMOSA26: 160 ns/row] [email protected] ALICE-MFT Meeting – March 26th, 2012, Orsay 6 Column-Level Auto-zeroed High-Speed Discriminator Vr2 S1 Vref1 SF S2 Vref2 S1’ VRD Vin VCALIB S4 S3 C1 C2 - + A + - + A + C1’ S2’ - + A + C2’ Q S3 - A + + Latch Q 3 S4’ Vr2 • Both IOS (Input Offset Storage) and OOS (Output Offset Storage) techniques, • All offsets of gain stages removed using only 2 control signals and phases. t1: S1-S1’, S3-S3’, S4-S4’ ON; S2-S2’ OFF Sampling of - offsets of gain stages, - signal level of the pixel (VRD), - threshold voltage Vref1. t2: S2-S2’ ON; S1-S1’, S3-S3’, S4-S4’ OFF, Offset correction (auto-zero) and comparison with - offset of the output stage of the pixel (VCALIB), - the common mode of the threshold voltage Vref2. t3: S2-S2’ ON; S1-S1’, S3-S3’, S4-S4’ OFF, Latching [email protected] Threshold: Vth=Vref1-Vref2 Signal: Vsig = VRD-VCALIB Static power dissipation: ~120µW ALICE-MFT Meeting – March 26th, 2012, Orsay 1 (RD) 2 (CALIB) 3 (LATCH) t1 t2 t3 [MIMOSA26: ~250µW/discri] 7 Column-Level Auto-zeroed High-Speed Discriminator Layout of the discriminator of M32 Gain Stage Vout- Vout+ Vin+ (20µm x 230 µm) Latch LATCH LATCH Q Q Vi1 Vi2 Vin- LATCH Ib A4 • Output common mode voltage well defined, doesn’t need common mode feedback circuit • Dynamic latch: No static power dissipation Vcm(out)= (Vo+ + Vo-)/2 = VDD – ( ib /2).R [email protected] ALICE-MFT Meeting – March 26th, 2012, Orsay 8 3.3 mm MIMOSA32: Overall Chip 13 mm Overall chip dimensions: 13x3.3 = 43 mm² • Prototype for charge collection optimization, radiation studies and in-pixel amplifier optimization, • Prototype for in-pixel amplification & correlated double sampling and column-level discrimination, • Various test structures (LVDS I/O, JTAG, ramp generator, very large diode, etc.), • Prototype including pixels in-pixel discrimination (extension of the 3D RSBPix architecture), • Small prototype including pixels with ampli-shaper-discri, • SPAD: CMOS SiPMs (InESS). * Submission: Octobre 24th, 2011 * Total surface paid: 50 mm² 82.3 kUSD (60 chips) + 4.4 kUSD (2x20chips) [email protected] ALICE-MFT Meeting – March 26th, 2012, Orsay 9 3.3 mm MIMOSA32: Charge Collection & In-Pixel Amplifier Study Chip Pixel Array (128 x 256) 5.2 mm • 32 different sub-arrays of 64x16 pixels, • Basic pitch 20µm, except two sub-arrays (20x40 µm² and 20x80 µm²), • 3T basic pixels (with standard NMOS, Enclosed Layout NMOS, « logic gate » as disturber to check deep P-well, etc.), • Various diode types and sizes (N-well/P-epi, Deep N-well, half pinned), • Pixels with NMOS, PMOS and CMOS based amplifiers (N-well/P-epi diode), • 5 bit decoder to choose one of 32 sub-arrays, 16 parallel analog outputs, • Integration time < 32µs, [email protected] ALICE-MFT Meeting – March 26th, 2012, Orsay 10 Sequencer 1.9 mm MIMOSA32: Column-Level Discrimination & In-Pixel Amplifier Study Chip Pixel Array (128 x 64) Discriminators (128) Output Multipexer (128 to 16) 3.3 mm • 4 different sub-arrays of 64x32 pixels, • Pitch 20µmx20µm, standard N-well/P-epi diodes, • Pixels with NMOS, PMOS based amplifiers and diode-connected transistor or P+/N-well diode as bias element (same pixels also repeated on the previous prototype), • Column-ended discriminators (2 variants), • Simple digital sequencer, • 16 parallel digital outputs, • 3 bit decoder to choose a sub-array of 64x16 pixels & 16 discriminators, • Common threshold voltage for 128 discriminators [email protected] ALICE-MFT Meeting – March 26th, 2012, Orsay 11 Thank you for your attention [email protected] ALICE-MFT Meeting – March 26th, 2012, Orsay 12