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Topics
CAD systems.
 Simulation.
 Placement and routing.
 Layout analysis.

Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
CAD systems
Tools aren’t very useful if they don’t talk to
each other.
 Design interchange languages:

– VHDL (TM), Verilog (TM) (function and structure);
– EDIF (netlists);
– GDS, CIF (masks).
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
CAD tool interactions
xlate a
tool 1
tool 2
tool 1
tool 2
xlate b
xlate c
xlate d
database
xlate e
tool 3
tool 4
database (hub-and-spoke)
Modern VLSI Design 3e: Chapter 10
tool 3
tool 4
translator
Copyright  1998, 2002 Prentice Hall PTR
Back annotation
Often want to iteratively improve design.
 Back annotation updates a more-abstract
design with information from later design
stages.

– Example: annotate logic schematic with
extracted parasitic Rs and Cs.

Back annotation requires tools to know
more about each other.
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Event-driven simulation

Event-driven simulation is designed for
digital circuit characteristics:
– small number of signal values;
– relatively sparse activity over time.

Event-driven simulators try to update only
those signals which change in order to
reduce CPU time requirements.
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Event-driven simulator structure
An event is a change in a signal value.
 A timewheel is a queue of events.
 Simulator traces structure of circuit to
determine causality of events—event at
input of one gate may cause new event at
gate’s output.

Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Event-driven simulation example
A
C
D
B
logic network
Modern VLSI Design 3e: Chapter 10
behavior
Copyright  1998, 2002 Prentice Hall PTR
Event-driven simulation example,
cont’d

Events at primary inputs:
– A changes at t=1;
– B changes at t=2.

Immediate causality:
– C changes at t=3 when both inputs to NOR are
0.

Event propagation:
– D changes at t=4.
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Delay models
Unit-delay simulators assume that each
component has a one-unit delay. Model
function but not performance.
 Variable-delay simulators allow each
component to have its own delay. Accuracy
of performance estimates from variabledelay simulators depends on how well
circuits can be extracted to digital model.

Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Switch simulation
Special type of event-driven simulation
optimized for MOS transistors.
 Treats transistor as switch. Takes
capacitance into account to model charge
sharing, etc.
 Can also be enhanced to model transistor as
resistive switch.

Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Switch simulation example
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Switch simulation example,
cont’d
Node g may be connected to either power
supply, but signals on that node are
terminated by gate of transistor.
 To solve for values of a and b nodes, must
first solve for value of g node.

– If g=1, then a=b.
– If g=0, other parts of circuit determine a and b
independently.
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Switch simulation and charge
sharing
Closed transistor connects source and drain
nodes. Want to determine voltages of
source/drain nodes taking into account
capacitance.
 Capacitance determines node size. Use size
of connected nodes to determine new value
of nodes.
 Result may be X (unknown).

Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Layout synthesis

Two critical phases of layout design:
– placement of components on the chip;
– routing of wires between components.

Placement and routing interact, but
separating layout design into phases helps
us understand the problem and find good
solutions.
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Placement metrics

Quality metrics for layout:
– area;
– delay.
Area and delay deterined in part by wiring.
 How do we judge a placement without
wiring? Estimate wire length without
actually performing routing.

Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Wire length as a quality metric
bad placement
Modern VLSI Design 3e: Chapter 10
good placement
Copyright  1998, 2002 Prentice Hall PTR
Wire length measures
Estimate wire length by distance between
components.
 Possible distance measures:

– Euclidean distance (sqrt(x2 + y2));
– Manhattan distance (x + y).

Multi-point nets must be broken up into
trees for good estimates.
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Placement techniques
Can construct an initial solution, improve an
existing solution.
 Pairwise interchange is a simple
improvement metric:

– Interchange a pair, keep the swap if it helps
wire length.
– Heuristic determines which two components to
swap.
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Placement by partitioning
Works well for components of fairly
uniform size.
 Partition netlist to minimize total wire
length using min-cut criterion.
 Partitioning may be interpreted as 1-D or 2D layout.

Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Min-cut bisecting partitioning
A
1 net
B
3 nets
C
partition 1
Modern VLSI Design 3e: Chapter 10
D
partition 2
Copyright  1998, 2002 Prentice Hall PTR
Min-cut bisecting partitioning,
cont’d

Swapping A and B:
– B drags 1 net;
– A drags 3 nets;
– total cut increase: 4 nets.

Conclusion: probably not a good swap, but
must be compared with other pairs.
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Kernighan-Lin algorithm

Compute min cut criterion:
– count total net cut change.
Algorithm exchanges sets of nodes to
perform hill-climbing—finding
improvements where no single swap will
improve the cut.
 Recursively subdivide to determine
placement detail.

Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Simulated annealing
Powerful but CPU-intensive optimization
technique.
 Analogy to annealing of metals:

– temperature determines probability of a
component jumping position;
– probabilistically accept moves.
– start at high temperature, cool to lower
temperature to try to reach good placement.
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Routing

Major phases in routing:
– global routing assigns nets to routing areas;
– detailed routing designs the routing areas.

Net ordering is a major problem. Order in
whch nets are routed determines quality fo
result. Net ordering is a heuristic.
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Maze routing
Will find shortest path for a single wire, if
such a path exists.
 Two phases:

– Label nodes with distance, radiating from
source.
– Use distances to trace from sink to source,
choosing a path that always decreases distance
to source.
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Maze routing example
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Detailed routing
Dogleg router breaks net into multiple
segments as needed.
 Try to minimize number of dogleg segments
per net to minimize congestion for future
nets.
 One good heuristic—use left-edge criterion
on each dogleg segment to fill up the
channel.

Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Rivest-Fiduccia channel router
Routes from left to right. Assigns all nets
that cross the current column to tracks.
 Heuristics:

–
–
–
–
–
Make connections to pins.
Add jogs to put multi-track net into one track.
Add jogs to reduce distance in multi-track nets.
Add jogs to move net toward next pin.
Add tracks when necessary.
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
YACR2
Tries to minimize number of vias as well as
number of tracks.
 Temporarily satisfies vertical constraints by
adding blank space between pins.
 Eliminates blank space ater by adding jobs.
 May route in both directions on same layer.

Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Layout analysis

Test design rules using Boolean
combinations of masks, grow/shrink.
M2
M1
M1 and M2 not (M1 or M2)
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Scan line algorithm
Mark each edge of polygon with direction.
 Sweep scan line across layout.
 At each point on scan line, count number of
left-hand and right-hand edges to determine
what rectangle that point is in.

Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR
Scan line algorithm example
M2
M1
b
a
sweep
Modern VLSI Design 3e: Chapter 10
Copyright  1998, 2002 Prentice Hall PTR