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CMOS Layout diffusion poly side view cuts top view CSE 567 - Autumn 1998 - CMOS - 1 metal A View of Interconnect Layers CSE 567 - Autumn 1998 - CMOS - 2 Intel 4004 (1971) CSE 567 - Autumn 1998 - CMOS - 3 Pentium II (1996) CSE 567 - Autumn 1998 - CMOS - 4 Silicon in 2010 Die Area: 2.5x2.5 cm Voltage: 0.6 V Technology: 0.07 m Density AccessTime (Gbits/cm2) (ns) DRAM 8.5 10 DRAM (Logic) 2.5 10 SRAM (Cache) 0.3 1.5 Density Max. Ave. Power Clock Rate (Mgates/cm2) (W /cm2) (GHz) Custom 25 54 3 Std. Cell 10 27 1.5 Gate Array 5 18 1 Single-Mask GA 2.5 12.5 0.7 FPGA 0.4 4.5 0.25 CSE 567 - Autumn 1998 - CMOS - 5 CMOS Inverter Layout CSE 567 - Autumn 1998 - CMOS - 6 Layout 4-input NAND gate VDD In1 In2 In3 In4 Out In1 In2 In3 In4 CSE 567 - Autumn 1998 - CMOS - 7 Standard Cell Design Methodology Example “stick diagram” metal1 VDD Well VSS Routing Channel signals polysilicon CSE 567 - Autumn 1998 - CMOS - 8 Different Layouts are Possible Different layouts for x = VDD VDD x x GND a c b (a) Input order {a c b} GND a b c (b) Input order {a b c} CSE 567 - Autumn 1998 - CMOS - 9 The Barrel Shifter A3 B3 Sh1 A2 B2 : Data Wire Sh2 A1 B1 Sh3 A0 B0 Sh0 Sh1 Sh2 Sh3 CSE 567 - Autumn 1998 - CMOS - 10 : Control Wire 4x4 barrel shifter A3 A2 A1 A0 Sh0 Sh1 Sh2 Sh3 CSE 567 - Autumn 1998 - CMOS - 11 Buffer Logarithmic Shifter Sh1 Sh1 Sh2 Sh2 Sh4 Sh4 A3 B3 A2 B2 A1 B1 A0 B0 CSE 567 - Autumn 1998 - CMOS - 12 0-7 bit Logarithmic Shifter A A A A 3 Out3 2 Out2 1 Out1 0 Out0 CSE 567 - Autumn 1998 - CMOS - 13 Latches D In D (b) Non-overlapping clocks (a) Schematic diagram Pseudo-static Latch CSE 567 - Autumn 1998 - CMOS - 14 Edge-Triggered Register (Master/Slave) D A In B Overlapping Clocks Can Cause • Race Conditions • Undefined Signals CSE 567 - Autumn 1998 - CMOS - 15 Non-Overlapping Clocks D In t12 CSE 567 - Autumn 1998 - CMOS - 16 Dynamic Register In D Input Sampled Output Enable CSE 567 - Autumn 1998 - CMOS - 17 Registers and intervening logic Switches and/or gates compute new values to store on next clock cycle straightforward implementation CL 2 1 this circuit can use the entire clock cycle – no wasted time - a form of retiming CL CL 2 CSE 567 - Autumn 1998 - CMOS - 18 1 Memory – Static Register Cells 8-transistor cell bit bit' rd or wr (rd or wr)' sensing amplifier rd/wr' CSE 567 - Autumn 1998 - CMOS - 19 Memory – Dynamic Register Cells 4-transistor cell data-in wr dedicated busses for reading and writing rd dynamic charge storage must be refreshed CSE 567 - Autumn 1998 - CMOS - 20 data-out' Memory – Dynamic Register Cells (cont'd) 3-transistor cell pre-charge data-out' to generate 1 outputs data-in no p-type transistors yield wr a very compact cell rd CSE 567 - Autumn 1998 - CMOS - 21 +5V data-out' Memory – Dynamic Register Cells (cont'd) 1-transistor cell precharge to intermediate voltage level storage capacitor is one end of transistor charge sharing with bus capacitance (Ccell << Cbus) destructive read (must immediately write back) extra demands on sense amplifier to detect small changes in bus charge CSE 567 - Autumn 1998 - CMOS - 22 Read-only Memory Cells To store constants or other invariant data Popular for control implementation bit1 bit2 bit3 read1 read2 programmable logic array structure (exploits distributed NOR gate structure) CSE 567 - Autumn 1998 - CMOS - 23 Multi-ported Register Cells Add more input and output transistors (similar for all variations) Not usually done for 1-transistor cells bus2' bus1 row-bus1 row-bus2 bus2 bus1' CSE 567 - Autumn 1998 - CMOS - 24 Random access memory Decoding logic to select word Attempt to make critical lines (data lines) as short as possible Square aspect ratio rather than rectangular 2m k-bit words per row n address of word (n+m bits) m d e c o d e r 2n by 2m*k bits memory cell array 2n rows multiplexer ( 2m :1) k bits wide (k bits/word) CSE 567 - Autumn 1998 - CMOS - 25 Decoders Decoder looks like AND-plane of ROM (all input combinations) usually replicated throughout array +5 V d e c o d e r memory cell array n rd/wr (row select) bit CSE 567 - Autumn 1998 - CMOS - 26 bit' Multiplexers Decode address into one-hot control signals Each bit passes through single n-device or pass gate note: bits of word in row are interleaved word1 word2 word3 word4 bit1 from a decoder CSE 567 - Autumn 1998 - CMOS - 27 bit2 Content-Addressable Memory Compares input to all entries in memory in parallel applications: pattern recognition, TLBs, etc. Require and encoder to indicate where a match occurred perform inverse function of decoders take a one-hot collection of signals and encodes them m bits 2n rows content addressable memory cell array m CSE 567 - Autumn 1998 - CMOS - 28 e n c o d e r n Content-Addressable Memory Cells Read and write like normal 6T memory cell Match signal is precharged to 1, pulled to 0 if no match send data on bit' and data' on bit for matching match remains 1 if and only if all bits in word match row select match bit bit' CSE 567 - Autumn 1998 - CMOS - 29