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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 4: September 14, 2011 Gates from Transistors 1 Penn ESE370 Fall2011 -- DeHon Previously • Simplified models for reasoning about transistor circuits – Zeroth-order – First-order 2 Penn ESE370 Fall2011 -- DeHon Today • How to construct static CMOS gates 3 Penn ESE370 Fall2011 -- DeHon Outline • Circuit understanding (preclass) • Static CMOS – Structure – Inverter – Construct gate – Inverting – Cascading 4 Penn ESE370 Fall2011 -- DeHon What gate? 5 Penn ESE370 Fall2011 -- DeHon What function? 6 Penn ESE370 Fall2011 -- DeHon DeMorgan’s Law • /f = a + b • What is f? 7 Penn ESE370 Fall2011 -- DeHon What function? 8 Penn ESE370 Fall2011 -- DeHon Static CMOS Gate 9 Penn ESE370 Fall2011 -- DeHon Static CMOS Gate Structure 10 Penn ESE370 Fall2011 -- DeHon Static CMOS Gate Structure 11 Penn ESE370 Fall2011 -- DeHon Static CMOS Gate Structure • Drives rail-to-rail (output is Vdd or Gnd) • Inputs connects to gates load is capacitive • Once charge capacitive output, doesn’t use energy – (first order) • Output actively driven Penn ESE370 Fall2011 -- DeHon 12 Inverter • Out = /in 13 Penn ESE370 Fall2011 -- DeHon Inverter 14 Penn ESE370 Fall2011 -- DeHon Gate Design Example 15 Penn ESE370 Fall2011 -- DeHon Gate Design • Design gate to perform: f=(/a+/b)*/c 16 Penn ESE370 Fall2011 -- DeHon f=(/a+/b)*/c • Strategy: 1. Use static CMOS structure 2. Design PMOS pullup for f 3. Use DeMorgan’s Law to determine /f 4. Design NMOS pulldown for /f 17 Penn ESE370 Fall2011 -- DeHon f=(/a+/b)*/c • PMOS Pullup for f? 18 Penn ESE370 Fall2011 -- DeHon f=(/a+/b)*/c • Use DeMorgan’s Law to determine /f. • What is /f ? 19 Penn ESE370 Fall2011 -- DeHon f=(/a+/b)*/c • NMOS Pulldown for /f? 20 Penn ESE370 Fall2011 -- DeHon f=(/a+/b)*/c a c b 21 Penn ESE370 Fall2011 -- DeHon Inverting Gate 22 Penn ESE370 Fall2011 -- DeHon Inverting Stage • Each stage of Static CMOS gate is inverting 23 Penn ESE370 Fall2011 -- DeHon Why not? 24 Penn ESE370 Fall2011 -- DeHon Source/Drain Reminder • Source is: – Most negative terminal NMOS • source of the electrons – Most positive terminal PMOS • Source of holes 25 Penn ESE370 Fall2011 -- DeHon Source Drain Annotation S D S S D D D S D D S S 26 Penn ESE370 Fall2011 -- DeHon Static CMOS Source/Drains • With PMOS on top, NMOS on bottom – PMOS source always at top (near Vdd) – NMOS source always at bottom (near Gnd) 27 Penn ESE370 Fall2011 -- DeHon Why not buffer? D S S D 28 Penn ESE370 Fall2011 -- DeHon Input at 0V • Vgs NMOS? • Vgs PMOS? • Output voltage? D S S D 29 Penn ESE370 Fall2011 -- DeHon Input at Vdd • Vgs NMOS? • Vgs PMOS? • Output voltage? D S S D 30 Penn ESE370 Fall2011 -- DeHon Behavior Roundup Vin 0 0 1 1 Initial Vout Vout<0.3 Vout>0.3 Vout<0.7 Vout>0.7 Final Vout Vout (unchanged) 0.3 0.7 Vout (unchanged) 31 Penn ESE370 Fall2011 -- DeHon Why not buffer? • Output signal not drive to rails • One threshold voltage away • True any time use PMOS/NMOS on “wrong” side • What’s wrong with it not driving to rails? 32 Penn ESE370 Fall2011 -- DeHon How do we buffer? 33 Penn ESE370 Fall2011 -- DeHon How implement OR? 34 Penn ESE370 Fall2011 -- DeHon Cascading Stages 35 Penn ESE370 Fall2011 -- DeHon Stages • Can always cascade “stages” to build more complex gates • Could simply build nor2 at circuit level and assemble arbitrary logic by combining – universality – but may not be smallest/fastest/least power 36 Penn ESE370 Fall2011 -- DeHon Implement: f=a*/b • Pullup? • Pulldown? 37 Penn ESE370 Fall2011 -- DeHon f=a*/b 38 Penn ESE370 Fall2011 -- DeHon Admin • Friday in Detkin (RCA) Lab – Note homework 1 (due Friday) to design gates before lab – Please read through HW2, Lab1 details – Bring USB drive with you to lab on Friday to store waveforms 39 Penn ESE370 Fall2011 -- DeHon Big Idea • Systematic construction of any gate from transistors 1. Use static CMOS structure 2. Design PMOS pullup for f 3. Use DeMorgan’s Law to determine /f 4. Design NMOS pulldown for /f Penn ESE370 Fall2011 -- DeHon 40