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Complementary CMOS Logic Style Construction (cont.) Digital Integrated Circuits Introduction © Prentice Hall 1995 Example Gate: NAND Digital Integrated Circuits Introduction © Prentice Hall 1995 Example Gate: NOR Digital Integrated Circuits Introduction © Prentice Hall 1995 Example Gate: COMPLEX CMOS GATE VDD B A C D OUT = D + A• (B+C) A D B Digital Integrated Circuits C Introduction © Prentice Hall 1995 4-input NAND Gate Vdd VDD VDD In1 In2 In3 In4 Out In1 In2 Out In3 Out In4 GND In1 In2 In3 In4 GND In1 In2 In3 In4 Digital Integrated Circuits Introduction © Prentice Hall 1995 Nand / Nor Gates Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Standard Cell Layout Methodology metal1 VDD Well VSS Routing Channel signals Digital Integrated Circuits polysilicon Introduction © Prentice Hall 1995 Two Versions of (a+b).c VDD VDD x x GND a c b a b c (b) Input order {a b c} (a) Input order {a c b} Digital Integrated Circuits GND Introduction © Prentice Hall 1995 Properties of Complementary CMOS Gates High noise margins: VOH and VOL are at VDD and GND, respectively. No static power consumption: There never exists a direct path between VDD and VSS (GND) in steady-state mode. Comparable rise and fall times: (under the appropriate scaling conditions) Digital Integrated Circuits Introduction © Prentice Hall 1995 Complex Gate Structures Vdd And-Or-Invert (AOI) C B A B C A Out Out = A+(B*C) ... B A C Gnd How to add terms? Introduction to VLSI Design Introduction © Steven P. Levitan 1998 OAI/AOI Duality Vdd Or-And-Invert (OAI) C B A B C A Switch from: Out = A+(B*C) ... To: B A C Out = A*(B+C) ... Introduction to VLSI Design Demorgan’s Law in Action Out Gnd Introduction © Steven P. Levitan 1998 Demorgan’s Law in Action Or-And-Invert (OAI) A B C Out = A*(B+C) ... Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Demorgan’s Law in Action Or-And-Invert (OAI) A B C Out = A*(B+C) ... Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Demorgan’s Law in Action Or-And-Invert (OAI) A B C Out = A*(B+C) ... Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Demorgan’s Law in Action Or-And-Invert (OAI) A B C Out = A*(B+C) ... Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Demorgan’s Law in Action Or-And-Invert (OAI) A B C Out = A*(B+C) ... What is the Magic command to do this? Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Complex (AOI/OAI) Gates Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Quiz Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Step by Step Layout of XNOR Gate – The equation for XNOR is: f = (a * b) + (a' * b') – using DeMorgan's law on each of the two terms gives: f = (a'+ b')' + (a + b)' – using DeMorgan's law on the two terms together gives: f = ((a'+ b') * (a + b))' – This could be directly implemented with a single complementary CMOS gate: the equation is in a simple negated product of sums form. This form can be implemented with the standard Or-And-Invert (OAI) style gate. Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Non-Inverted Inputs – However, using DeMorgan's law one more time on the left term gives: f = ((a * b)' * (a + b))’ a b f – This form uses no inverted inputs and can be implemented with two gates a NAND gate and an OAI gate. Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Now lets lay it out Start with Vdd! and GND! power buses. Without any more information, about the use of this cell, make the power and ground lines in metal 1 sized 3 and 3 apart. Use poly as inputs A B and guess that C might be used. Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Step by Step Now put in a stripe of N diffusion (green) creating a series of 2 n-channel transistors for the pull down structure for the first NAND gate. Also put in a stripe of P diffusion (brown) and center connection to Vdd to plan for a parallel connection for the pull up structure for the NAND gate. Introduction to VLSI Design Introduction © Steven P. Levitan 1998 By step Now finish wiring up the NAND gate. Strap the two ends of the pull-up parallel transistors and tie them to the series pull down. Use the polly line, C to tie them together. Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Or Gate Begin to add the OR structure for the OAI gate above the NAND gate transistors. This allows us to share the poly lines for A and B inputs. Since we are building an OR structure, its series in the pull up and parallel in the pull down. Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Oh, Oh! No good way to get power up to the end of that pull-up structure, shown above. So, we have to swap the pull-ups for the NAND gate and the OR gate Note that we are only half done with the swap in this picture, the output is not wired correctly. Introduction to VLSI Design Introduction © Steven P. Levitan 1998 We have done several steps – We fixed the output of the NAND so that it uses the correct pull-up structure. – We added a new pull-up transistor in parallel with the two series transistors of the OR structure on the OAI. – It's in parallel because it provides a second path to Vdd for the output. – Note the "L" of metal indicating where the output will come from. – We added a complementary series pull-down transistor for the OAI as well. Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Finish up Here, all we did was add the output strap between the pull-up and pull down structures, completing the OAI gate. We are still missing the WELL contact cuts. I did not finish, 'cause I was late for class. Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Question: Is this the same circuit? Does it compute the same function? Trace it out and see! Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Lab 2: Full Adder Sum = A xor B xor C Cout = AB + AC + BC expand sum Sum = ABC+AB’C’+A’BC’+A’B’C (exactly 1 or 3 inputs true) use Cout to help generate Sum Sum = ABC + Cout’(A+B+Cin) Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Full Adder (4 gates) Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Full Adder (4 gates) Introduction to VLSI Design Introduction © Steven P. Levitan 1998 One Solution (125x136) Introduction to VLSI Design Introduction © Steven P. Levitan 1998 Lab 3: 8 Bit Ripple Carry Adder Introduction to VLSI Design Introduction © Steven P. Levitan 1998 X-panded Introduction to VLSI Design Introduction © Steven P. Levitan 1998