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Chapter 12
Test Technology Trends
in Nanometer Age
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 1
What is this Chapter About?
 Introduce
the test technology roadmap
 Focus on a number of difficult
challenges and test solutions:
 Delay testing, Physical failures and Soft
errors, FPGA testing, MEMS testing, Highspeed I/O testing, and RF testing
 Concluding
remarks
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Section 12.1
Test Technology Roadmap
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Moore’s Law and Test Challenges



Moore’s law: the number of transistors integrated per
square inch will double approximately every 18
months.
To keep track of Moore’s law: die size , feature size ,
gate delay , interconnect delay
To reduce interconnect delay, interconnects are made
taller and taller, and this causes crosstalk noises
between adjacent lines due to capacitive and
inductive coupling (called signal integrity problem).
This is very difficult to test.
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Moore’s Law and Test Challenges



Power integrity: clock frequency , supply voltage , power
supply voltage can drop by L(di/dt). This is very difficult to
test.
Process variation: precise control of silicon process is
becoming more and more difficult. For example, it is hard
to control effective channel length of a transistor. This
makes power and delay exhibit large variability. This is
hard to detect.
Low-power design faults: low-power design circuits might
result in fault models that are difficult to test. For example,
drowsy cache design by reducing power supply will cause
drowsy faults.
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Fabrication Capital versus Test Capital
Cost (cents/transistor)
Fab capital/transistor (Moore’s law)
1
0.1
0.01
0.001
0.0001
Test capital/transistor (Moore’s law for test)
0.00001
0.000001
0.0000001
1982
Based on 1997 SIA Roadmap Data
and 1999 ITRS Roadmap
1985
1988
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1991
1994
1999 Roadmap
1997
2000
2003
2006
2009
2012
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International Technology Roadmap
for Semiconductors (ITRS)


ITRS identifies technological challenges and needs
facing the semiconductor industry over the next 15
years
ITRS test and test equipment near-term challenges
[SIA 2004]:





High-speed device interfaces
Highly integrated designs
Reliability screens
Manufacturing test costs
Modeling and simulation
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International Technology Roadmap
for Semiconductors (ITRS)
 ITRS
test and test equipment long-term
challenges [SIA 2004]:
 DUT (device under test) and ATE
(automatic test equipment) interfaces
 Test methodologies
 Defect analysis
 Failure analysis
 Disruptive device technologies
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International Technology Roadmap
for Semiconductors (ITRS)

ITRS design test near-term challenges [SIA 2004]:
 Effective speed test with increasing core frequencies and
widespread proliferation of multi-GHz serial I/O protocols
 Capacity gap between DFT/test generation/fault grading
tools/design complexity
 Quality and yield impact due to test process diagnostic limitations
 Signal integrity testability and new fault models
 SOC and SIP test

ITRS design test long-term challenges [SIA 2004]:
 Integrated self-testing for heterogeneous SOCs and SIPs
 Diagnosis, reliability screens and yield improvement
 Fault tolerance and on-line testing
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Sections 12.2
Delay Testing
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Why Delay Testing?

Three sources of yield loss
 Random defects – causing both logical and timing failures
 Systematic failures – causing both logical and timing failures
 Parametric variations – more likely causing timing failures
Yrandom
Ysystematic
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Yparamtric
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Fault Models:
Path-Delay & Gate-Delay Faults
Path-delay fault:
 Propagation delay of path exceeds clock interval
 # of paths grows exponentially with number of gates
Only consider long paths or a subset of paths
 Tests can detect small distributed failures
 Tests for longest paths also useful for speed-sorting
Gate-delay fault:
 A logic model for a defect that delays a rising or a falling
transition
 Small distributed timing failures could be missed
 # of modeled faults is much smaller and manageable
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 12
Transition Faults & Small Gate-Delay Faults
Transition fault (Gross gate-delay fault):
 The extra delay caused by the fault is assumed to be
large enough to prevent the transition from reaching
any PO at the time of observation
 Can be tested along any path from fault site to any PO
 The test is a vector pair that creates a transition at the
fault site and the second vector is a test for the stuck-at
fault at the fault site
Small gate-delay fault:
 Is tested along the longest propagation delay path
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Path Delay Faults - Type of Tests
Single-path-sensitization test:
• Guarantee that DUT will fail if and only if the path under test has excessive delay
• Fully characterize the timing of the path and is ideal for delay fault diagnosis
• All side inputs of gates along the given path must be stable
Single-path-sensitization test conditions (for AND gate):
Must be stable “1”
V1 V 2
Off-path inputs
Must be stable “1”
V1 V2
Off-path inputs
Target path
Target path
S1
S1
S1
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S0
S0
S1
S1
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Path Delay Faults - Type of Tests (Cont’d)
Non-robust test :
• Test may be invalidated in presence of other path delay faults
Non-robust test conditions (for AND gate):
Could be either
1 or 0
V1 V2
Could be either
1 or 0 V1 V2
Off-path inputs
Target path
Target path
S1 /
S1 /
S1 /
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Off-path inputs
S0 /
S0 /
S1 /
S1 /
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 15
Path Delay Faults - Type of Tests (Cont’d)
Robust test :
• Guarantees DUT will fail if the path under test has excessive delay
Robust test conditions (for AND gate):
Could be either
1 or 0
V1 V2
Off-path inputs
Must be stable “1”
V1 V 2
Target path
Target path
S1 /
S1 /
S1 /
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Off-path inputs
S0
S0
S1 /
S1 /
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 16
Application of Delay Tests

Require application of a vector pair to the combinational
logic portion and the circuit being clocked at speed
input
latches
output
latches
Combinational
Circuit
Input
clock
Rated clock
period
Input
clock
Output
clock
V1 applied
V2 applied
output
clock
Output latched
An arbitrary vector pair may not be applied to a sequential
circuit under full-scan, partial-scan or non-scan methodology
17
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 17
At-Speed Test
 At-speed
test means application of test
vectors at the rated-clock speed.
 Methods of at-speed test:
 External, functional test
Functional vectors applied by high-speed
testers
 At-speed scan test
 Built-in self-test (BIST)
 Software-based
self-testguarantee high-quality
At-speed
test does not necessarily
delay testing unless tests are designed to detect delay
faults!
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Applying At-Speed Scan Tests
Primary
Inputs
Mode
Swithch
V2 states generated, (A) by one-bit scan shift of V1, or
(B) by V1 applied in functional mode.
Primary
Outputs
Combinational
Logic
Scan in
MUX Scan Cell
1
DATA
FF
0
SCAN_IN
MODE_SW
Scan chain
length: L
FF
Q
D-FF
Q
CLK
FF
Scan out
Test application scheme (B):
Test application scheme (A):
Test Mode
L+1 cycles
CLK
l
l
Test mode Functional mode
2 cycles
L cycles
Functional mode
1 cycle
l
l
l
l
CLK
l
l
l
l
l
MODE_SW
MODE_SW
V2 Response
V1
applied applied captured
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V2
V1
Response
applied applied captured
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 19
l
Classifications of Paths
Based on test conditions:
total path population
non-robust testable
Based on test application schemes:
total path population
scan testable
robust testable
S-P-S
testable
functional
testable
There are untestable paths even if full-scan is used to deliver tests!
But do we really need to test them, if defects/variations on them do
NOT degrade circuit performance in functional mode?
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A Cost-Effective Test Strategy
 Use
functional vectors
 Functional vectors can be applied at-speed
and should catch some delay defects.
 Functional vectors should be evaluated for
transition fault coverage.
 Derive
and apply tests for undetected
transition faults
 Derive and apply tests for long pathdelay faults
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Delay Test/Speed Binning
Challenges for Nanometer Devices

Delay variability increases due to process, circuit,
temperature, power, and noise factors.

No. of critical paths increases due to speed and
power saving techniques.

Clock is increasingly susceptible to
faults/variations creating test inaccuracy and
escapes.

Conventional transition and path delay models and
test methodologies are severely challenged!
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Variability of Path Delay

Noise-induced variability
 Coupling cap -- pattern (excitation/propagation)/timing specific
 Power grid fluctuation -- pattern specific
 Circuit induced -- leakage, charge sharing (pattern specific)

Process-induced variability
 Spatial & temporal parametric variability: lot to lot, wafer to
wafer, die to die
 Limitations in lithography
 CMP induced variability

Thermal-induced variability

Power-induced variability
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Source: TM Mak, Intel
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 23
More Critical Paths: Slowing Down
Non-Critical Paths
 Severe power constraint drove
power optimization everywhere.
# of paths
required time
critical paths to be fixed
delay
 Slowed-down paths + sped-up
paths all crowded around
required period.
required time
# of paths
 More critical paths make it easier
for crosstalk-slowdown to
propagate.
 Bus coupling effect over local wires
may be more likely & frequent.
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non critical paths
to be slowed down
critical paths to be fixed
delay
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 24
Potential Solution: Go Statistical!

Circuit delays can be modeled as correlated random
variables to take various local & global factors into
account:
 Noise, process variations, pattern dependency, temp. variations, etc.
 Global effects can be modeled by correlations factors between delay
random variables.
a
15/1
b
13/2
c
14/2
d
12/3
Mean/variance of pin-to-pin
delay or interconnect delay
e
10/1
g
9/3
f
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Notion of Critical Path
a
b
c
d
Most critical?
15/1
e
13/2
10/1
9/3
14/2
12/3
g
f
Most critical?
The most critical path can be different based
upon which delay model you have in mind!
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Critical Path Varies from Chip
Instance to Instance
15/1
b
13/2
c
14/2
d
12/3
e
10/1
9/3
g
P1:
P2:
P3:
P4:
a, e, g
b, e, g
c, f, g
d, f, g
f
Suppose 10000 chip instances are produced:
P1
P2
P3
P4
43.6% 19.1% 23.6% 13.7%
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Statistical Delay Test & Diagnosis Framework
Need to consist of five major components:
Statistical timing analysis
 Statistical critical path selection
 Selecting statistical long and true paths whose tests
maximize the detection of DSM delay defects
 Path coverage metric
 Estimating the quality of a path set
 Generation of high quality tests for target paths
 Identifying tests that activate longest delay along the
target path
Path delay is highly pattern dependent
 Delay fault diagnosis based on statistical timing model

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Statistical Timing Analyzer

Gate/Cell level
 Correlated delay vs.
 Cell delay library
 Interconnect model
(Correlated) cell/interconnect delays

Monte Carlo Based
 Automatically
determine
convergence condition

Static and dynamic
 Vector-less or vectorArrival times
dependent
(V1V2….)
Estimate signal arrival time as
random variable
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Statistical Critical Paths
Arrival time of O
O
I
Critical Not critical


A critical path can be defined as the one with greater
than P probability of exceeding a cut-off period T
Adjusting P and T to limit the size of critical path set
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Considering Path Correlation for Path
Selection
Change of distributions
after testing A:
Output arrival times:
overlap
A
B
C
clk
25/3
Return of
testing path A
24/3
Return of
testing path B
22/2
Return of
testing path C
After selecting path A, should path B or C be selected?
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Considering Path Independence for
Path Selection
Captured
Paths selected for
test generation



Not captured
Defects on selected paths can be captured.
However, a (small) defect falls beyond the selected
paths may not be captured.
Even with transition fault tests, path independence can
still be an important factor for path selection.
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Statistical Critical Path Selection

A new method achieving four objectives:





Select statistical long paths
Consider path correlation
Achieve path independence
Eliminate statistical false paths
Results indicating that selecting statistical long paths
considering correlation and independence
simultaneously:
 Achieves higher test quality with the same number of selected
paths
 Selects fewer paths to achieve same level of test quality
*J.-J. Liou, et al., "Experience in Critical Path Selection For Deep Sub-Micron Delay Test and Timing
Validation," ASPDAC 2003.
*J.-J. Liou, et al., "False-Path Aware Statistical Timing Analysis and Efficient Path Selection for Delay
Testing & Timing Validation," DAC 2002.
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 33
Section 12.3.1
Signal Integrity
and
Power Supply Noise
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Coping with
Signal Integrity
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 35
Signal Integrity
 Motivation
 Modeling
 Test
Methodologies
 Enhanced BIST
 Enhanced Scan
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 36
Motivation
cost will be dominant in this decade
[ITRS’01]
Cost: Cents/Transistor
 Test
New
DFTs
ITRS
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 37
Result of Technology Scaling
Source:
[ITRS’01 Roadmap]
Factors
Technology
Technology [nm]
0.35
Coupling C [pF]
41.59 49.73 56.93 64.17 70.54
Ground C [pF]
12.89 10.06
9.65
7.30
6.42
Mutual L [nH]
0.80
0.84
0.88
0.93
0.97
Self L [nH]
1.17
1.17
1.18
1.21
1.23
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0.25
0.18
0.13
0.10
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 38
Testing for Signal Integrity
Process
Variations
Shrink of
Technology
Increase of
Frequency
Smaller Design
Rules
Wave-Oriented
Phenomena
Physical
Defects
“There are only two kinds of designers: the ones who
have signal integrity problems, and the ones who will.”
[www.chipcenter.com]
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 39
Fatal Problems on First Spin

Overall 61% of new ICs require at least one re-spin
45
[www.deepchip.com]
40
35
30
25
20
15
10
5
0
Functional
Signal
Error
Integrity
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Reliability
High
Power
Firmware
Error
40
Ch. 12 - Test Technology Trends In Nanometer Age - P. 40
The Bottom Line
Signal integrity loss occurs due to process
variations, manufacturing defects, the parasitic and
coupling C/L. Integrity loss leads to failure.
 Signal integrity problem is both design & test issue.
A systematic approach for testing is needed.

Interconnect
Core i
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Core j
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 41
Interconnect Model
 Signal
integrity problems originate from
interconnects.
 Distributed RLC model is too complicated.
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 42
Integrity Loss Model



Excessive delay degrades performance and causes
functional error.
Ringing causes functional error.
Overshoot contributes to noise, delay, hot carrier, timedependent dielectric breakdown, and electromigration.
overshoot
VHthr
Vdd
VHmin
ringing
Excessive delay
VLmax
Vss
VLthr
T_SI_R
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T_SI_F
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 43
Prior Works

Fault model and test pattern generation
 W. Chen, S. Gupta and M. Breuer [ITC98]
 M. Cuviello, S. Dey, X. Bai and Y. Zhao [ICCAD99]
 A.Attarha, M.Nourani [VTS02]

Self-test methods for testing interconnects
 X. Bai, S. Dey and J. Rajski [DAC00]
 M. Nourani and A. Attarha [DAC01] [JETTA02]
 I. Rayane, J. Medina and M. Nicolaidis [VTS99]

Modified boundary scan





J. Shin, H. Kim and S. Kang [DATE99]
K. Lofstorm [ITC96]
C. Chiang and S. Gupta [VTS97]
S. Yang, C. Papachristou and M. Tabib-Azar [DAC01]
M. Tehranipoor, N. Ahmed, M. Nourani [TCAD04]
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 44
Method 1: Enhanced BIST




The adverse effects of integrity loss will appear only at
the working frequency.
The effects of integrity loss are usually transient and
intermittent.
At-speed testing requires high-performance ATEs.
External test of signal integrity is limited due to speed,
access and probing difficulties.
Test
Pattern
Generator
Interconnect Under Test
(IUT)
Output
Response
Analyzer
Test Controller
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 45
On-Chip Noise Detection


The internal Noise Detector (ND) and Skew Detector (SD)
cells sample signals and record skew and delay
violations.
Our BIST-based methodology can be integrated within
conventional BIST environments with 20% to 50% more
overhead.
T
P
G
R
Interconnect Under Test
(IUT)
ND Cell
SD Cell
M
I
S
R
BIST Controller
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 46
Noise Detector (ND) Cell

The ND cell detects voltage violations, e.g. overshoot and ringing.
signal
Core j
IUT
Core i
Signal + noise
T3
x
Test_mode
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T4
T1
T2
y
T6
c
To read-out
circuit
T7
T5
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 47
Behavior of the ND Cell

The noise detector (ND) cell shows a hysteresis
property and can detect two threshold voltages.
Input:
Output:
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 48
Skew Detector (SD) Cell
XNOR
Sensor
Level restorer
c
To flip-flop
Interconnect signal
(Signal + Delay) a
PDN
Inverter 2
TCK
TCK
b
Inverter 1
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b
b
ADR
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 49
Behavior of the SD Cell
ADR
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Violation
50
Ch. 12 - Test Technology Trends In Nanometer Age - P. 50
Readout Architecture
ND Cell
Vb
Vc
SI
SO
SD
SD Cell
Cell
Vb
Vc
Vb
Vc
SI
SO
1
0
ND Cell
Vb
Vc
SI
SO
SD Cell
Vb
Vc
SI
SO
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1
1
TestController
Controller
Test
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 51
Method 2: Enhanced JTAG
 Boundary
scan provides easy access to the
interconnects
 The boundary scan cells and TAP controller
need modification to:
 generate and apply the test patterns (PGBSC)
 capture and read out the integrity violations
(OBSC)
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 52
Maximum Aggressor (MA) Model
Pg0
Pg1
Ng1
Ng0
Rs
Fs
AI
AI
1
VI
0
1
0
AI
AI
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 53
Pattern Analysis in MA Model
Pg0
Initial value 1
00000
Initial value 2
11111
00000
11111
Ng1
11011
00100
Rs
Fs
00100
11011
Ng0
Pg1
11111
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00000
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 54
Pattern Generation BSC (PGBSC)
TDO/next cell
Input pin/
Core output
0
1
0
D1
1
Q1
D2
0
FF2 Q2
FF1
TDI/
previous cell
Q1
ClockDR
1
ShiftDR
1
Mode
0
Q3
FF3
SI
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Q2
Output pin/
Core input
T
UpdateDR
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 55
Operational Modes of PGBSC
PGBSC Mode
Victim
Aggressor
Normal
Q1
1
0
X
Victim mode
SI
1
1
0
Aggressor mode
UpdateDR
CLK-FF2
Q2
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 56
Encoded Data for Victim Line
Victim-Select
Victim Line
10000
1
01000
2
00100
3
00010
4
00001
5
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 57
Observation BSC (OBSC)
TDO/next cell
ND/SD
ND FF
Input pin/
Core output
SD FF
1
0
0
1
ShiftDR
TDI/
previous cell
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0
0
D1
1
sel
Q1
FF1
ClockDR
D2
Q2
FF2 Q2
Output pin/
Core input
1
Mode
UpdateDR
SI
58
Ch. 12 - Test Technology Trends In Nanometer Age - P. 58
Operational Modes of OBSC
 Values
Modes
ND/SD
SI
NDFF
SDFF
1
0
1
1
Normal
X
0
of signal sel:
SI
ShiftDR
sel
1
1
0
1
0
1
0
X
1
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 59
Operation of OBSC
TCK
Controller
State
Capture-DR Shift-DR
ClockDR
ShiftDR
SI=‘1’
sel=SI+ShiftDR
Select
ND/SD
cell
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(form the
scan chain)
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 60
Test Architecture
BSC
IUT
PGBSC
1
1
2
2
Core i
Standard
IEEE1149.1
Interface
m
OBSC
1
2
Core j
n
k
TDI
TCK
TMS
TRST
TDO
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 61
New Test Instructions



Two new instructions are added to the IEEE1149.1
instruction set
G-SITEST Instruction
 Facilitates test pattern generation based on the MA fault
model
 PGBSCs are enabled with signal SI=1
 ND/SD cells become active (CE=1) to capture the signal
integrity information
O-SITEST Instruction
 Is used to capture and scan out the ND/SD FFs data
 Is loaded after the G-SITEST instruction
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 62
Concluding Remarks - SI



Signal integrity failures are intermittent; therefore, new
test pattern generation, detection and readout strategies
are required.
Enhanced BIST Methodology:
 Is capable of at-speed testing.
 Is relatively expensive unless limited to long buses.
 Provides data for test/reliability analysis and diagnosis.
Enhanced JTAG Architecture:
 Requires noise/skew detector cells on interconnects.
 Needs modified boundary scan cells.
 Provides a cost effective solution to test interconnects
for integrity loss.
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 63
Coping with
Power Supply Noise
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 64
Power Supply Noise (PSN)

Noise in high speed design
 Sharp rise and fall times (small dt)
 Changes in current drawn from Vdd (large di)

VPSN = L · di(t)/dt + R · i(t)

Large voltage fluctuation
 Intermittent malfunctions
 Functional failure
 Reliability problem
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 65
Motivation

Power supply noise analysis captures noise
more globally in high speed circuits.

PSN analysis can be useful for
 Pre synthesis noise/performance estimation
 Sensitivity analysis
 Power supply network design

Accurate estimation of PSN in a core based
SoC without exhaustive simulation.
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 66
Prior Work

Genetic algorithms
 Y. Jiang, K. Cheng and A. Krstic [CICC’97]
 G. Bai, S. Bobba and I. Haji [ICECS’01]
 S. Zhao, K. Roy and C. Koh [ICCD’00]

Estimation based on modeling
 Y. Chang, S. Gupta and M. Breuer [VTS’97]
 L. Zheng, B. Li, and H. Tenhunen [ISCAS’00]
 M. Nourani, M. Tehranipoor, N. Ahmed [VTS’05]

Application – power distribution and floor planning
 N. Pham, M. Cases, D. Araujo and E. Matoglu [VTS’04]
 S. Zhao, K. Roy and C. Koh [ASP-DAC’02]
67
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 67
Power Distribution Wire and Pin Model

Vnoise(t) = (Vdd,pin - Vdd,block(t)) – (Vss,pin - Vss,block(t))
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 68
PSN Analysis Metrics

Level – A level of a node (distance from primary
input) implies how difficult or restrictive it is to
switch that node.

Fan-Out – Switching time (tP) is inversely
proportional to fan-out. Switching low fan-out
gates will reduce dt  increase di/dt.

Fan-In – Large fan-in gates are resized (more
wide) to allow proper pull-up and pull-down.
Large width allows drawing more current.
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 69
Effect of Level
Lower level  More
switching
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 70
Effect of Fan-Out
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 71
Effect of Fan-In
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 72
Different Methods
Method
M1
M2
M3
M4
M5
M6
Order of
Metrics
ILO IOL OLI OIL LOI LIO

Ordering of metrics gives priority to switching one gate
over the other.

Level is given the highest priority due to ease of control.
 M5 (LOI) and M6 (LIO) methods are used.
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 73
Test Pattern Generation
 Exhaustive
 2n·(2n-1) ≈ 22n possible transitions
 Random
 Cannot guarantee peak power in short time.
 Instead
of exhaustive or random search,
heuristic-based approach should be used.
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 74
Basic Approach

Use conventional s-a-f pattern generation
method and tools to stimulate 01 or 10
transition.

Determine test pattern pairs by estimating
maximum PSN according to three PSN
metrics.
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 75
Concluding Remarks (PSN)

Power supply noise captures the effect of
noise globally.

One goal is often to generate a pattern pair to
stimulate maximum PSN in non-embedded
cores.

Combining individual PSN curves strategically
provides a way to estimate PSN of SoC
without full simulation.
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 76
Section 12.3.2
Parametric Defects, Process
Variation, and Yield
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 77
Defects and Physical Defects





Physical defects occur during manufacturing, and can
cause static or timing physical failures
Defects can be random or systematic, and can be
functional or parametric
Traditional work is more on functional random spots
Other three types of defects need to be researched
Defects can also be caused by process variations
and random imperfections
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 78
Defect-Based Test


Defect-based test can be done by enumerating likely defect sites from
layout
At-speed tests (path-delay tests and transition tests) must be used
ATPG
RTL
Schematics
RC Extraction
Layout
Synthesis
Modeling
Timing Analysis
Defect-Based
Fault Enumeration
Gate-level Netlist
Structural Tests
Defect-Based Fault Simulator
Fault List
Functional Tests
Defect-Based ATPG
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Path Extractor
Critical Path
List
Physical Faults
Fault Mapping
Logical Fault List
Structural Tests
79
Ch. 12 - Test Technology Trends In Nanometer Age - P. 79
Supplements of Conventional Stuck-at Tests






Bridging tests: enumerate likely bridging fault sites
(interconnects) by layout simulation
N-defect stuck-at tests: detect every stuck-at fault N times by
targeting different sensitive paths
TARO (transition fault propagation to all reachable outputs):
generate transition tests one for each reachable output, for each
given transition fault.
IDDQ tests: test by measuring current flow
Functional Testing: must be added to supplement structural tests
Key issue: how to generate these defect-based tests in a timely
manner to meet test goals.
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 80
Sections 12.3.3 -12.3.4
Soft Errors and Fault Tolerance
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 81
Cosmic Ray/Radiation Mechanics
high
energy
neutrons
lighter
Particles
+ -+
+ -+
+ -+
+ -+
+ -
++ +- +
-+- +- + - -+
some particles also may
pass through all material
without colliding with any
atoms
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 82
Mechanism of Neutron SER
cosmic rays
protons, heavy ions
neutrons
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 83
Neutron Environment

Primary
Cosmic Rays

Neutrons
Secondary
Cosmic Rays

N,O


























EE141
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Normand et al.
1,000,000 feet
330 km
Shuttle
150,000 feet
50,000 m
Top of
Atmosphere
60,000 feet
20,000 m
Peak
Neutron
Flux
~ 35,000 feet
10,000 m
Aircraft
Ground ~ 1/500 of Peak Flux
84
Ch. 12 - Test Technology Trends In Nanometer Age - P. 84
electrons
gammas
Flux in n/(MeV*cm2*s)
Neutron Energy Spectrum for
Atmospheric Cosmic Rays
1.E-02
1.E-03
varies with altitude
1.E-04
1.E-05
and geography
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
1.E-11
1.E-12
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Neutron Energy (MeV)
Flux n/(MeV*cm2*s)
n0-Si interaction can result in a short
range, intense burst of charge
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 85
Mechanism of Alpha Particle SER
Host material
(package, Si,
oxide, etc.)

Impurity in ppb 
amounts
(238U, 232Th, etc.)
Impurities
disintegrate in
alpha decay
Observed alpha
flux 0.01/h/cm2
-
Alpha
Particle
+
+
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-
electron is
stripped
from atom
The neutral
atom gains a +
charge
= an ion
86
Ch. 12 - Test Technology Trends In Nanometer Age - P. 86
Sources of alpha

alpha decay from radioactive
isotope Pb 210
 travel short distance, a few
centimeters
 but they are located at the
surface of the dies with C4
mounting

Traditional solutions, e.g.,
epoxy die coat, are not
effective
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 87
Shrinking Process Decrease Charge per Node
4
1
desktop Vcc
3
Cnode
Vcc
Qnode
0.1
2
1
Soft error is a function of stored charge
at sensitive nodes
Q=CV
i.e., Cnode and Vcc
0.01
Cnode/Qnode
(normalized)
mobile Vcc
How low will it go?
0
0.001
500
350
250
180
130
90
Technology node (nm)
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 88
RAM cell sensitive area
SER Critical area is drain/source
junction rather than metal
interconnect
Vcc
1
m
Not all diffusion
area are sensitive
Word line
Word line
Different junction
have different
sensitivity
characteristics
Bit line
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SER sensitive
junctions
Vss
SER sensitive
during read time
Bit Line
89
Ch. 12 - Test Technology Trends In Nanometer Age - P. 89
SER
α
 A diff (C gateVcc )
bit
Caches on CPU chip
%
Kbytes
30000
Itanium2
25000
Neutron Scaling Trends
Tech.
ADIFF
l
0.7x
l
20000
Scaling Factor
1
0.54
CGATE Vcc
1
0.75
1
SER / bit
15000
1
10000
0.7
1.08-1.45
0.8
0.92-1.18
Size of primary embedded cache (desktop)
5000
Size of primary embedded cache (server)
Itanium
0
Pentium
Pentium
Pro
Pentium II Celeron -A Pentium III
Pentium 4
Pentium4+
Core2Duo
This may lead to
false security
Doubling of devices every generation will double soft error rate as well !!
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 90
Logic Circuit
Subjected to SEU


Q
D
Logic is not immune to SER
 All feedback nodes are susceptible
 Typical hardening techniques will
pose performance penalty

Feedback loop exists
Clk
Latch is susceptible when in the
holding phase (50% of cycle)
F/F Master/Slave
typical D-latch
sensitive junctions
 Each is sensitive during its inactive
phase
Disturbance change
logic state permanently
Focuses on meta-stable window results in low probability event
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 91
SER Cannot be Screened During
Manufacturing



SER is recoverable error (if recomputed)
Most memory elements (with feedback) are
susceptible to SER (maybe to different degree)
Errors in compute elements may become SDC (silent
data corruption) or at best system crash (equally
undesirable)
 Low end system may be OK with a reboot; not acceptable
for a server
 SDC is the most vulnerable; won’t know unless computation
is repeated at another time
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 92
Redundancy - Spatial
Identical Compute elements

Spatial
 Duplication &
compare
 Triplicate & vote

Checkpointing and
rollback is a
common recovery
technique
Miscompare !
checker
Initiate rollback
Continue if correct;
Checkpointing regularly
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 93
Redundancy - Temporal

Temporal
 Assume error is not
persistent
 Recompute
everything (twice)
 First result
compare to second

Checkpointing and
rollback is common
recovery technique
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Compute element
Temporary storage
Compute
twice
1st result
stored
temporarily
2nd result
forward for
comparison
checker
Miscompare !
Initiate rollback
Continue if correct;
Checkpointing regularly
94
Ch. 12 - Test Technology Trends In Nanometer Age - P. 94
Redundancy - Information
parity

Error detection by
extra information
data
 E.g. parity
 Parity is preserved
through computation

Error correction by
extra information
 E.g. Hamming code
operation
Parity
should
match
result
One bit in a row
defective
ECC
check
bits
data
ECC logic
data
Defective bit, correct by ECC
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 95
Hierarchy of Protection

Start with most unreliable (and highest quantity)
elements
 DRAM (highest number of bits)
– Parity, ECC
 Hard disk (mechanical)
– RAID (Redundant Arrays of Identical Disks)
 IO Channels
– CRC, ECC
 Cache
– Parity, ECC
 Register files
– Parity
 Execution units
– DMR
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 96
Section 12.3.5
Defect and Error Tolerance
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 97
Defect Tolerance

Assumptions:
 Defect rate is low
 Most defects cause
single
cell/row/column
failures

Repair defect
elements using
redundant resources
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Redundancy Repair – An Example




Design in spare rows or
columns or blocks
Test to identify where
bad cell or row/column
is
Algorithm to figure out
how best to use spare
elements to repair all
defects
Fuse change decoders
to address spare
elements instead of
faulty elements
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spares
99
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Error Tolerance


Increasing new computing
applications are with
multimedia data
Compression is generally
used for these data types:
 E.g. MP3, JPEG, MPEG
 Lossy in nature
 Human senses are not
keen enough to spot the
difference


Errors may be tolerated for
these kinds of applications
Accepting more faulty chips
will increase effective yield
while lowering cost
re: Error Tolerance, Mel Breuer, 2005
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Section 12.4
FPGA Testing
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Field Programmable Gate Arrays

2-dimensional array
 Programmable logic blocks (PLBs)
 Programmable routing network
 Programmable I/O cells

Recent FPGAs incorporate
specialized cores
 Memory cores: RAMs, FIFOs, etc.
 Digital signal processors (DSPs)
 Embedded processors
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=PLB
=I/O buffers
=specialized core
=interconnect
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Basic PLB Architecture
 Look-up
Table (LUT)
 implements combinational logic truth table
 Memory
elements
 Flip-flop/latch
 Some LUTs also implement small RAMs
 Carry
and control logic
carry out
Input[1:4]
4
LUT/
RAM
Control
Carry &
Control
Logic
Flip-flop/
Latch
Output
Q output
clock, enable, set/reset
3
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carry in
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Programmable Interconnect Network
 Wire
segments of varying length
 xN = N PLBs in length
N = 1, 2, 4, 6, 8 are most common
 xH = half the array in length
 xL = length of full array
 Programmable
Wire A
config
bit
Wire B
Interconnect Points (PIPs)
 Transmission gate connects 2 wire segments
– Controlled by configuration memory bit
 Four basic types of PIPs
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Programmable Interconnect Points

Break-point PIP
 Connect or isolate 2 wire segments

Cross-point PIP
 2 nets straight through
 1 net turns corner and/or fans out

Compound cross-point PIP
 Collection of 6 break-point PIPs
– Can route 2 isolated signal nets

Multiplexer PIP
 Directional and buffered
 Main routing resource in recent FPGAs
 Select 1-of-N inputs for output
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Ranges of Programmable Resources
FPGA Resource
Logic
Routing
PLBs per FPGA
LUTs and flip-flops per PLB
Wire segments per PLB
PIPs per PLB
Bits per memory core
Specialized
Cores
Memory cores per FPGA
DSP cores
Other
Input/output cells
Configuration memory bits
Small
FPGA
Large
FPGA
100
1
50
80
128
16
0
62
32,000
22,000
4
400
1,000
18,432
500
500
1,200
50,000,000
Large FPGAs easily exceed 500 million transistors
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FPGA Testing Problem
 Must
test all modes of operation
 Many test configurations must be downloaded
 Long test time
 Large
and complex devices
 Large FPGAs exceed 500 million transistors
 Many different types of functions to test
– PLBs
– Routing resources
– Specialized cores (RAMs, FIFOs, DSPs, etc.)
 Frequently changing architectures
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FPGA Testing Approaches
 With
respect to system application:
 Application independent testing
– Test all resources in FPGA regardless of system
function to be implemented
 Application dependent testing
– Test only those resources that will be used by a
given system function
 Testing
techniques
 External testing
– Test patterns applied and output responses
monitored through I/O pins with external equipment
 Built-In Self-Test (BIST)
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BIST for FPGAs
 Basic
idea: reprogram FPGA to test itself
 No area overhead or performance penalties for
system applications
 Applicable
to all levels of testing
 From device-level through system-level testing
 Cost:
 Memory to store BIST configurations
– Goal: minimize number of configurations
 Download time to execute BIST configurations
– Goal: minimize downloads and/or download time
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BIST for PLBs
 Program
=TPG
=BUT
=ORA
PLBs as
 Test Pattern Generators (TPGs)
– Multiple TPGs prevent faulty PLBs
under test from escaping detection
when there is a fault in a TPG PLB
Test session 1
 Identically configured logic blocks
under test (BUTs)
 Output Response Analyzers (ORAs)
– Comparison-based
 Row
or column orientation
 Two test sessions required
Test session 2
BUTi output
BUTj output
 TPGs/ORAs and BUTs reverse rolls
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Pass/
Fail
ORA
110
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BIST for Routing Resources
 Program
groups of wire segments
and PIPs as wires under test
 Program some PLBs as TPGs wires under test
and ORAs
T N
 Similar to BIST for PLBs
 Two
P
G
– Similar to BIST for PLBs
 Parity-based
Cnt0
T ...
P CntN
G
Parity
wires under test
..
.
Pass
Fail
ORA
parity-based BIST
– TPG produces test patterns with parity
– ORA performs parity check
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ORA
comparison-based BIST
BIST approaches
 Comparison-based
N
Pass
Fail
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Concluding Remarks
 FPGAs
are more SoC-like with
specialized cores
 RAMs, DSPs, etc. can be tested with
approach similar to BIST for PLBs
 SoCs
are incorporating FPGA cores
 These cores can be tested with BIST for
FPGA techniques
 Complex
Programmable Logic Devices
(CPLDs) are similar to FPGAs
 Can be tested with approaches similar to
those used for FPGAs
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Section 12.5
MEMS Testing
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Introduction to MEMS

What is MEMS?
 MEMS: Micro Electro Mechanical System

Extremely small (in range of um) devices utilizing
both electrical and mechanical properties.
MEMS gear chain and a mite for size comparision
(Sandia MEMS)
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Video Clips from Sandia MEMS
 A micro-resonator
is used as an
actuator to drive MEMS gears with
mites crawling on top.
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Commercially Available MEMS Devices
Digital Micromirror Device (DMD)
(Texas Instruments, Inc.)
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MEMS ink jet print head (nozzle)
(HP, Inc.)
116
Ch. 12 - Test Technology Trends In Nanometer Age - P. 116
Commercially Available MEMS Devices
ADXL50 accelerometer “LambdaRouter” optical switch
(Analog Devices, Inc.)
(Lucent, Inc.)
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Why MEMS?

Why MEMS?






Lower cost due to batch fabrication
Light weight
Smaller size
Lower energy consumption
Higher performance
MEMS applications






Automobile industry
Health care
Aerospace
Consumer Products
RF telecommunications
Other areas
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World MEMS Market Prediction


Worldwide MEMS market is increasing rapidly.
Worldwide MEMS sales > $5 billion in 2004,
> $8 billion in 2007.
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Basic Concepts for Capacitive MEMS Devices
 0S
C
1  C2 
 In static mode:
d 0 where
  0 : dielectric constant of air
 S: overlap area between M and F1/F2
 d0: static capacitance gap between M and F1/ F2
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Basic Concepts for Capacitive MEMS Devices
C2 

 0S
(d 0  x)

 0S
d0
(1 
x
)
d0
Assume Vertical stimulus force causes movable
mass M to move upward with displacement x, where
x << d0
( x  d0 ) d0
d
C1 

(1  0 )
S 0
S 0
x
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 0S
 0S
x
C2 

(1  )
(d 0  x) d 0
d0
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Basic Concepts for Capacitive MEMS Devices
C2 

 0S
(d 0  x)

 0S
d0
(1 
x
)
d0
To sense displacement x, modulation voltages Vmp and Vmn
are applied to F1 and F2 respectively
VF 1  Vmp  V 0 sqr (t )
VF 2  Vmn  V 0 sqr (t )
Where V0 is modulation voltage amplitude, w is freq of
modulation, t is time for operation, sqr is square waveform
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Basic Concepts for Capacitive MEMS Devices
C2 

 0S
(d 0  x)

 0S
d0
(1 
x
)
d0
According to charge conservation law,
C1(VF 1  VM )  C 2(VM  VF 2)
where VM is voltage sensed by movable plate M

Solve the equation:
VM  ( x / d 0)V 0 sqr (t )

By sensing Vm, we find displacement x.
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MEMS BIST Research

Statement of problem: MEMS testing is
becoming an urgent need.
 MEMS is finding applications in safety-critical
areas, such as automobile, aerospace, medical
instruments, etc.
 MEMS will be integrated into SoC, so it needs to
be thoroughly tested to ensure reliability.
 The commercialization of MEMS technology
needs a thorough and efficient testing solution in
order to ensure reliability and reduce the test cost.
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MEMS Testing: A Challenging Topic

MEMS testing is chanllenging:






multi-field coupling
diversity in device structure & working principle
analog signals involved
vulnerable to various defect souces (stiction, etch variances,
particle contamination, etc.)
Just like VLSI testing, built-in self-test (BIST) is
believed to be a promising solution for MEMS
testing.
Research goals: develop a robust and efficient BIST
solution for capacitive MEMS devices.
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MEMS Sensitivity BIST Scheme

How to generate test stimulus for MEMS?
 Apply voltage Vd to F1 and nominal voltage Vnom to M
 Electrostatic force Fd will be experienced where
2d 0 2
Fd 
 0 SVd 2
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MEMS Sensitivity BIST Scheme
 The
force will result in a displacement x.
 The sensitivity BIST scheme requires
another similar structure to sense the
displacement x.
 Sensed VM is compared with a known
value for comparison.
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Symmetry BIST for Capacitive MEMS
Vmp  V 0 sqr (t )  Vmn
C1(Vmp  VM )  C 2(VM  Vmn)
VM  Vmp(C1  C 2) /(C1  C 2)
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Symmetry BIST for Capacitive MEMS (cont.)




For a fault-free Device:
 C1=C2, then VM=0
 If C1 ≠C2(faulty): VM≠0
Fixed capacitance plates are partitioned into two equal portions
(S1, S2 in top and S3, S4 in the bottom).
During symmetric BIST, always check VM=0?
Local Defect causing left-right asymmetry is detected.
* Partitioning by movable plate: see N. Deb and R. D. (Shawn) Blanton,
“Built-in Self Test of CMOS-MEMS Accelerometers,” ITC02, p.1075.
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Capacitance Partition for Dual-mode BIST
S1 D1
S2
S1
C1
C1
M
C2
C2
C3
C4
M
S2
S3
D2 S4
(a) Typical MEMS (b) Capacitance partition
differential capacitance for dual-mode BIST

In Fig (b)
 S1, S2: top sensing
plates,
 S3, S4: bottom sensing
plates,
 D1,D2: driving plates
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
In Fig (b) cont.
 M: movable plate
 C1, C2: top sensing cap.
 C3, C4: bottom sensing
cap.
130
Ch. 12 - Test Technology Trends In Nanometer Age - P. 130
Capacitance Partition for Dual-mode BIST
S1 D1
S2
S1
C1
C1
M
C2
C2
C3
C4
M
S2
S3
D2 S4
(a) Typical MEMS (b) Capacitance partition
differential capacitance for dual-mode BIST



Fixed plate at each side of the movable plate is
divided into three portions: 1 for electrostatic driving,
other 2 equal portions for capacitance sensing.
The movable capacitance plate is not partitioned.
Sensitivity and symmetry BIST can be implemented.
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Voltage Biasing Scheme of Dual-Mode BIST



D1 & D2 also participate the normal operation.
Analog switches are used for mode-switching.
Any defect causing sensitivity change or left-right asymmetry will
be detected.
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MEMS Comb Accelerometer


Device prototype ADXL50 by Analog Devices Inc.
The serrated comb finger groups are extremely
vulnerable to defects, thus BISR is highly desirable.
Comb accelerometer without BISR
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Working Principles of Accelerometer

Uses differential capacitance sensing technique

Vmp (Vmn): Complimentary
modulation voltages
v 0( Lf  )h v 0( Lf  )h
x

(1  )
( d 0  x)
d0
d0
v 0( Lf  )h v 0( Lf  )h
x
C2 

(1  )
(d 0  x)
d0
d0
C1 
C1(VF 1  Vm)  C 2(VM  VF 2)
VM  ( x / d 0)V 0 sqr (t )
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 134
Working Principles of Accelerometer
(cont.)


VM is proportional to displacement x, which is in turn
directly proportional to acceleration a.
By sensing VM, the value of a can be measured.
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BIST for Comb Accelerometer
Driving
Fingers
D1
D3
D2
D4
S1
S3
S2
S4
M2
M5
M2
Sensing
Fingers
M6

Ms
S5
S7
S6
S8
D5
D7
D6
D8
M3
Driving
Fingers

M7
M4
M8

Voltage
Biasing
Vd
Normal
Operation
Sensitivity
BIST
Symmetry
BIST
-
D1,D3,D5,D7
D1,D3,D5,D7
-
D2,D4,D6,D8
M1,M4,M5,M8
D2,D4,D6,D8
M1,M4,M5,M8
S2,S4,S6,S8
Vnom
Vmp
S1,S3,S5,S7
D1,D3,D5,D7
S1,S3,S5,S7
S1,S5
Vmn
S2,S4,S6,S8
D2,D4,D6,D8
S2,S4,S6,S8
S3,S7
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

Device prototype:
ADXL50
Since fixed plates are
separated comb
fingers, the partition
can be easily realized.
M1-M8: movable plates
D1-D8: fixed driving
plates
S1-S8: fixed sensing
plates
136
Ch. 12 - Test Technology Trends In Nanometer Age - P. 136
ANSYS Fault Simulation* of Comb Accelerometer
Stiction defect simulation result
Defect
location
Frequency
(kHz)
Sensitivity
BIST(mV)
Symmetry
BIST(mV)
Defect-free
11.85
967.6
0
0%
28.80
107.8
2.5
10%
32.75
82.2
2.1
20%
39.23
56.4
1.6
30%
46.80
39.2
1.2
Finger height mismatch simulation
Height mismatch
H (um)
Frequency
(kHz)
Sensitivity
BIST(mV)
Symmetry
BIST(mV)
Defect-free
11.85
967.6
0
0.1
11.85
951.8
42.9
0.2
11.85
937.1
83.9
0.3
11.85
921.8
128.2
0.4
11.85
904.4
181.3

Stiction (on right
central movable
finger): sensitivity
BIST is more efficient.

Finger height is
matched (only in right
portion): symmetry
BIST is more efficient.
* For definitions of simulated defects, see paper at ITC02, p.1075.
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Conclusions of Dual-Mode BIST



By partitioning fixed instead of movable capacitance
plate, the BIST technique can be extended to bulkmicromachining and other MEMS technologies.
Each sensitivity and symmetry BIST has its own fault
coverage. A combination of both ensures better
coverage.
Sensitivity BIST is necessary during in-field usage
even after calibration.
 Some unstable defects may change status.
 New defects may be developed in in-field usage.
 Stiction is also possible during in-field usage.
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Ch. 12 - Test Technology Trends In Nanometer Age - P. 138
Section 12.6
High-Speed I/O Testing
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I/O Test Requirements and Architectures
I/O test requirements are largely driven by the
interoperability, system performance, and
functional performance goals.
 I/O test requirements are closely related to the link
architectures.
 For data rates < 1 Gbps, global common clock
(CC) and source-synchronized (SS) are popular.
 Above 1 Gbps, serial architectures are dominant
 Timing, voltage, and bit error rate (BER) are
common testing parameters.

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I/O Architecture (I) Common Clock (CC)
 Synchronized
global (common) clock
 Common clocks for Tx data driving and Rx
data sampling
 Clock skew on board limits its use to < a
few 100 Mbps data rate
 Needs to test:
Data to clock delay at Tx
Setup/hold time at Rx
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I/O Architecture (I) Common Clock (CC)
Period




Synchronized global
(common) clock
Common clocks for
Tx data driving and
Rx data sampling
Clock skew on
board limits its use
to < a few 100 Mbps
data rate
Needs to test:
 Data to clock delay
at Tx
 Setup/hold time at
Rx
Clock
at driver Data 0
Data1
Tco
flight time
Tsetup Thold
Data1
at receiver
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Reference to external clock source
Tester is programmed to provide clock
142
Ch. 12 - Test Technology Trends In Nanometer Age - P. 142
I/O Architecture (II) Source Synchronous (SS)
Tx sends
data along
with strobe
(another
clock)
 Rx uses
sent strobe
to sample
the data
 No clock or
strobe
skew issue

Dx
data
clock domain 1
clock domain
2
wire delay
strobes
wire delay
Strobe
One set of strobe/strobe#
per group of data pins
system clock
Bus Clock
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board trace delay A
board trace delay B
143
Ch. 12 - Test Technology Trends In Nanometer Age - P. 143
I/O Architecture (II) Source Synchronous (Cont’d)
Data
All driven
by
same bus
clock
& matched Strobe
signal
paths
Tvb
Tva
Tvb
Tva
Tsetup Thold
Strobe#


Some designs use strobe/strobe# to improve timing accuracy.
Needs to test
 Data valid before and after strobe at Tx end
 Setup and hold times at Rx end
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I/O Architecture (II) Source Synchronous (Cont’d)

Skew due to
mismatches/noises
Limited by data to
data skew due to
uneven channels
 Board layout
 E-M issues: e.g.,
coupling, noises
 Variation in drive
among channels

A
B
C
Achieve up to
~1000 Mbps data
rates for wide bus
 Can improve data
rate with splitting
into many narrower
bus
D
E
Strobe Clk
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setup/hold
145
Ch. 12 - Test Technology Trends In Nanometer Age - P. 145
AC IO loopback self-test
Dx
driver
clock dom ain 1
clock domain 2
data
latch
wire delay
strobes
wire delay
receiver
latch
Strobe
Similar circuit as the receiving end!
Testing hardware already exists!
-- test for both drive/receive
system clock
-- low overhead
Bus Clock
board trace delay
board trace delay
Loop time = Tco (or Tvb) + Tsetup OR Tva+Thold
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bus group
Defect-based
IO test
Strobe
delay
good buffers distribution
stress to fail by
pushing
strobes to the data
edge
(driver or receiver)
buffer group
should have tight
distribution

A wider
spread of
data valid
time indicate
faults
faulty buffer
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wider distribution => local
defective buffers
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I/O Architecture (III) Serialier/Deserializer (SERDES)
Rx
recovered data
system clock
clock
multiplier
serial to
parallel
decoder
bit rate clock
recovered clock
Channel
parallel
to serial
encoder
Tx
serial data
incoming signals
(with embedded clock)
Clock
Recovery
parallel data



Bit clock is embedded in the serial data and gets
recovered at Rx via clock recovery circuit.
Link layer is composed of encoder and decoder.
Physical layer (PHY) is composed of Tx, channel, and
Rx.
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I/O Architecture (III) A SERDES PHY Implementation
Ref Clock
(100 MHz)
+
Channel
-
Rx
Tx
D
PLL
25X
D
PI
C
Rx eye
Closure
Q
Data
out
C
PLL
25X





Bit clock is recovered via a phase interpolator (PI) clock recovery.
PI clock recovery tracks low frequency jitter from reference clock, Tx, and
channel.
“Differential” PLLs reduce the jitter from reference clock.
Used widely in PCI Express (2.5 Gen I, 5.0 Gbps Gen II) and FB DIMM (3.2,
4.0, and 4.8 Gbps Gen I).
Jitter is the major limiting factor/performance metric.
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Jitter Components and Terminology
Jitter
Deterministic
Jitter (DJ)
Data Dependent
Jitter (DDJ)
Duty Cycle
Distortion
(DCD)
Random Jitter (RJ)
Periodic
Jitter (PJ)
BUJ
Gaussian
(GJ)
MultiGaussian
(MGJ)
Inter-symbol
Interference
(ISI)
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Eye-Diagram, Jitter, and Noise Testing

For output
testing, jitter and
noise probability
density functions
(PDFs), and eyeopening should
be upper
bounded.

For input
tolerance testing,
jitter and noise
PDFs, and eyeopening should
be lower
bounded.
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Noise PDFs
Jitter PDFs
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Summary
Link architecture determines the relevant test
parameters and methods.
 For synchronized CC and SS architectures,
critical test parameters include:

 Data valid to clock/strobe
 Setup/hold time

For a SERDES architecture, critical test
parameters include:
 Jitter, includes deterministic jitter (DJ), random jitter
(RJ), and total jitter (TJ) or timing eye-opening
 Noise, and voltage eye-opening
 Bit error rate (BER)
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Chapter 12.7
RF Testing
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Outline of the Section

Introduce the basic concepts related to RF

Discuss the various challenges associated with RF
test

Describe different core RF building blocks

Elaborate various test specifications for RF devices

System-level testing and associated specifications

Conclude with present and future trends
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Introduction to RF

RF stands for ‘Radio Frequency’
 Usually very high frequencies where signals can
be transmitted wirelessly
 Range of frequencies  300MHz ~ 3GHz

RF is used synonymously with ‘wireless’

Significant growth during the last decade in
the consumer segment
 Increased consumer applications
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Applications of RF

Earlier, consumer applications of wireless
technology were limited
 Military, space communications, air traffic control

Currently, consumer applications are on the
rise
 Cell phone, laptop, PDA, satellite radio
 Radiofrequency identification (RFID)
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Challenges with RF testing

Tests are performed in two steps
 Characterization test
 Production test


Various challenges make production test hard and
expensive
RF devices need extra attention during testing
(challenge #1)
 Impedance matching @ input and output ports to ensure
optimal power transfer
 Shielding from external wireless signals during testing
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Characterization test


Characterization validates the first set of silicon
Uses highly accurate instruments to
 Verify the functionality of the design
 Ascertain that the specifications are met
 Ensure high repeatability of the measurement system

Production test needs to perform all of the above with
 Cheaper instrumentation  a least-cost commercial tester
(challenge #2)
 In much smaller duration of the time used for
characterization (challenge #3)
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Repeatability and accuracy issues

Test procedure should classify:
 ‘Good’ devices as ‘good’ and
 ‘Bad’ devices as ‘bad’

This is constrained by measurement noise
 Reduces the accuracy of measurement during production
testing (challenge #4)
 Introduces large variability in the same measurement
repeated many times (challenge #5)

These can be mitigated by using
 Accurate test application procedure
 High resolution measurements
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Summary of challenges

Challenge #1 is very specific to RF devices  needs
careful measurement setup

Challenge #2 and 3 are also specific to RF
 RF testers are very expensive (> $1M) compared to the
analog and digital counterparts
 RF tests are usually longer compared to analog tests

Challenge #4 and 5 are general for all electronic
devices
 However, these are more prominent in RF due to the large
amount of noise involved
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Typical RF system
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RF specifications

Linearity specifications
 Gain, conversion gain, output power

Non-linearity specifications
 Third-order intercept (TOI), adjacent channel power ratio
(ACPR)

Noise specifications
 Noise figure (NF), signal-to-noise ratio (SNR), sensitivity,
dynamic range

System specifications
 Error-vector magnitude (EVM), bit error rate (BER)
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A note on decibel

Decibel is a very commonly used unit in wireless
domain
 Notation for decibel  dB
 Any number N can be converted to decibel by
NdB = 20 log10(N)

A similar unit is mili-decibel (notation  dBm)
 Used to denote power with reference to 1 mW
 P watts of power is converted to dBm by
PdBm = 10 log10(P/1 mW)
 Thus 1W = 1000mW = 30 dBm; 10W = 0.01mW = -20 dBm
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Gain

Measures the small-signal gain of the device/system

Input is a single-tone stimulus within the operating
frequency

Amplitude is within linear range of operation

Gain = (Output amplitude / Input amplitude), usually
expressed in dB
A2
A1
f1
f1
Gain = A2/A1
= 20 log10(A2/A1), in dB
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Conversion Gain

Measures the small-signal gain of mixers
 Mixers translate the input frequency at a different output
frequency


Input is a single-tone stimulus within the input
operating frequency, amplitude within linear range of
operation
Gain = (Output amplitude @ f2 / Input amplitude @f1),
usually expressed in dB
A2
Different
frequencies
A1
f1
f2
Gain = A2/A1
= 20 log10(A2/A1), in dB
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TOI

Measure of nonlinearity for a device/system

Two-tone input, within operating range
 Frequencies are closely spaced, difference is usually <1% of
the device bandwidth

Amplitude is larger than linear range of operation

TOI = Pout + |(Pout – PIMD)/2|
Fundamental tones
Pout
DUT
f1
PIMD
f2
f1
2f1 - f2
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Intermodulation tones
f2
2f2 - f1
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A note on TOI

Third-order nonlinear term
Usually, RF devices exhibit
third-order nonlinearity
y(t) = A0 + A1x(t) + A3x(t)3

TOI is denoted in dBm
 It indicates the output power
level where the fundamental
tones and intermodulation
tones attain same power
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Basics of SNR

SNR is an important factor for any signal
(-23) – (-73) = 50 dB
Amplitude
 SNR for a known signal can be easily computed
 SNR denotes the level of purity
-23 dBm
 For this sinusoid, SNR = 50 dB
-73 dBm
Frequency

This notion can be extended to any known
signal
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Noise figure

Noise figure measures the degradation of
SNR of a signal when it passes through the
DUT
 Noise figure = SNRin/SNRout
 This indicates the amount of noise added by the
DUT
 NF is usually measured in dB (it’s a ratio !!)

NF is measured using NF meter
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System-level test : ACPR


ACPR test provides an idea of the overall nonlinearity
of a system
Why is ACPR important ?
 In communication systems, information is transmitted in
channels (a fixed span of frequencies)
 Many devices communicate simultaneously in different
channels
 If power leaks from one channel to other, both channels may
result in erroneous transmission
Power leakage to adjacent
channels due to nonlinearity
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ACPR Test

Pseudo-random bitstream is transmitted from the
DSP to test for ACPR
 This ensures all frequencies within the channel are equally
likely
Test setup for
ACPR

ACPR is the ratio of total power within the desired
channel and the adjacent channel
 Usually denoted in dB
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EVM test

RF systems employ modulation during transmission
 Helps in protecting information from transmission channel
noise

Inaccuracies in channel can cause
 Amplitude error
 Phase error
 AM-PM or PM-AM modulation

EVM is an aggregate measure of all the above
effects
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EVM test

As done in ACPR, PR sequences are transmitted and
received back during EVM test

Use the demodulated data symbols to compute EVM

EVM is the RMS of the received symbols compared
to the actual symbols
 Need to use a large number of symbols to obtain a
statistically correct value
 The amplitudes are normalized for systems employing
phase-amplitude based modulation (e.g. 16-QAM, 64-QAM)
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EVM measurement
Ideal
symbol

The symbols for phase
modulated systems should lie on
a circle
 Deviations from the circle
indicate presence of magnitude
error + noise of the system
 Rotation of the symbols indicate
phase error
 Non-uniform rotation indicates
improper group delay present in
the system (usually from
passives)
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Actual
symbol
received
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EVM (contd.)

EVM is calculated using the following formula
EVM RMS

1
 
N
N
 Videal,i  Vmeasured,i
i 1
2
 1
 
 N
2
V

ideal,i 
i 1

N
EVM is a very good indicator
of the overall system health
 Typically, EVM is within 3-15
%
 This figure shows EVM for a
QPSK system
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Concluding remarks

RF test cost is on the rise
 It is estimated that test cost can be up to 40%
unless new techniques are developed
 RF test is constantly gaining attention from
industry and academia
 RF testers are extremely expensive with limited
functionalities compared to analog or digital
testers

In this light, innovative solutions are needed
to overcome RF test challenges
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Future trends

Defect-based test of RF devices can provide a quick
estimate in a production test environment
 However, it does not provide any info about specifications

Use of low-cost instrumentations/ATE to perform
complex tests
 Example, using a multi-tone signal to measure EVM (no
transmitter needed)

Use alternate measurements/BIST to facilitate test
procedure
 Can significantly reduce cost of testing + time required to
test
 Minimizes the requirements of the tester
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Section 12.8
Concluding Remarks
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Conclusions




ITRS challenges for test, test equipment, and design
test have been reviewed.
Promising techniques for delay testing; coping with
physical failures, soft errors, and reliability issues;
FPGA testing; MEMS testing; high-speed I/O testing;
and RF testing have been briefly reviewed.
BIST/BISR must be pushed to deal with most circuits
from digital circuits to analog and mixed-signal
circuits.
Other important test techniques, such as softwarebased self-test, design for manufacturability (DFM),
design for yield enhancement (DFY), and design for
debug and diagnosis (DFD) must be researched.
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