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CAE tools and technology challenges
in making deep sub-micron IC designs
ESE Group seminar 30/3/2010
Kostas Kloukinas
CERN, PH-ESE dept.
CH1211, Geneve 23
Switzerland
Overview

Technology Challenges

Modern CAE Tools

IC design CAE tools at CERN
30/3/10
[email protected]
2
How it all got started….
10 cm process
.35 um process
30/3/10
[email protected]
3
…and the story continues…
CAE Tools co-evolved with process technology
30/3/10
[email protected]
4
What drives CAE tools Innovation
Design
Challenges
Technology
Challenges
Productivity
Requirements
CAE
Tools
30/3/10
[email protected]
5
CAE tools have to coop with:
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Deep Submicron effects “Black List”
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Numerous and Complicated Design Manufacturing Rules
Leakage currents of devices
Interconnect parasitics
Process Variations
Process Fault modes and Design For Manufacturability (DFM)
Design Challenges
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System On Chips (SOC) and IP Reuse
Low Power Design techniques
Formal Design Methodologies
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30/3/10
Digital design flows
Analog and Mixed Signal flows
Hierarchical Implementation flows
Advanced Verification Techniques
[email protected]
6
Complicated Design Rules
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Design Manual page count:
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Design Rule Check deck files:
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250nm: 5,300 lines
130nm: 13,500 lines
90nm: 38,400 lines
65nm: 89,300 lines
One single verification tool is not capable any more
to detect all DRC violations!

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250nm: 170 pages
130nm: 600 pages + numerous application notes
Foundries require design sign-off verification using independently two
verification tools from two different vendors.
Tools make use of parameterized cells (Pcells) and
automated “analog routers” to assist layout work and
increase design productivity.
30/3/10
[email protected]
Parameterized cell
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Full Custom IC Assembly Router
Tool: Cadence Virtuoso Chip Assembly Router
to augment design productivity.
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Features and Benefits
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Device, cell, block and top-level chip
assembly routing support.
Design constraint and process rule driven
Interactive signal routing
Multi-net/bus routing support
On the fly Design Rule checking
Variable Width and Spacing rules
Automated signal routing
Automated special net shielding
Requirements:

30/3/10
Support from foundry PDK with
technology specific design rules and
constraints.
[email protected]
8
Leakage currents affecting Power
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Digital Circuit Power Dissipation
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Dynamic Power dissipation
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Static Power due to leakage currents
Leakage currents in deep submicron
technologies:
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Short circuit power
Switching power
P = C * f * V2dd
Gate tunneling leakage (a)
Sub-threshold leakage (b)
Reversed biased PN junction leakage (c)
Gate Induced Drain Leakage (b)
Leakage Power is a significant
component of the total power dissipation
in 90nm technologies and below.
30/3/10
[email protected]
9
Multiple VT standard cell libraries
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Multiple VT standard cell libraries.
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High VT cells for low power
Low VT cells for high performance
Nominal VT cells for general purpose.
Logic synthesis
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High performance strategy
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Low power strategy
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Synthesize with High VT libraries
and then optimize with Low and Nominal.
Integrated strategy
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Synthesize with Low VT libraries
and then optimize with High and Nominal.
Synthesize with all libraries concurrently.
State-of-the-art synthesis tools, like Synopsys “Design
Compiler” or Cadence “RTL Compiler”, support multi VT
synthesis. Efficient synthesis is obtained when it is
implemented at a cell level (not block level).
CAE tools have to deal with:
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30/3/10
Multiple libraries of 1,000s of cells
Highly customized design flows.
[email protected]
10
Low Power Design (1/6)
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Multi Voltage Libraries
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Level Shifter cells
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Power down idle blocks to reduce leakage currents.
Requires special power control cells (switches) as well as isolation and state retention cells.
Dynamic Voltage and Frequency scaling.
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Each power domain receives the voltage swing it expects.
Power Gating
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Different fixed supply voltages
depending performance requirements.
Requires standard cell libraries
characterized at different supply voltages
Voltage and frequency dynamically adjusted in response to changing workloads.
High-Low
Applicable to processors and microcontrollers.
Level Shifter
CAE tools are required to handle:
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Multiple standard cell libraries characterized at different
power supply voltages.
Floorplanning and special power rooting.
Multi modes, Multi Voltage of operation.
30/3/10
Low-High
Level Shifter
[email protected]
Floorplanning with Level Shifters
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Low Power Design (2/6)
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Power Switch cells
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In a power gating design, sleep transistors are
used as switches to shut off power supplies to
parts of a design in standby mode
Power Grid floorplanning
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Ring Style floorplanning
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Better IR drop management & area optimization.
Complexity in Physical Synthesis and Power Routing.
Less complex P&R especially for existing hard IP blocks
For large blocks the IR drop in the center can be high.
Isolation & State Retention cells
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30/3/10
Isolation logic is typically used at the output of
a powered-down block to prevent floating,
unpowered signals (represented by unknown
or X in simulation) from propagating from
powered-down blocks.
To speed power-up recovery, state retention
power gating flops can be used to retain their
state while the power is off.
Power grid distribution
[email protected]
Ring style distribution
12
Low Power Design (3/6)
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Control of the substrate voltage
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Basic Principle:
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Increase the back gate voltage to increase VT and
thus decrease leakage.
Decrease the back gate voltage to decrease VT and
thus increase performance at the expense of leakage
power consumption. (Difficult & risky approach)
Special Tap cells (fill cells)
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Back or forward biasing for
performance/leakage optimization
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Correct well/substrate voltages in case of
on-chip power gating
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30/3/10
N-well voltage different from VDD
Substrate or P-well (triple well process) voltage
different from VSS
Bias voltage routed as signal pin or special power net
Well pins connect wells to always-on power supplies
Keep wells “alive” when island is power down
VNW must connect to always-on power when using
“header” power switches.
VPW must connect to always-on power when using
“footer” power switches.
[email protected]
13
Low Power Design (4/6)
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Clock Gating
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Useful when data only loaded infrequently.
No dynamic power when clock is stopped.
Transformation to the 2nd implementation can be
done automatically by the CAE synthesis tool.
Integrated Clock Gating cells (ICG) are special
standard cells that ensure a predictable clock gating
behavior.
Controlled with tool specific settings.
Can use normal standard cells but timing issues are
always a hazard.
Clock Gating: Cloning & Decloning
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30/3/10
You can even reduce the power some more by
moving the clock gating cells to higher levels in the
hierarchy and combining them as much as possible.
[email protected]
14
Low Power Design (5/6)
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Operand Isolation (Data Gating)
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Gate level power optimizations
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Cell sizing
Buffering
Pin swapping
Factoring
Implementation choices for Data Paths
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Holding inputs to combinatorial blocks constant when
their outputs are not required.
Reduces power by preventing switching activity
Multipliers
Adders
Bus Encoding
Pipelining
Asynchronous Logic Design
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30/3/10
Extremely hard work with practically no support
from CAE tools!
[email protected]
15
Low Power Design (6/6)
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Power intend description languages
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Universal Power Format (Synopsys)
Common Power Format (Cadence)
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Power aware simulation
Power aware synthesis
Power aware verification
Power aware implementation
Power aware logic equivalence check
Power aware sign-off
[email protected]
16
Interconnect Parasitics
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Increased number of metal layers at finer pitch.
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The wire interconnect dominates timing
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Metal interconnects have smaller widths,
taller heights, shorter intra-layer spacing.
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Gate delay equals to interconnect delay at 130nm.
In 350nm, wire to substrate capacitance was dominant.
In 90nm, wire to wire capacitance is dominant.
Increased complexity of interconnect
parasitic device extraction:
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30/3/10
Copper wire distortions caused primarily due to
CMP (Chemical Mechanical Polishing) results in
irregular trapezoid conductors.
Below 90nm wireline variations require
(min/typ/max) extraction.
[email protected]
17
Signal Integrity issues
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Crosstalk in Deep Submicron
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Crosstalk induced Noise
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The aggressor net causes glitching on the victim net.
If the glitches coincide with clock edges
then errors occur.
Crosstalk induced Delay
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Smaller geometries increase coupling
Technologies have gotten faster.
Edge rates are much higher,
increasing the likelihood of crosstalk
and worsen power/ground bounce.
Chips are much more complex,
increasing the likelihood of long parallel wires.
Causing signal to speed up or slow down.
CAE Tools involved:
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30/3/10
Interconnect parasitic extraction engines.
Static Timing Analysis engines
Timing Optimization engines (buffer resizing)
Place & Route engines (net reordering, wire spreading)
[email protected]
18
Evolution of Digital Libraries
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More accurate Timing Libraries
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Above 90nm NLDM is good enough
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Below 90nm Current Source models in use
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NLDM (Non Linear Device Model) “liberty” files (.lib)
Interconnect capacitance > cell drive impedance.
Non linear switching waveforms.
Input pin capacitance becomes a function slope.
Current sources are more effective at tracking
non-linear switching waveforms.
Timing, Noise and Power calculations.
ECSM (Effective Current Source Model) by Cadence
CCS (Composite Current Source model) by Synopsys
More Libraries due to:
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Multi-VT options
Multi-voltage options
Multi-corners due to process parameters:
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30/3/10
Tox, VTh variations
Interconnect variations
[email protected]
19
MMMC analysis & optimization
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Static Timing Analysis & Optimization
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Many Modes of operation
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Process Variations
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Interconnect corners
Device VT corners
Range of Voltage & Temperature conditions.
Traditional method
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Functional modes
Low Power design techniques
Single mode/corner analysis
Design for worst case conditions
Still good for 90nm
Overdesign or non-converging solution for < 65nm.
MMMC: Multi Mode Multi Corner
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30/3/10
“Scenario” (PVT+Mode+Parasitics) based approach.
Optimization runs concurrently on all “scenarios” .
Tools identify “dominant scenarios” performing
automated “scenario” reductions.
[email protected]
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Design for Variability
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Process Variations
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Traditional Static Timing Analysis
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Random dopant fluctuations affecting VTH
Lithography (metalization)
Intra-die variations
Wafer- level, wafer-to-wafer, lot-to-lot variations
Difficult to meet timimg
Too pessimistic => overdesign.
Statistical Static Timing Analysis
(SSTA)
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RC extraction with sensitivites
Uses sensitivities to find correlations among delays.
Uses these correlations when computing how to
add statistical distributions of delays.
Needs libraries supporting statistical timing
30/3/10
[email protected]
21
Design for Reliability
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IR drop refers to fluctuations of the supply
voltage over the length of the supply line.
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For IC design we consider both static &
dynamic IR drop.
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Electromigration
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EM problems occur when the power grid is not
sufficient to handle the current densities required by
the design.
On the signal nets driven by high drive strength
cells if the wires are too narrow,
On the power grid when several large current
hungry cells are placed near to each other and are
fed by inadequate power grid routing.
CAE Tools
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30/3/10
Synopsys: PrimeRail
Cadence: VoltageStorm
Animated voltage drop maps
[email protected]
22
Automated Power Grid Design
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PNA: Power Network Analysis
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Manual Power Planning
Provides early estimation of the final sign-off
analysis.
“Virtual rails” that are not simulated,
only higher metal layers are considered.
“What if” analysis varying number of straps,
width of straps, placement of pads, etc.
Iterations to achieve target constraints.
Power Network Analysis
PNS: Power Network Synthesis
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30/3/10
Attempt to eliminate the manual work!
PN constraints describe the design targets like
total IR drop, as well as provide guidelines for
the layout of the grid.
PNS is quite often an iterative process.
Once the IR-drop and EM maps look ok the
power plan can be committed and the physical
straps and rings can actually be laid down.
[email protected]
Power Network Synthesis
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Flip Chip Solutions
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RDL flow
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Wirebond pads placed at the periphery.
Redistribution wiring layer to connect to ball pads.
Area Array flow
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30/3/10
Special C4 IO pads placed in designated “sites” inside the chip area.
Special short signal routing.
Special concerns for the placement of ESD structures
[email protected]
24
Design For Manufacturability
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Antenna Violations
To prevent damage caused by charge build-up on MOS
gates (during plasma etch processing steps), which
causes damage to the MOS gate oxides
If you fail to fix antenna violations, you will end up with
plasma induced gate oxide damage.
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Max Metal Width Rules
To prevent large areas of metal from lifting off during
processing due to differences in thermal co-efficient (metal
and substrate will expand by different amounts)
Reduces the effects of Electro-migration.
Slotting/Cheesing wide wires
or Splitting wide wires into multiple smaller wires.
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Pattern Density Rules
To reduce dishing and erosion of the inter-level dielectrics,
requires metal lines to be at a certain minimum distance
from each other (metal density). This leads to the so
called metal fills (dummy metal)
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30/3/10
The cause of many design Tape Out delays!
Early consideration of pattern density rules is essential.
[email protected]
25
Layout Sign-Off Tools
30/3/10
[email protected]
26
IDESA - IC Design Skills for Advanced DSM Technologies
Sign-off Evolution: Growing Importance of Sign-off
Example
1X
Complexity
Should be predictable
180nm
130nm
30-40X
complexity
Conservative design
90nm
65nm
Design Schedule
Future Project – 40  32nm
Design Schedule Variability Due to Sign-off
?
© IDESA 2007 |
Analog & Mixed Signal Flows
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The Concept
Top-Down Functional Design
Early chip level verification strategy has to be
in place and validated with correct partitioning
between analog and digital.
As the project is proceeding toward completion,
the same top-level validation is done by replacing
the behavioural model with a transistor-level
description (including RC parasitic if required).

Top-Down Physical Design
Early floorplanning (including pad placement)
even with rough estimation of block (area, aspect
ratio, pin location) will enable to plan for special
nets routing (buses, clocks, power network,
sensitive nets ...).
As the project is proceeding toward completion,
the same floorplanning could be refined and
adapted.

The use of the workflows may vary depending on
the design requirements and organization of design teams.
30/3/10
[email protected]
Bottom-up Block Function
& Physical Design
Analog and Digital block circuit level
implementation (transistors & gates)
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Advanced CAE tools platform.
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Full-Custom Analog design
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Standard-cell Digital design
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Cadence Virtuoso platform
“Front End design flow”
Cadence SOC Encounter platform
“Back End design flow”
Key Technology: Open Access database
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30/3/10
A common database to save & restore designs
from Virtuoso and SOC_Encounter platforms.
Significantly reduces data translations and
associated errors.
Open standard. (http://openeda.org)
[email protected]
29
“Analog on Top” Design Flow
For big ‘A’ small ‘D’ designs.
SOC_Encounter
Virtuoso
Digital block creation
Chip assembly
Begin
Finish
30/3/10
[email protected]
30
Virtuoso Floorplanning
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Generate Physical Hierarchy.
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Early in design phase: from soft-block
(abstract) to hard-block (layout)
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Helps avoid late-in-cycle block resizing,
reshaping, pin-shuffling.
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Cut down design cycle time with
continuous and iterative floorplanning.
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Accurate area estimation.
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Full connectivity view (instances,
connectivity, pins & prboundary)
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Partial layout view generation
(abstract like)
30/3/10
[email protected]
31
AMS Designer Simulator

Mixed-signal, mixed-language, mixed-level simulator.
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Verilog¨, Verilog-A, Verilog-AMS, VHDL, VHDL-AMS,
System-C, System-Verilog, SPICE, and Spectre languages
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Component-level schematics, netlists,
behavioral models, structural models
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A single-executable simulator incorporating the fastest in
digital simulation (NCSim) with a choice of analog solvers
(Spectre and UltraSim¨).
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UltraSim provide FastSPICE simulation capability.

Built on the INCA (Interleaved Native Compiled
Architecture) platform.
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High performance
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Fewer interfaces between tools
Small, efficient memory footprint
Unified Debugging environment
30/3/10
[email protected]
32
Constraint driven Analog design
30/3/10
[email protected]
33
“Digital on Top” Design Flow
For big ‘D’ small ‘A’ designs.
Virtuoso
SOC_Encounter
Analog Block Creation
Chip Design
RTL synthesis
O
p
e
n
30/3/10
A
c
c
e
s
s
Timing
optimization
Logical
Equivalence
Checking
Floorplanning
& power
routing
Automated
task
User task
Logical
Equivalence
Checking
Clock tree
synthesis
DFM
Timing
optimization
Signoff
RC extraction
Routing
Timing
analysis
DRC
Placement
LVS
Congestion
analysis
Timing
optimization
Tape-out
[email protected]
34
IC design CAE tools at CERN
30/3/10
[email protected]
35
Objectives

At present, Support for two advanced technology nodes:
CMOS 8RF-LM
CMOS 8RF-DM
Low cost
technology for
Large Digital
designs
Low cost
technology for
Analog & RF
designs
BiCMOS 8WL
Cost effective
technology for Low
Power RF designs
BiCMOS 8HP
CMOS 9SF LP/RF
High Performance
technology for
demanding
RF designs
High performance
technology for
dense designs
130nm CMOS

Development of:
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90nm CMOS
“CMOS8RF Mixed Signal Design Kit”
“Analog & Mixed Signal Methodologies (Workflows)”
Provide:
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30/3/10
Maintenance
Training
Support
[email protected]
36
CAE Tools & Technology support
Foundry
Physical IP
vendors
CERN
CAE tools &
technology support
CERN designers
30/3/10
CAE Tools
vendors
Cadence
VCAD
design services
External designers
[email protected]
37
CMOS8RF Mixed Signal design kit

Key Features:
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IBM PDK V1.6
IBM Standard cell and IO pad libraries

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IBM
IBM
PDK
Physical Layout views available.
Access to standard cell libraries is legally
covered by already established IBM CDAs
Standard
cell libraries
CAE
Tools
New versions of CAE Tools

Open Access database support.

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Interoperability of Virtuoso and SOC-Encounter platforms.
Compatible with the “Europractice” distributions.
Mixed Signal

Design
Kit
Support for LINUX Platform (qualified on RHEL4)

Two design kits available:


30/3/10
[email protected]
CMOS8RF-DM (3-2-3 BEOL)
CMOS8RF-LM (6-2 BEOL)
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CMOS8RF Mixed Signal Workflows
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PDK
Analog & Mixed Signal (AMS) Workflows.
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Formalize the design work by employing
standardized and validated Design Workflows.
Formalize the design work
across design teams in common projects.
Provide a repository with reference design examples.
Digital
Library
Design
Workflows

Development work subcontracted to Cadence, VCAD design services.

Close collaboration of CERN - VCAD - IBM



30/3/10
VCAD brought in their invaluable expertise on the CAE tools
IBM provided the physical IP blocks and important technical assistance
CERN assisted the development and validated the design kit functionality.
[email protected]
39
Analog & Mixed Signal Workflows
30/3/10
[email protected]
40
Digital Block
Implementation Flow
“I2C slave” serial interface IP block
employing Triple Module Redundancy
for enhanced SEU protection.
Prepared by
Sandro Bonacini
CERN PH/ESE
[email protected]
30/3/10
[email protected]
41
Digital Design Flow
Automated task
RTL synthesis
Logical
Equivalence
Checking
Floorplanning
& power
routing
User task
Timing
optimization
Clock tree
synthesis
DFM
Timing
optimization
Signoff
RC extraction
Logical
Equivalence
Checking
DRC
Placement
Routing
Congestion
analysis
LVS
Timing
analysis
Timing
optimization
Tape-out
30/3/10
[email protected]
42
Synthesis
[email protected]
Timing
constraints
[.sdc]
Max timing
Liberty libraries
[.lib]
RTL description
[.v] / [.vhd]
RTL synthesis
Synthesis,
mapping and
timing reports
Capacitance
tables [.CapTbl]
Abstract layout
Definition [.lef]
Mapped netlist
[.v]
Conformal script
[.lec]
RTL compiler
script [.tcl]
30/3/10
[email protected]
43
Logic Equivalent Checking (LEC)
[email protected]
RTL description
[.v] / [.vhd]
Mapped netlist
[.v]
Conformal script
[.lec]
Max timing
Liberty libraries
[.lib]
Logical
Equivalence
Checking

LEC
report
30/3/10
[email protected]
Tool:
Conformal
44
Floorplanning & Power Routing
[email protected]

Define
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Chip/core size
target area utilization
I/O placement
module placement in
case of TMR or other
special constraints
Power
planning/routing

30/3/10
Core/block rings and
stripes
[email protected]
45
Placement
[email protected]

Encounter
command file
Open Access
Floorplanned
Design [.oa]
Connect cells
power/ground
Add tap cells
Placement
Scan-chain
reorder
Reports
30/3/10
Open Access
Placed
Design [.oa]
[email protected]
46
Placement
[email protected]
Tap
cells
Standard
cells
Power/ground
connections
30/3/10
Sandro Bonacini
- PH/ESE - [email protected]
[email protected]
47
Congestion analysis
[email protected]

Use Encounter
Trialroute to
estimate
congested areas

Manually add
placement
partial blockage

Change position
of I/Os or blocks

…or increase
number of
routing metals
Open Access
Placed
Design [.oa]
Congestion
analysis
Placement
optimization
Open Access
Placed
Design [.oa]
30/3/10
[email protected]
48
Clock tree synthesis & signal routing
[email protected]
30/3/10
[email protected]
49
Design For Manufacturing
[email protected]
Open Access
Routed
Design [.oa]
Antenna fix
Via
optimization
Cells & metal
fill
Signoff
RC extraction
Final netlist
[.v]
Open Access
Final
Design [.oa]
Signal integrity
analysis
Delay file
[.sdf]
Timing
analysis
Signoff timing
report
30/3/10
[email protected]
50
Antenna fix
[email protected]


30/3/10
[email protected]
Re-routes long nets
Inserts tie-down diodes
51
Via optimization
[email protected]
30/3/10
[email protected]
52
Filler cells and metal fill
[email protected]
30/3/10
[email protected]
53
Back to Virtuoso !
[email protected]

OA design is present
in Virtuoso

30/3/10
[email protected]
Easily included in a
mixed-signal chip
54
Training: AMS Workshops

Workshop Targets:




Present the IBM CMOS8RF (130nm) Mixed Signal Kit.
Present Workflows for Analog, Digital and Mixed Signal designs.
Introduce the new Platform of Cadence CAE Tools.
This is NOT:


30/3/10
A course on analog or digital designing.
An advanced course targeted to a specific Cadence Tool.
[email protected]
55
Example Design

The workshop modules are based
on a realistic Mixed Signal ASIC:



Analog IP block: DAC
Digital IP block: SRAM
Digital block: I2C slave



synthesizable RTL code
Triple Module Redundancy
Digital Flow Scripts

Top level Behavioral Modeling

Design verification

Final chip Physical verification
30/3/10
[email protected]
56
AMS Workshop Contents

Day 1 (Lead by Maxime Barbe)
- Introduction to AMS kit Workshop
- Functional Verification : Digital Simulation Flow
- Functional Verification : AMS Simulation from command-line
- Functional Verification : AMS Simulation from DFII

Day 2 (Lead by Maxime Barbe)
- Analog IP Characterization : ADEXL
- Overview of IC6.13 (ADEXL and VSE)
- Analog Block Creation: Constraints

Day 3 (Lead by Vincent Cao Van Phu)
- Hierarchical Floorplaning (Virtuoso based)
- CDB IP Import to OA database for IC61 Methodology

Day 4 (Lead by Vincent Cao Van Phu)
- Digital Block Implementation
- Block IP Characterization Back End
- Digital IP Characterization Front-End

Digital
Day 5 (Lead by Vincent Cao Van Phu)
- Constraint Driven Analog Block Creation Back-End
- DRC (Calibre + Assura workflows)
- LVS (Callibre + Assura workflows)
- Extraction
- Round table discussion and workshop evaluation (30min).
30/3/10
Analog
&
Mixed Signal
[email protected]
Physical Verification
57
AMS Workshops

Workshop sessions








Statistics



1st session: 26/10 – 30/10, 2009 (CERN internal engineers, “pilot” run)
2nd session: 16/11 – 20/11, 2009 (CERN, open to external engineers)
3rd session: 30/11 – 4/12, 2009 (IPHC, Strasbourg, France)
4th session: 1/2 – 5/2, 2010 (CERN, with fees)
5th session: 15/2 – 19/2, 2010 (CERN, with fees)
6th session: 1/3 – 5/3, 2010 (CERN, with fees)
7th session: 12/4 – 16/4, 2010 (CERN, with fees)
CERN
IN2P3
INFN
NIKEF
Germany
US
other
10 engineers/session.
70 engineers in total.
Support


30/3/10
Technical: Bert Van Koningsveld
Secretarial: Evelyne Dho
[email protected]
58
Future Plans

Extend the functionalities of the CMOS8RF (130nm) kit.

Next PDK release scheduled for 3Q 2010



Development of a Design Kit for the CMOS9LP/RF (90nm)



Integrates PDK V1.7.0
Implements bug fixes as reported by users.
Standard cell libraries.
Design Workflows similar to those in the CMOS8RF Design Kit.
IP Block Packaging Solution
30/3/10
[email protected]
59
IP packaging solution (VCAD)
30/3/10
[email protected]
60
DECM tool in use at CERN

Design Environment Configuration Management




Centralized management:





PDKs &
Libraries
Workflow management tool
Design environment configuration
(environment variables, startup files, tool paths, etc)
CAE tools rely heavily on UNIX environment variables for their
configuration.
EDA
Tools
Workflows
Projects
DECM server
Admin editor
Project editor
Project users
Customized design environment for each project
Consistency of setup within the design team
Stability
Project versioning
Flexibility




Easy Graphical User Interface for the users and administrators.
Different GUIs for different user roles
Multiple sessions with different design environment configurations
Built in project access control mechanism

VCAD Productivity IP solution.

Administrator: Bert Van Koningsveld
30/3/10
[email protected]
61
LINUX CAE platform for IC design
File Backup server
Tivoli server
Administrators: Bert Van Koningsveld
Wojciech Bialas
CAE Server #1
lnxmics1
DAS server
DELL
1 TB RAID 1 Disc Storage
DELL
7 TB RAID 6 Disc Storage
lnxmic10
lnxmic11
lnxmic12
Cogestra
P. Aspell
SUN
P. Moreira
S. Bonacini
SUN
W. Snoeys
Cogestra
M. Marra
SUN
G. Venturini
lnxmic19
lnxmic20
lnxmic21
lnxmic22
lnxmicjb
SUN
X. Llopart
SUN
T.S. Poikela
lnxmic4
lnxmic5
lnxmic6
lnxmic7
lnxmic8
SUN
C. Paillard
SUN
K. Kloukinas
SUN
S. Marchioro
SUN
A. Rivetti
Cogestra
L. Pierobon
Cogestra
W. Bialas
lnxmic13
lnxmic14
lnxmic15
lnxmic16 lnxmic17
lnxmic18
SUN
S. Michelis
SUN
SUN
F. Anghinolfi W. Snoeys
30/3/10
SUN
F. Faccio
SUN
S. Orlandi
Users Workstations
(LINUX PCs)
lnxmic9
lnxmic3
SUN
K. Poltorak
CERN IT
CERN ESE
RAID Server
lnxmic2
SUN
J. Kaplon
STATUS: Feb. 15, 2010
[email protected]
HP
Cogestra
R. De Oliveira L. Perktold
62
The CERN ASIC support website
http://cern.ch/asic-support
Download Design Kits and
access technical documents
(restricted access)
Information about MPW runs
and foundry access services.
Communicate news and
User support feedback forms
and access request forms.
This website replaces our ‘afs’ based download facility.
30/3/10
[email protected]
63
Wrap Up

A message to Industry
Third party
IP vendors
Foundry
90 nm
130 nm
45 nm
65 nm
Methodologies
CAE Vendors
A message to industry:
“ The present situation of IC design, which has high levels of flexibility
in implementation is not sustainable by small and medium scale design groups
and a highly structured design flow and methodologies will need to be established”
30/3/10
[email protected]
64
Acknowledgements
• IDESA training EU 7th Framework Program (http://www.idesa-training.org/) for material presented in slides.
• Cadence & VCAD services group in Paris for material presented in slides.
• IBM for technology data presented in slides.
• Sandro [email protected], for his work on the customized digital design flow.
• [email protected], [email protected], for their efforts in the CAE tools support services.
30/3/10
[email protected]
65
Sign-Off Formal Equivalence



Verify that the final netlist is functionally
equivalent to the original RTL code.
Using formal methods to compare logic.
Two representations:



Reference (Golden) RTL code, the “correct” reference design
Implementation (unknown) the design being verified.
Give a pass/fail result with information to
help diagnosis.
30/3/10
[email protected]
66