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THE INVERTER
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
EE415 VLSI Design
DIGITAL GATES
Fundamental Parameters
The key parameters that govern a digital
gate’s performance and usability.



Area and Complexity
Functionality and Robustness (Reliability)
Performance
» Speed (delay)
» Power Consumption (dissipation)
» Energy
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Area and Complexity
•Small area very desirable for digital gate
•higher integration density
•smaller die size
•lower fabrication cost
•faster (smaller Cg)
•Implementation area
•depends on number of transistors
•interconnection area
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Functionality and Robustness
•Prime requirement for digital gate:
•perform designed function
•Measured behavior deviates from expected response. Why?
•variations in process
•noise (unwanted variations of voltages and currents at the
logic nodes)
•Logic levels
•VOH and VOL represent high and low logic levels
•difference is called the logic swing
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Noise in Digital Integrated Circuits
v(t)
VDD
i(t)
(a) Inductive coupling
(b) Capacitive coupling
(c) Power and ground
noise
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The Voltage-Transfer Characteristic
•Electrical function of gate is best expressed by its
voltage-transfer characteristic (VTC)
(DC transfer characteristic)
•Plots Vout =f(Vin)
•Gate (Switching) logic threshold voltage, VM:
•VM=f(VM)
•intersection of VTC at Vout=Vin
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DC Operation:
Voltage Transfer Characteristic (VTC)
V(y)
V(x)
V
OH
f
V(y)=V(x)
V
Switching Threshold
M
VOL
VOL
V
OH
V(x)
Nominal Voltage Levels
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V(y)
Mapping between analog and digital signals
Problem:
•Output signal deviates from expected nominal value due
to:
•noise
•loading of the gate output
Solution:
•Logic levels represented by range of acceptable values
•Regions of acceptable values delimited by VIH and VIL
•represents points in VTC where (dVout/dVin) = -1
•undefined region known as transition width
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Mapping between analog and digital signals
"1"
V
OH
V
IH
V(y)
V
OH
Slope = -1
Undefined
Region
V
IL
"0"
V
OL
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Slope = -1
VOL
V
V
IL IH
V(x)
Noise Margins
•Measure of a gate sensitivity to noise
•Quantize the size of legal “0” and “1”
•Represents level of noise that can be tolerated when gates
are cascaded
•NML (noise margin low)
NML = VIL - VOL
•NMH (noise margin high)
NMH = VOH - VIH
•Should be large as possible for good noise immunity
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Definition of Noise Margins
"1"
V
OH
NMH
V
IH
Undefined
Region
Noise Margin High
Noise Margin Low
NML
V
V
IL
OL
"0"
Gate Output
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Gate Input
The Regenerative Property
•Large noise margin alone not sufficient for proper
operation
•Gate must “boost” weak levels back to nominal
values
•Known as regeneration (of levels)
•Non-regenerative gate output will converge to
intermediate value
•Conditions for regeneration:
•VTC transient region gain >1 (absolute value)
•Gain in the two legal zones must be < 1
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The Regenerative Property
...
v1
v0
v2
v3
v5
v4
v6
(a) A chain of inverters.
v1, v3, ...
v1, v3, ...
finv(v)
f(v)
finv(v)
v0, v2, ...
(b) Regenerative gate
EE415 VLSI Design
f(v)
v0, v2, ...
(c) Non-regenerative gate
Directivity
•A gate must be unidirectional:
•input not affected by output changes
•causes noise in input otherwise
•Real gate:
•full directivity never achievable
•capacitive coupling causes feedback
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Fan-in and Fan-out
•Fan-out:
•Number of load gates, N, that are connected to the output of
the driving gate
•tends to lower the logic levels
•deteriorates dynamic performance
•gate must have low output resistance to drive load
•library cells have maximum fan-out specification
•Fan-in:
•Number of inputs, M, to the gate
•large fan-in gates are more complex
•results in inferior static and dynamic performance
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Fan-in and Fan-out
(a) Fan-out N
M
N
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(b) Fan-in M
The Ideal Gate
Vout
Ri = 
Ro = 0
g=-
Vin
Static CMOS comes close to ideal
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VTC of Real Inverter
5.0
Vout (V)
4.0
NML
3.0
2.0
VM
NMH
1.0
0.0
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1.0
2.0
3.0
Vin (V)
4.0
5.0
Dynamic Behavior
Propagation Delay, Tp
•Defines how quickly output is affected by input
•Measured between 50% transition from input to output
•tpLH defines delay for output going from low to high
•tpHL defines delay for output going from high to low
•Overall delay, tp, defined as the average of tpLH and tpHL
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Dynamic Behavior
Rise and fall time, Tr and Tf
•Defines slope of the signal
•Defined between the 10% and 90% of the signal
swing
Propagation delay and rise and fall times affected by
the fan-out due to larger capacitance loads
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Delay Definitions
Vin
50%
t
t
Vout
t
pLH
pHL
90%
50%
10%
tf
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t
tr
The Ring Oscillator
•A standard method is needed to measure the gate
delay
•It is based on the ring oscillator
•2Ntp >> tf + tr for proper operation
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Ring Oscillator
v1
v0
v0
v2
v1
v3
v4
v5
T = 2  tp N
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v5
Power Dissipation
•Power consumption determines heat dissipation and energy
consumption
•Influence design decisions:
•packaging and cooling
•width of supply lines
•power-supply capacity
•# of transistors integrated on a single chip
Power requirements make high density bipolar ICs
impossible (feasibility, cost, reliability)
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Power Dissipation
Supply-line
sizing
Battery drain,
cooling
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Power Dissipation
•Ppeak = static power + dynamic power
•Dynamic power:
•(dis)charging capacitors
•temporary paths from VDD to VSS
•proportional to switching frequency
•Static power:
•static conductive paths between rails
•leakage
•increases with temperature
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Power Dissipation
•Propagation delay is related to power consumption
•tp determined by speed of charge transfer
•fast charge transfer => fast gate
•fast gate => more power consumption
•Power-delay product (PDP)
•quality measure for switching device
•PDP = energy consumed /gate / switching event
•measured using ring oscillator
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Power Dissipation
Supply-line
sizing
Battery drain,
cooling
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Energy consumed /gate /switching
event
CMOS Inverter: Steady State Response
•CMOS technology:
•No path exists between VDD and VSS in steady state
•No static power consumption! (ideally)
•Main reason why CMOS replaced NMOS in early 80’s
•NMOS technology:
•Has NMOS pull-up device that is always ON
•Creates voltage divider when pull-down is ON
•Power consumption puts upper bound on (# devices /
chip)
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Static CMOS: Properties
•VOH = VDD , VOL = VSS (GND)
•voltage swing equal to supply voltage
•provides high noise margins
•Logic levels not dependent on relative device sizes
•transistors can be minimum size
•known as ratioless logic (as opposed to ratioed
logic based on NMOS devices)
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Static CMOS: Properties
•Finite resistance always exists between output and
supply rails (in steady state)
•low output impedance (typically 10K ohms)
•less sensitive to noise
•Extremely high input resistance
•MOSFET gate perfect insulator and draws no DC
current
•steady-state input current zero (ignoring leakage)
•can have large fan-out and still be functional
•fan-out has no effect on steady-state behavior
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Voltage
Transfer
Characteristic
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CMOS Inverter Load Characteristics
VDD
G
S
D
Vin
Vout
CL
D
G
S
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PMOS Load Lines
VDD
IDn
G
V in = V DD +VGSp
IDn = - IDp
V out = VDD +VDSp
S
D
Vin
Vout
D
V out
CL
G
IDp
S
IDn
IDn
Vin=0
Vin=0
Vin=3
Vin=3
V DSp
V DSp
VGSp=-2
VGSp=-5
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Vin = V DD+VGSp
IDn = - IDp
Vout = V DD+VDSp
Vout
CMOS Inverter Load Lines
PMOS
2.5
NMOS
X 10-4
Vin = 0V
2
Vin = 2.5V
Vin = 0.5V
1.5
Vin = 2.0V
1
Vin = 1.0V
Vin = 1V Vin = 1.5V
Vin = 0.5V
Vin = 2V
0.5
Vin = 1.5V
Vin = 2.0V
0
0
V = 2.5V
in
Vin = 1.5V
Vin = 1.0V
Vin = 0.5V
0.5
1
1.5
2
2.5
Vin = 0V
Vout (V)
0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V
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Cutoff
Linear
Saturation
pMOS
Vin -VDD= VGS> VT
Vin -VDD=VGS< VT
Vin -Vout=VGD< VT
Vin -VDD=VGS> VT
Vin -Vout=VGD>VT
nMOS
Vin = VGS< VT
Vin =VGS> VT
Vin -Vout =VGD> VT
Vin =VGS> VT
Vin -Vout =VGD< VT
Regions of operations
For nMOS and pMOS
In CMOS inverter
VDD
G
S
D
Vin
Vout
D
G
S
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CL
CMOS Inverter Load Characteristics
•For valid dc operating points:
•current through NMOS = current through PMOS
•=> dc operating points are the intersection of load lines
•All operating points located at high or low output levels
•=> VTC has narrow transition zone
•high gain of transistors during switching
•transistors in saturation
•high transconductance (gm)
•high output resistance (voltage controlled current source)
EE415 VLSI Design
CMOS Inverter VTC
NMOS off
PMOS res
2.5
2
1.5
1
0.5
0
NMOS sat
PMOS res
Vout (V)
NMOS sat
PMOS sat
NMOS res
PMOS sat
0
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0.5
1
Vin
1.5
(V)
2
NMOS res
PMOS off
2.5
Voltage Transfer
Characteristic
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Switching Threshold



VM where Vin = Vout (both PMOS and NMOS in
saturation since VDS = VGS)
VM  rVDD/(1 + r) where r = kpVDSATp/knVDSATn
Switching threshold set by the ratio r, which
compares the relative driving strengths of the PMOS
and NMOS transistors
Want VM = VDD/2 (to have comparable high and low
noise margins), so want r  1
(W/L)p = kn’VDSATn(VM-VTn-VDSATn/2)
(W/L)n kp’VDSATp(VDD-VM+VTp+VDSATp/2)
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Switch Threshold Example

In our generic 0.25 micron CMOS process, using the
process parameters from table a VDD = 2.5V, and a
minimum size NMOS device ((W/L)n of 1.5)
VT0(V)
(V0.5)
VDSAT(V)
k’(A/V2)
(V-1)
NMOS
0.43
0.4
0.63
115 x 10-6
0.06
PMOS
-0.4
-0.4
-1
-30 x 10-6
-0.1
(W/L)p 115 x 10-6 0.63 (1.25 – 0.43 – 0.63/2)
=
(W/L)n
x
-30 x
10-6
x
-1.0
(1.25 – 0.4 – 1.0/2)
(W/L)p = 3.5 x 1.5 = 5.25 for a VM of 1.25V
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= 3.5
Simulated Inverter VM
1.5
1.4
VM is relatively insensitive to
variations in device ratio
 setting the ratio to 3, 2.5
and 2 gives VM’s of 1.22V,
1.18V, and 1.13V

1.3
1.2
1.1
1
Increasing the width of the
PMOS moves VM towards VDD

0.9
0.8
0 .1
1
(W/L)p/(W/L)n
Note: x-axis is semilog
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~3.4
10
Increasing the width of the
NMOS moves VM toward GND

Noise Margins Determining
VIH and VIL
3
By definition, VIH and VIL are
where dVout/dVin = -1 (= gain)
VOH = VDD
2
VM
1
VOL = GND0
VIL
Vin VIH
A piece-wise linear
approximation of VTC
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NMH = VDD - VIH
NML = VIL - GND
Approximating:
VIH = VM - VM /g
VIL = VM + (VDD - VM )/g
So high gain in the transition
region is very desirable
Vout (V)
CMOS Inverter VTC from
Simulation
0.25um, (W/L)p/(W/L)n = 3.4
(W/L)n = 1.5 (min size)
VDD = 2.5V
2.5
2
1.5
1
0.5
0
VM  1.25V, g = -27.5
VIL = 1.2V, VIH = 1.3V
NML = NMH = 1.2
(actual values are
VIL = 1.03V, VIH = 1.45V
NML = 1.03V & NMH = 1.05V)
0
0.5
1
Vin (V)
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1.5
2
2.5
Output resistance
low-output = 2.4k
high-output = 3.3k
Gain Determinates
Vin
0
0.5
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
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1
1.5
2
Gain is a strong function of the slopes
of the currents in the saturation region,
for Vin = VM
(1+r)
g  ---------------------------------(VM-VTn-VDSATn/2)(n - p )
Determined by technology parameters,
especially channel length modulation
(). Only designer influence through
supply voltage and VM (transistor
sizing).
Vout (V)
Impact of Process Variation
2.5
2
1.5
1
0.5
0
Good PMOS
Bad NMOS
Nominal
Bad PMOS
Good NMOS
0
0.5
1
1.5
2
2.5
Vin (V)
Pprocess variations (mostly) cause a shift in the switching
threshold
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Scaling the Supply Voltage
2.5
0.2
2
Vout (V)
Vout (V)
0.15
1.5
1
0.1
0.05
0.5
Gain=-1
0
0
0
0.5
1
1.5
Vin (V)
Device threshold voltages are
kept (virtually) constant
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2
2.5
0
0.05
0.1
0.15
Vin (V)
Device threshold voltages are
kept (virtually) constant
0.2
Propagation
Delay
EE415 VLSI Design
Switch Model of Dynamic Behavior
VDD
VDD
Rp
Vout
Vout
CL
CL
Rn
V =V
in
DD
Vin = 0 time is determined by the time
 Gate response
to charge
CL
through Rp (discharge CL through Rn)
EE415 VLSI Design
What is the Inverter Driving?
VDD
VDD
M2
Vin
Cg4
Cdb2
Cgd12
M4
Vout
Cdb1
Cw
M1
Vout2
Cg3
M3
Interconnect
Fanout
Simplified
Model
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Vin
Vout
CL
CMOS Inverter Propagation Delay
Approach 1
VDD
tpHL = CL Vswing/2
Iav
CL
Vout
~
Iav
Vin = V DD
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CL
kn VDD
CMOS Inverter Propagation Delay
Approach 2
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
Vout  VOH e -t /( RonCL )
0.5
0.36
Vin = V DD
RonCL
EE415 VLSI Design
t
CMOS Inverter: Transient Response
How can the designer build a fast gate?
•tpHL = f(Ron*CL)
•Keep output capacitance, CL, small
•low fan-out
•keep interconnections short (floor-plan your layout!)
•Decrease on-resistance of transistor
•increase W/L ratio
•make good contacts (slight effect)
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CMOS Properties





Full rail-to-rail swing
Symmetrical VTC
Propagation delay function of load
capacitance and resistance of transistors
No static power dissipation
Direct path current during switching
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MOS Transistor Small Signal Model
G
D
+
vgs
gmvgs
-
Define
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S
ro
Determining VIH and VIL
VIH and VIL are based on derivative of VTC equal to -1
EE415 VLSI Design
Transient Response
?
3
2.5
tp = 0.69 CL (Reqn+Reqp)/2
Vout(V)
2
tpHL
tpLH
1.5
1
0.5
0
-0.5
0
0.5
1
1.5
t (sec)
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2
2.5
-10
x 10
Inverter Transient Response
3
VDD=2.5V
0.25m
W/Ln = 1.5
W/Lp = 4.5
Reqn= 13 k ( 1.5)
Reqp= 31 k ( 4.5)
Vin
2.5
2
1.5
tpHL
1
tf
tpLH
tr
0.5
tpHL = 36 psec
0
tpLH = 29 psec
so
-0.5
0
0.5
1
1.5
t (sec)
2
2.5
x 10-10
From simulation: tpHL = 39.9 psec and
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tp = 32.5 psec
tpLH = 31.7 psec
Design for Performance
Keep capacitances small
 Increase transistor sizes

» watch out for self-loading!

Increase VDD (????)
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Delay as a function of VDD
5.5
5
tp(normalized)
4.5
4
3.5
3
2.5
2
1.5
1
0.8
1
1.2
1.4
1.6
V
1.8
(V)
DD
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2
2.2
2.4
Sizing Impacts on Delay
x 10-11
3.8
for a fixed load
3.6
The majority of the
improvement is already
obtained for S = 5. Sizing
factors larger than 10 barely
yield any extra gain (and cost
significantly more area).
3.4
3.2
3
2.8
2.6
2.4
2.2
2
1
3
5
7
9
S
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11
13
15
self-loading effect
(intrinsic capacitance
dominates)
PMOS/NMOS Ratio Effects
5
x 10-11
tpLH
4.5
 of 2.4 (= 31 k/13 k)
gives symmetrical
response
tpHL
4
 of 1.6 to 1.9 gives
optimal performance
tp
3.5
3
1
2
3
 = (W/Lp)/(W/Ln)
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4
5
Impact of Rise Time on Delay
0.35
tpHL(nsec)
0.3
Rise time is a function
of fan-in
0.25
0.2
0.15
0
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0.2
0.4
0.6
trise (nsec)
0.8
1
Inverter
Sizing
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CMOS Inverter: Four Views
Vdd
Vin
Vout Vin
Vout
Gnd
Logic Transistor Layout
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Physical
CMOS Inverter Layout
Out
metal1
metal2
pdiff
In
metal1-poly via
polysilicon
VDD
PMOS (4/.24 = 16/1)
NMOS (2/.24 = 8/1)
metal1-diff via
ndiff
GND
metal2-metal1 via
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Inverter Delay
• Minimum length devices, L=0.25m
• Assume that for WP = 2WN =2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network
 WP 

RP  Runit 
 Wunit 
-1
 WN 

 Runit 
 Wunit 
Delay (D): tpHL = (ln 2) RNCL
Load for the next stage:
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-1
 RN  RW
tpLH = (ln 2) RPCL
W
C gin  3
Cunit
Wunit
2W
W
Inverter with Load
Delay
RW
CL
RW
Load (CL)
tp = k RWCL
k is a constant, equal to 0.69
Assumptions: no load -> zero delay
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Wunit = 1
Inverter with Load
CP = 2Cunit
Delay
2W
W
CN = Cunit
Cint
CL
Load
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)
= Delay (Internal) + Delay (Load)
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Delay Formula
Delay ~ RW Cint  C L 
t p  kRW Cint 1  C L / Cint   t p 0 1  f /  
Cint = Cgin with   1
f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
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Impact of Fanout on Delay


Extrinsic capacitance, Cext, is a function of the fanout
of the gate - the larger the fanout, the larger the
external load.
First determine the input loading effect of the inverter.
Both Cg and Cint are proportional to the gate sizing, so
Cint = Cg is independent of gate sizing and
tp = tp0 (1 + Cext/ Cg) = tp0 (1 + f/)
i.e., the delay of an inverter is a function of the ratio
between its external load capacitance and its input gate
capacitance: the effective fan-out f
f = Cext/Cg
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Inverter Chain

Real goal is to minimize the delay through an inverter chain
In
Out
Cg,1
1
2
N
CL
the delay of the j-th inverter stage is
tp,j = tp0 (1 + Cg,j+1/(Cg,j)) = tp0(1 + fj/ )
and
tp = tp1 + tp2 + . . . + tpN
so

tp = tp,j = tp0  (1 + Cg,j+1/(Cg,j))
If CL is given
» How should the inverters be sized?
» How many stages are needed to minimize the delay?
EE415 VLSI Design
Apply to Inverter Chain
In
Out
1
2
N
CL
tp = tp1 + tp2 + …+ tpN
 C gin, j 1 

t pj ~ RunitCunit 1 
 C

gin
,
j


N
N 
C gin, j 1 
, C gin, N 1  C L
t p   t p , j  t p 0  1 
 C

j 1
i 1 
gin, j 
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Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors
C gin, j  C gin, j -1C gin, j 1
- each stage has the same effective fanout (Cout/Cin)
- each stage has the same delay
EE415 VLSI Design
Optimum Delay and Number
of Stages
When each stage is sized by f and has same eff. fanout f:
f N  F  CL / Cgin,1
Effective fanout of each stage:
f NF
Minimum path delay

t p  Nt p 0 1  N F / 
EE415 VLSI Design

Example
In
C1
Out
1
f
f2
CL= 8 C1
CL/C1 has to be evenly distributed across N = 3 stages:
f 38 2
EE415 VLSI Design
Determining N: Optimal
Number of Inverters




What is the optimal value for N given F (=fN) ?
» if the number of stages is too large, the intrinsic delay of the
stages becomes dominate
» if the number of stages is too small, the effective fan-out of each
stage becomes dominate
The optimum N is found by differentiating the minimum delay
expression divided by the number of stages and setting the result to
0, giving
 +NF - ( NF lnF)/N = 0
For  = 0 (ignoring self-loading) N = ln (F) and the effective-fan out
becomes f = e = 2.71828
For  = 1 (the typical case) the optimum effective fan-out (tapering
factor) turns out to be close to 3.6
EE415 VLSI Design
Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
N
CL  F  Cin  f Cin with N 
ln f
t p 0 ln F  f


t p  Nt p 0 F /   1 

  ln f ln f
t p t p 0 ln F ln f - 1 -  f


0
2
f

ln f
1/ N
For  = 0, f = e, N = lnF
EE415 VLSI Design



f  exp 1   f 
Optimum Effective Fan-Out
5
7
6
4.5
5
4
4
3.5
3
2
3
1
2.5
0
0

0.5
1
1.5

2
2.5
3
1
1.5
2
2.5
3
3.5
4
4.5
f
Choosing f larger than optimum has little effect on delay and
reduces the number of stages (and area).
» Common practice to use f = 4 (for  = 1)
» But too many stages has a substantial negative impact on delay
EE415 VLSI Design
5
Example of Inverter (Buffer)
Staging
1
Cg,1 = 1
Cg,1 = 1
CL = 64 Cg,1
4
1
tp
1
64
65
2
8
18
3
4
15
4
2.8
15.3
16
Cg,1 = 1
1
f
CL = 64 Cg,1
8
1
N
2.8
Cg,1 = 1
EE415 VLSI Design
CL = 64 Cg,1
8
22.6
CL = 64 Cg,1
Impact of Buffer Staging for
Large CL

F ( = 1)
Unbuffered
Two Stage
Chain
Opt. Inverter
Chain
10
11
8.3
8.3
100
101
22
16.5
1,000
1001
65
24.8
10,000
10,001
202
33.1
Impressive speed-ups with optimized
cascaded inverter chain for very large
capacitive loads.
EE415 VLSI Design
Input Signal Rise/Fall Time
x 10-11
5.4

In reality, the input signal changes
gradually (and both PMOS and
NMOS conduct for a brief time).
This affects the current available for
charging/discharging CL and
impacts propagation delay.
5.2
5
4.8
4.6
4.4
4.2
4


tp increases linearly with increasing
input slope, ts, once ts > tp
ts is due to the limited driving
capability of the preceding gate
EE415 VLSI Design
3.8
3.6
0
2
4
6
ts(sec)
8
for a minimum-size inverter
with a fan-out of a single gate
x 10-11
Design Challenge

A gate is never designed in isolation: its performance is
affected by both the fan-out and the driving strength of
the gate(s) feeding its inputs.
tip = tistep +  ti-1step
(  0.25)

Keep signal rise times smaller than or equal to the gate propagation
delays.
» good for performance
» good for power consumption

Keeping rise and fall times of the signals small and of approximately
equal values is one of the major challenges in high-performance
designs - slope engineering.
EE415 VLSI Design
Delay with Long
Interconnects

When gates are farther apart, wire capacitance and
resistance can no longer be ignored.
(rw, cw, L)
Vin
cint
Vout
cfan
tp = 0.69RdrCint + (0.69Rdr+0.38Rw)Cw + 0.69(Rdr+Rw)Cfan
where Rdr = (Reqn + Reqp)/2
= 0.69Rdr(Cint+Cfan) + 0.69(Rdrcw+rwCfan)L + 0.38rwcwL2

Wire delay rapidly becomes the dominate factor (due to the quadratic
term) in the delay budget for longer wires.
EE415 VLSI Design
Power
Dissipation
EE415 VLSI Design
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
EE415 VLSI Design
Dynamic Power Dissipation
Vdd
Vin
Vout
CL
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Not a function of transistor sizes!
Need to reduce CL, Vdd, and f to reduce power.
EE415 VLSI Design
Modification for Circuits with Reduced Swing
Vdd
Vdd
Vdd -Vt
CL
E0
1
= CL  Vdd   Vdd – Vt 
Can exploit reduced sw ing to low er power
(e.g., reduced bit-line swing in memory)
EE415 VLSI Design
Adiabatic Charging
2
2
EE415 VLSI Design
2
Adiabatic Charging
EE415 VLSI Design
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E N = CL  V dd2  n N 
EN : the energy consumed for N clock cycles
n(N ): the number of 0->1 transition in N clock cycles
EN
2
n N 
P avg = lim --------  fclk =  lim ----------- C  Vdd  f clk
N   N 
N N
L
0  1 =
n N 
lim -----------N N
P avg = 0 1  C  Vdd 2  f clk

L
EE415 VLSI Design
Transistor Sizing for Minimum
Energy
In
Out
Cg1

1
f
Cext
Goal: Minimize Energy of whole circuit
» Design parameters: f and VDD
» tp  tpref of circuit with f=1 and VDD =Vref
EE415 VLSI Design

f 
F 
t p  t p 0  1    1   
f  
   
VDD
t p0 
VDD - VTE
Transistor Sizing (2)

Performance Constraint (=1)
tp
t pref


t p0
t p 0 ref

F
 2  f  
f  VDD Vref - VTE


3  F 
Vref VDD - VTE

F
 2  f  
f 

1
3  F 
Energy for single Transition
2
E  VDD
C g1 1   1  f   F 
2
 VDD   2  2 f  F 
E
 




Eref  Vref   4  F 
EE415 VLSI Design
Transistor Sizing (3)
VDD=f(f)
E/Eref=f(f)
4
1.5
3.5
F=1
normalized energy
3
2
vdd (V)
2.5
5
2
1.5
1
10
0.5
20
0
1
2
3
4
f
EE415 VLSI Design
5
6
7
1
0.5
0
1
2
3
4
f
5
6
7
Short Circuit Currents
Vd d
Vin
Vout
CL
IVDD (mA)
0.15
0.10
0.05
0.0
EE415 VLSI Design
1.0
2.0
3.0
Vin (V)
4.0
5.0
How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if tfall >> trise,
but can’t do this for cascade logic, so ...
EE415 VLSI Design
Minimizing Short-Circuit Power
8
7
Vdd =3.3
6
Pnorm
5
Vdd =2.5
4
3
2
Vdd =1.5
1
0
0
1
2
3
t /t
sin sout
EE415 VLSI Design
4
5
Leakage
Vd d
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Sub-threshold current one of most compelling issues
Sub-Threshold
in low-energy
circuitCurrent
design!Dominant Factor
EE415 VLSI Design
Reverse-Biased Diode Leakage
GATE
p+
p+
N
Reverse Leakage Current
+
V
- dd
IDL = JS  A
2
JS = JS
1-5pA/
for a 1.2
technology
= 10-100
at 25
degCMOS
C for 0.25m
CMOS
mpA/m2
m
JS doubles for every 9 deg C!
Js double with every 9oC increase in temperature
EE415 VLSI Design
Subthreshold Leakage Component
EE415 VLSI Design
Static Power Consumption
Vd d
Istat
Vout
Vin =5V
CL
Pstat = P(In=1) .Vdd . Istat
Wasted energy …
Should •beDominates
avoided in
almost
all consumption
cases,
over
dynamic
but could help reducing energy in others (e.g. sense amps)
• Not a function of switching frequency
EE415 VLSI Design
Principles for Power Reduction

Prime choice: Reduce voltage!
» Recent years have seen an acceleration in supply
voltage reduction
» Design at very low voltages still open question
(0.6 … 0.9 V by 2010!)


Reduce switching activity
Reduce physical capacitance
» Device Sizing: for F=20
– fopt(energy)=3.53, fopt(performance)=4.47
EE415 VLSI Design
Impact of
Technology
Scaling
EE415 VLSI Design
Goals of Technology Scaling

Make things cheaper:
» Want to sell more functions (transistors)
per chip for the same money
» Build same products cheaper, sell the
same part for less money
» Price of a transistor has to be reduced

But also want to be faster, smaller,
lower power
EE415 VLSI Design
Technology Scaling

Goals of scaling the dimensions by 30%:
» Reduce gate delay by 30% (increase operating
frequency by 43%)
» Double transistor density
» Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency


Die size used to increase by 14% per
generation
Technology generation spans 2-3 years
EE415 VLSI Design
Technology Generations
EE415 VLSI Design
Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors
Year of
Introduction
1999
Technology node
[nm]
180
Supply [V]
2000
2001
2004
2008
2011
2014
130
90
60
40
30
0.6-0.9
0.5-0.6
0.3-0.6
8
9
9-10
10
3.5-2
7.1-2.5
11-3
14.9
-3.6
1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2
Wiring levels
6-7
6-7
7
Max frequency
[GHz],Local-Global
1.2
Max P power [W]
90
106
130
160
171
177
186
Bat. power [W]
1.4
1.7
2.0
2.4
2.1
2.3
2.5
1.6-1.4 2.1-1.6
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
EE415 VLSI Design
Technology Evolution (1999)
EE415 VLSI Design
ITRS Technology Roadmap
Acceleration Continues
EE415 VLSI Design
Technology Scaling (1)
Minimum Feature Size (micron)
10
10
10
10
2
1
0
-1
-2
10
1960
1970
1980
1990
2000
Year
EE415 VLSI Design
Minimum Feature Size
2010
Technology Scaling (2)
Number of components per chip
EE415 VLSI Design
Technology Scaling (3)
tp decreases by 13%/year
50% every 5 years!
Propagation Delay
EE415 VLSI Design
Technology Scaling Models
• Full Scaling (Constant Electrical Field)
ideal model — dimensions and voltage scale
together by the same factor S
• Fixed Voltage Scaling
most common model until recently —
only dimensions scale, voltages remain constant
• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors
EE415 VLSI Design
Scaling Relationships for Long Channel
Devices
EE415 VLSI Design
Transistor Scaling
(velocity-saturated devices)
EE415 VLSI Design
Dilbert
EE415 VLSI Design
Dilbert
EE415 VLSI Design
Dilbert
EE415 VLSI Design
Dilbert
EE415 VLSI Design
Dilbert
EE415 VLSI Design