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Challenges and advantages making
analog front-ends (for Silicon Strip
Detectors) in deep submicron
technologies
Jan Kaplon
Challenges and advantages making analog front-ends in deep submicron technologies
1
Outline
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General requirements for silicon strip detectors electronics
Technology scaling and its consequences
Improving the open loop gain of amplifier stages
 Motivations
 Methods
Biasing in weak inversion as a solution for input stage
 Motivations
 Costs
Comparison between front end amplifiers designed for short strip
(5 to 10pF detector capacitance) in 250 and 130(90)nm process
 Architecture
 Performance
Challenges and advantages making analog front-ends in deep submicron technologies
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General requirements for the Front-End
tracker electronics for SLHC detectors
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Detector capacitance in the order of pF
Low power (<1mW/channel), low noise (S/N>15  ENC < 1500e-)
(optimization of power for a minimum affordable noise level)
Collisions of particles every 25 ns  data time tagging to the given BCO
(peaking times <25ns)
Low input impedance  efficient charge collection and low cross talk
signals
Stability  required phase margin above 85 to 90 degree
Optimum PSRR (large systems, difficult to provide clean power supply)
Radiation hardness – doses >2×1014 N/cm2 (1MeV) and >10MRad
(CMOS front end preferred)
Challenges and advantages making analog front-ends in deep submicron technologies
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CMOS technology scaling
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Technology scaling ; formerly proportional reduction of all transistor
features size (tox, L, W) scaled together with voltage supply and vt
threshold voltage (constant field scaling). Smaller feature size 
higher integration scale, lower power consumption/higher speed etc.
Constant field scaling required proportional scaling of threshold
voltage  this is limited by subthreshold slope of the MOS transistor
(limit for minimum Vt >200mV)
Scaling today ; constant voltage scaling introducing short channel
effects
 mobility reduction(vertical and longitudinal field)
 degradation of output conductance (channel length modulation,
Drain Induced Barrier Lowering (decreasing of Vt for higher Vds))
Challenges and advantages making analog front-ends in deep submicron technologies
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Comparison of basic analogue parameters for
three generations of IBM CMOS processes
IBM CMOS
250nm RF
130nm RF
90nm LP (low
power)
tOX physical/effective
5nm/6.2nm
2.2nm/3.12nm
2.1nm/2.8nm
Ka (COX∙µ) NMOS
330 uA/V2
720 uA/V2
800 uA/V2
Vdd
2.5V
1.2V (1.5V)
1.2V
gm/gds Weak Inv.
70
30
18
Peak ft
35 GHz
94 GHz
105 GHz
Scaling advantages; higher ft, higher Ka
Challenges for front end; lower Vdd (lower dynamic range), lower intrinsic transistor gain
Challenges and advantages making analog front-ends in deep submicron technologies
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Motivations to increase open loop gain
 Lowering input impedance of
preamplifier
 Better charge collection efficiency
 Lower cross talk

PSRR (all single ended stages)
Challenges and advantages making analog front-ends in deep submicron technologies
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Charge collection from silicon strip detectors,
cross talk signals
Z IN ( s) 
Z F ( s)
KV ( s )
Cross Talk ( s ) 
Z IN ( s )
Z IN ( s )  Z IS ( s )
Optimal open loop gain preamplifier designed for 5 to 20pF detector capacitance is
around 70 to 80dB (in order to provide cross talk less than 5%)
Challenges and advantages making analog front-ends in deep submicron technologies
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Motivations to increase open loop gain

Lowering input impedance of preamplifier
 Lower cross talk
 Better charge collection efficiency
 PSRR (all
single ended stages)
Challenges and advantages making analog front-ends in deep submicron technologies
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PSRR for single ended stage (1)
So
KU 
 g m  rL || rDS 
Si
NO  Ni 
Z DS ( s)
Z DS ( s)  Z L ( s)
Challenges and advantages making analog front-ends in deep submicron technologies
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PSRR for single ended stage (2)
SO  KU  Se  NO
S f  f  SO
Se  Si  S f
Loop gain
KU
1
SO  Si
 NO
1  KU  f
1  KU  f
Driving KU improves PSRR.
All single ended stages should be designed as
feedback amplifiers with high open loop gain.
Challenges and advantages making analog front-ends in deep submicron technologies
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PSRR for single ended stage (3)
Power supply disturbance (1V) seen at cascode output working in open loop configuration
(red) and in transimpedance preamplifier (blue). 130nm version of front end.
Challenges and advantages making analog front-ends in deep submicron technologies
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Basic configurations for gain boosting
Intrinsic gain in 250nm ~70 V/V  we need 70 to 80dB (2000 to 10000 V/V)…
Challenges and advantages making analog front-ends in deep submicron technologies
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Cascade
g m1
gm2
KU 

g L  g DS1 g L  g DS 2
 Two stage i.e. two pole circuit; needs to be stabilized
 Significant gain after first stage; Miller effect in case of
driving from high impedance (as for silicon detector)  not
used as an preamplifier stage
 PSRR defined by gain of first stage only
 In 90 nm the gain of cascade is significantly degraded
because of intrinsic transistor gain, some circuits which
works in 250nm version shows bad PSRR characteristic
Challenges and advantages making analog front-ends in deep submicron technologies
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Cascode; common source – common gate
amplifier
KU 
g DS1
 g m1
g DS 2  g L
 gL
g m 2  g DS 2
KU 1 
 g m1 g DS 2  g L
gm2
gL
GBW 
g m1
2 COUT
 single stage amplifier; one dominant pole
 good PSRR
 no Miller effect (low gain of common source stage)
 If cascode load RL very high the overall gain KU comparable with cascade
Challenges and advantages making analog front-ends in deep submicron technologies
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Regulated cascode
KU 
 g m1
g DS1  g DS 2 g DS 3

 gL
gm2
g m3
 Cascode transistor controlled with common source amplifier
 Higher output conductance of cascode; possible higher gain
 GBW the same as for simple cascode
Challenges and advantages making analog front-ends in deep submicron technologies
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Boosting bandwidth and gain in cascode
GBW 
g m1
2 COUT
 g m1
KU 
g DS1  g DS 2
 gL
gm2
 Extra current source to drain of M1  increase of gm1
 Direct impact on gain bandwidth
 Gain changed according to output conductance of cascode and
active load
Challenges and advantages making analog front-ends in deep submicron technologies
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Active load for cascode stage (cascode
load)
rOUT  g m 2  rDS 2  rDS1
 Amplification of rDS1 by gm2
 For our application; OK for 250nm, not sufficient for 130 & 90nm
Challenges and advantages making analog front-ends in deep submicron technologies
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Active load for cascode stage (regulated
cascode load)
rOUT  g m 2  rDS 2  g m3  rDS 3  rDS1
 Amplification of rDS1 by gm2 and gm3
 Used in 130 & 90nm versions of preamplifiers
Challenges and advantages making analog front-ends in deep submicron technologies
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Biasing of the cascode
 All, four, transistors must be in the saturation (VDS ≥ VGS
– VT)
 Technology scaling  Vdd diminished from 2.5V in
250nm to 1.2V in 130nm and 90nm CMOS  possible
problems with dynamic range
 Solution  subthreshold operation (VGS ≈ VT)
 Minimum VDS SAT for weak inversion roughly 5 UT
(125mV)
Challenges and advantages making analog front-ends in deep submicron technologies
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Biasing transistors in weak inversion; some
consequences
Challenges and advantages making analog front-ends in deep submicron technologies
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Impact of the inversion order on the speed
of CMOS circuit
Transit frequency ft as a function of inversion order for 250nm CMOS technology *
For devices biased in weak inversion we never obtain highest possible speed of a
given technology
*
C.Enz, “MOS transistor modeling for RF IC design”, IEEE J.Solid-State Circ., vol. 35, no. 2, pp.186-201)
Challenges and advantages making analog front-ends in deep submicron technologies
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Noise of the active load (1)
If all transistor in weak inversion the gm is defined only by current  all gm the same
Increase of input series noise by ~40%!
Challenges and advantages making analog front-ends in deep submicron technologies
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Noise of the active load (2)
Resistive degeneration of gm works
But we have to spend another ~100mV taken out from Vdd…
Challenges and advantages making analog front-ends in deep submicron technologies
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Noise optimization in CR-RCn filters for
multi-channel FE electronics (remainder)
v
ENC[C ] FV  ns c d
f
vn thermal
series
parallel
t peak  Fi 
f
AFP
in feed
f

inp
f
 t peak
4  k T  n 
gm
 4  k  T    n  g mf
CR-RC
CR-RC2
CR-RC3
FV
0.96
0.92
0.97
Fi
0.96
0.8
0.72

1
1 I f
Resistive feedback
1 2
  I f
2 3
in feed
f
Challenges and advantages making analog front-ends in deep submicron technologies




4  k T
Rf
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Transconductance in MOS transistor (EKV)
Specific current
W
I S  2  n  K P  U T2
L
UT 
k T
q
WI/SI interpolation for If=ID/IS
1
G( I f ) 
1
I f   I f 1
2
Transconductance:
g m  G( I f )
ID
nU T
gm in weak inversion
IBM 130nm
NMOS
L=300nm
 Weak inversion provides highest transconductance at a given bias current
 Some technologies report excess noise for devices in strong inversion
 Conclusion; weak inversion in input transistor is good from the standpoint of
power consumption/noise optimization
Challenges and advantages making analog front-ends in deep submicron technologies
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Comparison of architectures and
performances of front ends
implemented in 250, 130 & 90nm
processes
Challenges and advantages making analog front-ends in deep submicron technologies
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Front end channel in IBM 250nm
(ABCN250)
6 mV/fC
tp 13 ns
36 mV/fC
tp 18 ns
100 mV/fC
tp 22 ns
Challenges and advantages making analog front-ends in deep submicron technologies
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Front end channel in 130nm & 90nm
technology (SCT short strips)
5.5 mV/fC
tp 8 ns
30 mV/fC
tp 18 ns
100 mV/fC
tp 22 ns
Challenges and advantages making analog front-ends in deep submicron technologies
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Preamplifiers open loop gain
90nm, 70dB, GBW=3.5GHz
Iin=80uA
130nm, 80dB, GBW=2GHz
Iin=80uA
250nm, 85dB, GBW=1.2GHz
Iin=140uA
Challenges and advantages making analog front-ends in deep submicron technologies
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Preamplifiers input impedances
250nm, 85dB, 330Ω @ 25MHz
Iin=140uA
130nm, 330Ω @25MHz
Iin=80uA
In all cases the cross talk signals less than 3%
Detector 1.5 pF to bulk + 2x 1.6 pF to neighbor
90nm, 380Ω @25mHz
Iin=80uA
Challenges and advantages making analog front-ends in deep submicron technologies
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PSRR *
1/PSRR
250nm, -3dBdB @ 25MHz
Iin=140uA, Cin=5pF to GND
130nm, -0.5dB @ 25MHz
Iin=80uA, Cin=5pF to GND
*
PSRR defined as the ratio of the 1V signal at the power supply line to the
signal at the output. For two different front end one should also look at
the charge gain!
90nm, +0.5dB @ 25MHz
Iin=80uA, Cin=5pF to GND
Challenges and advantages making analog front-ends in deep submicron technologies
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PSRR (2)
PSRR improves when:
 Cin decreases (also in case of real detector when part of the detector capacitance is
connected to neighboring channel)
 Bias current increases (GBW increases  loop gain increases)
Challenges and advantages making analog front-ends in deep submicron technologies
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Phase margin
90nm
130nm
We want to have 90 degree for nominal input capacitance (5pF), this has
impact on input impedance and PSRR but safety first.
Challenges and advantages making analog front-ends in deep submicron technologies
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Linearity and dynamic range
In 250nm version the dynamic range (limit in discriminator stage - might be adjusted) is about 12fC
In 130nm and 90nm version linear range up to 6fC
Difference caused by Vdd (2.5V in 250nm, 1.2V in 130nm and 90nm versions)
Challenges and advantages making analog front-ends in deep submicron technologies
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Comparison of power consumption at
constant ENC
Comparison of power consumption done for Cdetector = 5pF,
Ileakage=600nA and ENC = 800e250nm
130nm
90nm
Iinput
140uA
100uA
100uA
Itotal
280uA
180uA
180uA
Vdd
2.5V (2.2V)
1.2V
1.2V
Challenges and advantages making analog front-ends in deep submicron technologies
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Conclusion
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Big improvement in noise/power performance from 250nm to 130 and
90nm versions
Some improvements in AC characteristics due to higher bandwidth in
newer technologies (better PSRR and input impedance). Differences in
between 130nm and 90nm almost negligible. 90nm shows higher
bandwidth but lower gain than 130nm. This has slight impact on
differences between input impedance, PSRR and phase margin.
Dynamic range in 90nm and 130nm lower than in 250nm but still
sufficient for tracking applications (6fC range with gain of 100mV/fC)
For 130nm and 90nm front end amplifiers we need 1.2V which is a
nominal Vdd for those technologies. It means that the input voltage
for on chip LDO must be higher than nominal.
Improvements between 250nm and 130/90nm in terms of noise/power
performance due to:
 Excess noise in 250nm (in the order of 30%)
 Better transconductance parameter in 130/90nm
 Higher ft (less power in buffer/shaper/discriminator stages)
Challenges and advantages making analog front-ends in deep submicron technologies
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Addendum
Challenges and advantages making analog front-ends in deep submicron technologies
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Principles of the silicon detectors for
tracking applications
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p-n junction reverse biased forms
the detection zone
Ionization along the track of the
high-energy particle
For 300µm Si detector the most
probable signal is around 3.5fC
(non-irradiated detector)
Electric field proportional to bias
provides drifting of the created
charge – induced current is
readout by the Front-End
electronics
Spatial resolution provided by the
segmentation of the detector
Challenges and advantages making analog front-ends in deep submicron technologies
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Reception of signals from silicon detector – basic
configuration of the preamplifier
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Charge sensitive preamplifier
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Delta-Dirac current pulses integrated on
feedback capacitance
Discharge provided by the feedback resistor
(prevents saturation)
Mode of the preamplifier is defined by
feedback time constant τF=RF×CF
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τF comparable with the time constant of
the shaper  transimpedance preamplifier
τF >> time constant of the shaper  charge
amplifier
Challenges and advantages making analog front-ends in deep submicron technologies
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Input impedance and cross-talk signals for
charge and transimpedance amplifiers
Z F ( s)
Z IN ( s) 
KV ( s )

Cross Talk ( s ) 
Z IN ( s )
Z IN ( s )  Z IS ( s )
Input impedance and cross-talk for
amplifier with 83dB gain and 800MHz
Gain Bandwidth Product (GBP) working
in charge and transimpedance
configuration
Challenges and advantages making analog front-ends in deep submicron technologies
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Influence of GBP on preamplifier input
impedance and cross-talk signals

2 lower Gain-Bandwidth Product  2  higher input impedance
and cross-talk signals
Challenges and advantages making analog front-ends in deep submicron technologies
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Noise sources in MOS transistor
Noise spectra densities of the elementary noise sources:
2
Channel thermal noise  ind  4k T    g mb  g m  f  4k T   n g m f


Gate Induced Current noise (GIC):
i  8k T    g gs f
2
ng
2
4 2 COX
g gs  
45 n g m
COX  COXU W  L
1
1 I f
1 2
  I f
2 3





Channel thermal GIC noise correlation  ing ind
 4k T   j COX f
6
Ka
g m2
 2
f
Flicker (1/f) noise  i 
f COXU
W  L
2
nf
Challenges and advantages making analog front-ends in deep submicron technologies
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Noise filtering in multi-channel FE
electronics
ENC[C ] FV 



v ns
c d
f
t peak  Fi 
inp
f
 t peak
CR-RCn continuous filters – simplicity and
performance (1 high-pass + n low-pass stages)
ENC – Equivalent Noise Charge:
Output Noise / Pulse Gain
tpeak defined by timing requirements, Cd defined by
experiment  ENC optimised by controlling the
series and parallel noise sources  choice of the
optimal input device
Challenges and advantages making analog front-ends in deep submicron technologies
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Noise optimization of the input transistor
ENC series noise contribution of the input transistor as a function
of device dimensions (IBM 130nm, input transistor NMOS
L=300nm, detector capacitance 10pF )
Challenges and advantages making analog front-ends in deep submicron technologies
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