Download Destructive Single Event Effects - Istituto Nazionale di Fisica Nucleare

Industrial applications
of ionizing radiation sources
(Destructive Single Event Effects)
Andrea Candelori
Istituto Nazionale di Fisica Nucleare and Dipartimento di Fisica, Padova
1
Material for study
1) F. W. Sexton, “Destructive Single-Event Effects in Semiconductor Devices and ICs",
IEEE Trans. Nucl. Sci., vol 50, n.3, June 2003, pp. 603-621, and references therein.
2
Single event effects (SEE)
Definition:
“Single event effects (SEE) are individual events which occur when a single incident ionising
particle deposits in a sensitive volume of the device enough energy in form of ionization to
cause an effect in a device”.
Single event effects (SEE) can be:
-destructive events:
Single Event Burnout (SEB) in power MOSFET
Single Event Gate Rupture (SEGR) power MOSFET
Single Event Snapback (SES) in MOSFET
Single Event Latch-up (SEL) in CMOS technologies
-non destructive events:
Single Event Upset (SEU)
Single Event Drain Current Collapse (SEDC2)
Single Event Transient (SET)
Single Event Disturb (SED)
Single Event Functional Interrupt (SEFI)
3
Ionization track: reminder
0.1 m
An energetic ionizing particle going through a semiconductor material creates a track of
ionization with a radius typically less than 1 m (i.e., higher than the minimum channel
length of the current CMOS technologies) and within which the carrier density
decreases from the center.
4
Ion shunt effect
Illustration of the ion shunt effect:
the high charge density along a track can connect devices junctions.
5
Charge funneling: reminder
Microscopic mechanism
If an ion track traverses a reversed biased p-n junction the density of ionization can be so
high that the resulting current flow collapses the field across the junction and the collection
charge from the track reaches father into the semiconductor than the original depletion
region.
Definition
Charge funneling is the extension of the charge collection from an ionization track to a
region beyond the original depletion depth:
The charge funneling effect.
6
Single Event Effects (SEE) cross section: reminder
The cross section () for Single Event Effects is:
=NSEE/
NSEE: Number of SEE observed
: Particle fluence
WEIBUL FIT
= sat{1-exp[-(L-Lth)/W]S}
sat: saturation value of the cross section
Lth: threshold value for LET
W and s are fitting parameter
A typical measured and ideal SEE cross section curve.
7
Bipolar Junction Transistor (BJT): reminder
PNP type
B
P+
NPN type
E
N
E
N+
IE= IB+ IC
N
P
C
C
Condition
Cut-off
Active region (BE inverse)
Active region (BE direct)
Saturation
base-emitter junction
reverse biased
reverse biased
forward biased
forward biased
Equations in active region
IC= IBb
P
B
base-collector junction
reverse biased
forward biased
reverse biased
forward biased
Equations in saturation
IC,max= IB, max b
IC is the collector current, IB is the base current, b>>1 is the gain.
8
Power MOSFET
-Power MOSFETs are power devices capable of conducting large currents when turned in the
ON state and withstanding large voltage when turned in the OFF state.
-Current flow between the n-drain (substrate) and the n+-source in power n-MOSFET is
turned ON and turned OFF for positive values of the drain-to-source voltage VDS by
modulating the surface conductivity under the poly gate which is controlled by the gate-tosource voltage (VGS)
-The n+-source and the p-body contacts are short-circuited.
Cross section of a typical
n-channel power MOSFET
Current flow in a n-channel power MOSFET
9
Power n-MOSFET operation
-VGS<0 V: the n-epi surface region at the SiO2/Si interface becomes depleted and then approach to
strong inversion. The channel region (p-body surface region along the Si/SiO2 interface) approach
strong accumulation. The power n-MOSFET is turned OFF and no current flows.
-VGS>0 V: the n-epi surface region at the SiO2/Si interface approaches strong accumulation. The
channel region (p-body surface region along the Si/SiO2 interface) becomes depleted and approach
strong inversion, forming a n-type channel along the SiO2/Si surface that couples the drain
(substrate) with the source. The power n-MOSFET turned ON and current flows.
-The threshold voltage (VTH) is the minimum gate source voltage (VGS) to turn on the n-type
channel at the SiO2/Si interface.
Cross section of a n-channel
power MOSFET
Current flow in a n-channel power MOSFET
10
Power MOSFET
Advantages:
-fast switching time;
-high current capability;
-low on resistance;
-low gate current.
Applications:
-on-board space system;
-battery charge assemblies;
-power supply electronics;
-power conditioning systems;
-momentum wheels and controllers.
11
Power MOSFET
Power MOSFETs: large current capabilities are achieved by the parallel connection of
thousands of smaller units cells.
Cross section of a n-channel
power MOSFET
Cross-section for parallel connections
of n-channel power MOSFETs.
12
Power n-MOSFET: parasitic BJT (1)
IE
NPN type
N+
E
VBE
N+
p
B
VCE
P
N
IB
N
C
The parasitic npn Bipolar Junction Transistor (BJT) inherent to a power n-MOSFET. 13
IC
Power n-MOSFET: Single Event Burnout (SEB) and BJT (2)
-A single high-energy heavy ion is capable of destroying a power n-MOSFET.
-the ion going through the voltage supporting layer of the device generates high density of
electron-hole pairs along its track, which can induce high current density up to 104 A/cm2 in
presence of large drain-to-source voltages.
-for VDS>0 (VBS=0 and VGS≤0 can be varied) the hole current density flowing from the n-epi
substrate (collector) through the p-body region (base) below the lateral channel region may
cause a voltage drop exceeding 0.7 V for the base-emitter p-n junction, turning on the
parasitic bipolar junction transistor (emitter=n-source, base=p-body, collector=n-epi layer)
that is an inherent part of the power MOSFET, locally increasing the plasma current several
order of magnitude.
-the resulting very localized power density may be large enough to produce incandescent
temperatures, which are able to lead the device burn-out.
D
I
IE
NPN type
D
N+
I
E
N+
VBE
D
p
B
VCE
P
N
IB
I
N
C
IC
14
Power n-MOSFET: Single Event Burnout (SEB) and epi-layer (3)
The electric field intensity in the lightly doped n-epi region was the main contribution to SEB
sensitivity in power n-MOSFET (VDS>0, VBS=0 and varying VGS0):
-a heavy ion strike close to the n-source (emitter) region generate a dense plasma of electrons and
holes along the track of the ion strike.
-electrons flow to the n-drain (collector) region while holes are swept to the p-body (base)
diffusion.
-As excess holes move through the p-body spreading resistance to the ground contact, a voltage
drop develops that forward biases the parasitic base (p-body)-emitter (n-source) junction.
-Forward biasing leads to further electron injection into the lightly doped n-epi region, which,
under high field condition, then generates additional holes through avalanche multiplication.
Current in the n-epi layer increases regeneratively until the device enters second breakdown and
thermal runway.
D
I
15
Power n-MOSFET: Single Event Burnout (SEB) and review 2-3
Right side
Electrons flow
to the n-drain (collector) region
Holes are swept
to the p-body (base) diffusion
As excess holes move through the p-body spreading resistance to the ground contact, a voltage drop
develops that forward biases the parasitic base (p-body)-emitter (n-source) junction.
Forward biasing leads to further electron injection into the lightly doped n-epi region, which, under
high field condition, then generates additional holes through avalanche multiplication. Current in the
n-epi layer increases regeneratively until the device enters second breakdown and thermal runway.
16
Power MOSFET: Single Event Burnout (SEB)
Photograph of a power MOSFET after SEB.
17
Power MOSFET: Single Event Burnout (SEB) [opzionale]
Experimental set-up for SEB
cross section measurements
Destructive
SEB cross section measurements are independent
on IDS and VGS for a fixed VDS and VBS=0
SEB cross section measurements are independent
on the load resistance
18
Power MOSFET: Single Event Burnout (SEB) [opzionale]
What can be deduced by this plot?
.............................
.............................
.............................
.............................
.............................
.............................
SEB cross section data for the n-power MOSFET "2N6766"
(drain-source breakdown voltage BVDSS=200 V)
at VDS=200V and VGS=VBS=0V during irradiation
19
Power MOSFET: Single Event Burnout (SEB) [opzionale]
Cu, E=200 MeV
LET=28 MeV·cm2/mg
Range 40 m
I, E=90 MeV
LET=30-40 MeV·cm2/mg
Range 15 m
Cl, E=90 MeV
LET=16 MeV·cm2/mg
Range 25 m
What can be deduced by this plot?
.............................
.............................
.............................
.............................
.............................
.............................
SEB cross section data for the n-power MOSFET "2N6766"
(drain-source breakdown voltage BVDSS=200 V)
at increasing VDS and VGS=VBS=0V during irradiation
20
Power MOSFET: Single Event Burnout (SEB) [opzionale]
Cu, E=200 MeV
LET=28 MeV·cm2/mg
Range 40 m
I, E=90 MeV
LET=30-40 MeV·cm2/mg
Range 15 m
Cl, E=90 MeV
LET=16 MeV·cm2/mg
Range 25 m
What can be deduced by this plot?
.............................
.............................
.............................
.............................
.............................
.............................
SEB cross section data for the n-power MOSFET “IRF 130"
(drain-source breakdown voltage BVDSS=100 V)
at increasing VDS and VGS=VBS=0V during irradiation
21
Power MOSFET: Single Event Burnout (SEB)
Factors increasing SEB:
-gain of the parasitic npn transistor;
-spreading resistance in the base region;
-avalanche multiplication in the drain region;
-increase of the epitaxial layer thickness and decrease of the doping level (in presence of high
electron-hole densities, the peak of the electric field can easily shift from the base-collector
junction to the epi-substrate transition region);
Power MOSFET can be hardened to SEB by reducing the distance from the p+ plug to the
body region.
22
Power MOSFET: Single Event Burnout (SEB) and epi-layer (4)
Increase of the epitaxial layer thickness and decrease of the doping level (in presence of high electronhole densities, the peak of the electric field can easily shift from the base-collector junction to the episubstrate transition region) increase the SEB sensitivity.
-Power n-channel MOSFET failed at VDS equal to 20-90% of the rated breakdown voltage of the
device (current induced avalanche in the epitaxial region).
-Power p-channel MOSFET did not experience SEB up to their rated breakdown voltage.
Current Induced Avalanche (CIA), due to electrons, in the epitaxial layer.
Power n-MOSFET (left) and test structure (right)
for studies on the Current Induced Avalanche (CIA),
due to electrons, in the epitaxial layer.
23
Power MOSFET: Single Event Burnout (SEB)
Electric field in the npn structure as a
function of the current density
-In presence of high electron-hole densities, the peak of the electric
field can easily shift from the base-collector junction to the episubstrate transition region. Then by increasing the electron-hole
densities the value of the electric field increases.
-This effects in enhanced by increasing of the epitaxial layer thickness
and by decreasing the doping level increase, taking into account that an
ion generates high electron-hole density along its tracks whose
densities can be higher than the doping levels.
-High electric fields can induced Current Induced Avalanche (CIA),
due to electrons, in the epitaxial layer increasing the elecrton-hole
densities and the electric field.
(f)
24
Power MOSFET: Single Event Burnout (SEB)
SEB depends on the charge distribution along the ion track and not just on the surface LET of the ion:
the charge generation at least as deep as the epi-substrate junction contributes to SEB:
-higher energy ions (higher range) have a lower threshold to SEB than low energy ion (lower range) with
similar LET;
-there is lower charge recombination at higher ion energies, due to the larger track diameter.
Br 150 MeV
Depth
Br 285 MeV
25
Power MOSFET: Single Event Burnout (SEB)
For VDS values at 50% of the rate breakdown voltage, with VGS=0V and VBS=0V
SEB occurs primarily for ion impacts in the channel region close to the p-base region
Ion impact point
26
Power MOSFET: Single Event Burnout (SEB)
Drain current after ion impact
Charge collected at the drain node after the ion impact:
1) first peak charge collection at the drain depletion
region;
2) increasing LET or VDS a second peak appears:
transistor action in the base-emitter junction of the
vertical parasitic BJT. Both peaks moves gradually to
higher charges by increasing LET or VDS;
3) when SEB occurs a high charge peak appears
corresponding to the runway avalanche current
condition. The threshold charge QTH depends on
technology not on the operating conditions.
27
Power MOSFET: Single Event Burnout (SEB)
-Studies of SEB in power MOSFET by using techniques for preventing SEB, by limiting the
current with a series resistor and removing the power within 1 s of detection of high current
condition.
Experimental set-up
28
Power MOSFET: Single Event Burnout (SEB)
-The SEB sensitivity decreases by increasing temperature because the impact ionization rate decreases
by increasing temperature.
Note:
-Difference between static and dynamic operation: the saturation cross section in dynamic mode can be
2 orders of magnitude lower than in static mode.
-By tilting the sample, the 1/cos dependence for LET can not be applied
-By increasing the incidence angle the SEB sensitivity decreases.
-SEB can be induced also by protons and neutrons.
29
Power MOSFET: Single Event Gate Rupture (SEGR)
-Following an heavy ion strike in the center of the channel region of a power n-MOSFET, the
dense plasma of electrons and holes along the ion track separate under the influence of the drain
bias (VDS>0 and VGS=VBS=0V).
-Electrons are rapidly sweep to the n+ substrate (drain), while hole transport towards the oxide end
of the plasma surface and then radially, thought the surface accumulation layer, to the p-body
contact where they are collected.
-These holes, pooling up against the Si/SiO2 interface, induce an image charge on the gate
electrode, leading to a transient increase of the electric field in the gate dielectric.
Electric field at the SiO2/Si interface as a
function of the radial distance from the
heavy ion strike and time following the
strike.
+
+
+
+
+
+
-
+
+
+
+
+
+
-
30
Power MOSFET: Single Event Gate Rupture (SEGR)
-A single high-energy heavy ion that does not cause SEB may produce Single Event Gate Rupture
(SEGR) which is also capable of destroying the Power MOSFET.
-After the ion strike at the center of the gate region holes are driven toward the oxide-end of the
filament, at the interface between the n-epitaxial layer and the gate oxide, where they induce an
image charge in the gate electrode increasing the oxide field. SEGR occurs when the ion strike far
from the p-body region allows a considerable “pool” of holes to be collected at the Si/SiO2 interface
before diffusing to ground by the resistive path, locally increasing the oxide electric field beyond the
breakdown value.
Left: power MOSFET showing an ion strike at the center of the gate region, with holes moving
upward and electrons downwards under the influence of the positive drain voltage.
Right: The distributed RC-circuit model for the hole storage at the end of the strike filament (CIS
31
capacitors) and the leakage path to the grounded body region (resistors).
Power MOSFET: Single Event Gate Rupture (SEGR)
Power n-MOSFET test: fixed VDS, VGS=-1V, =4·104 ions/cm2
Maximum operating conditions
specified by the manufacturer
Breakdown limit for VDS:
0 V <VDS< 73V
Oxide breakdown limit for VGS:
-39V <VGS<0 V
32
Power MOSFET: Single Event Gate Rupture (SEGR)
Power n-MOSFET test: fixed VDS, VGS=-1V, =4·104 ions/cm2
Increasing LET
Effect of the ion
on the oxide.
Response of the substrate
VGS
LET


MeV cm 2

17.8
mg
 0.84  VDS 1  e






 1


50
LET
MeV  cm 2
53
33
mg
Power MOSFET: Single Event Gate Rupture (SEGR)
Power n-MOSFET (tox=50 e 150 nm, VDS=0 e 15 V)
Increasing LET
Effect of the ion
on the oxide.
Response of the substrate
LET


MeV cm 2

18
mg
 0.87  VDS 1  e



107  tox
V
cm

0.7



cos


VGS
LET
 1

MeV  cm 2

53
34
mg
This expression is independent on the channel (n or p) type
Power MOSFET: Single Event Gate Rupture (SEGR)
1998: measure of the current increase for SEGR detection and quick ion beam irradiation
stop, for accurate reading of the fluence to SEGR:
first measurements of the SEGR cross-section.
35
Power MOSFET: SEB and SEGR
Power n-MOSFET
Region I: low VDS values SEGR.
Region II: intermediate VDS values SEGR and SEB.
Region III: high VDS values SEB.
SEB can be prevented by limiting the drain current
SEGR can not be prevented
36
Power MOSFET: SEB and SEGR
-SEGR sensitivity increase for ion impact in the center of the channel
-SEB sensitivity decreases for ion impact in the center of the channel and on the p+ body region.
In source regions SEB occurs only at high LET values.
Maximum SEGR
Maximum SEB
To decrease SEGR sensitivity, decrease the channel length
To decrease SEB sensitivity, extend the p+ plug under the source
37
MOSFET: Single Event Snapback (SES)
NPN type
E
C
N+
N
P
B
Heavy ion induces snapback in MOSFET:
(a) ion injection into the depletion region;
(b) movement of electrons and holes;
(c) activation of the parasitic Bipolar Junction Transistor (BJT) inherent to a MOSFET.
38
CMOS inverter
The inverter is the simplest CMOS logic gate.
-When a low voltage (0 V) is applied at the input, the top p-type MOSFET is conducting (switch closed)
while the bottom n-type MOSFET behaves like an open circuit: the supply voltage (5 V) appears at the
output.
-When a high voltage (5 V) is applied at the input, the bottom n-type MOSFET is conducting (switch
closed) while the top p-type MOSFET behaves like an open circuit: the output voltage is low (0 V).
-The function of this gate can be summarized by the following table:
VDD
S
VIN
VOUT
High
Low
Low
High
p-channel
B MOSFET
VIN
D
D
VIN
VOUT
n-channel
B MOSFET
VOUT
S
VSS
CMOS inverter schematic (left) and standard symbol (right).
39
CMOS inverter: Single Event Latch-up
VIN
-A single high-energy heavy ion is capable of destroying a CMOS inverter by turning on the
inherent p-n-p-n structure: Single Event Latch-up (SEL)
P-MOSFET
S
D
D
S
B
VSS
n-channel
MOSFET B
S
D
D
VOUT
p-channel
MOSFET B
S
VDD
B
N-MOSFET
CMOS inverter: schematic (left) and physical cross section view (right) showing the
inherent p-n-p-n structure triggering the Single Event Latch-up (SEL).
40
CMOS inverter: the inherent p-n-p-n structure
P-MOSFET
N-MOSFET
NPN type
B
S
D
D
S
B
C
N
E
N+
IE= IB+ IC
B
n+
PMOS
D
S p+
NMOS
D
S n+ B p+
C
PNP
P
PNP type
B
E
NPN
p
B
P+
E
N
P
C
n
CMOS inverter: physical cross section view showing the inherent p-n-p-n structure triggering
the Single Event Latch-up (up) and equivalent circuits of the p-n-p-n structure (down)
41
implementing two parasitic BJT transistors.
CMOS inverter: the inherent p-n-p-n structure
VDD
VSS
P-MOSFET
N-MOSFET
S p+
S n+
B n+
N+
P+
VDD
B p+
N+
RS
P+
B
RW
RS
C
N
E
P
P
N-Substrate
P
C
P
B
E
B
N
C
P
NPN
C
P
N
B
P-Well
N
PNP
E
N
N
E
P
VSS
Physical cross section (left) and equivalent circuits (right) of the p-n-p-n structure with the
two parasitic BJT transistors..
42
RW
CMOS inverter: the inherent p-n-p-n structure
VDD
VSS
N-MOSFET
P-MOSFET
B n+
VDD
S p+ B p+
N+
P+
S n+
P+
RS
N+
B
RW
RS
C
N
E
P
P
N-Substrate
P
C
P
B
N
N
P
B
NPN
C
C
P
N
B
P-Well
N
PNP
E
E
E
N
P
VSS
Physical cross section (left) and equivalent circuits (right) of the p-n-p-n structure with the
two parasitic BJT transistors..
43
RW
CMOS technology: Single Event Latchup (SEL)
-In normal operating condition the two parasitic BJT are in high impedance state because the base
and the emitter are shortened.
-The collector of first BJT is connected to the base of the second BJT and viceversa: an unstable
loop is thus inherent to the CMOS technology (IC=IBb.
-Under external excitation (electrical or radiation) one parasitic BJT may be forced into conduction
activating the unstable loop condition.
-A self-maintained low-impedance path is opened between the supply terminal VDD and VSS that may
be followed by a permanent thermal failure.
-This destructive effect for the CMOS technology is called Single Event Latchup (SEL)
VDD
RS
B
C
N
E
N
P
E
N
P
C
P
B
RW
VSS
Physical cross section (left) and equivalent circuits (right) of the p-n-p-n structure.
44
CMOS inverter: I-V characteristics of the p-n-p-n structure
-Once the break-over voltage is surpassed the devices leave the forward blocking region and passes
through the negative resistance region to the ON region.
-If the operating point is such that the device current is higher than the holding current IH and the
device voltage is greater than the holding voltage VH, latchup is maintained.
-In order to eliminate the latchup condition, it is necessary to disconnect the power supply.
-Any condition that place the operating point to the ON region can trigger the latchup: an ion strike
can turn on one or either the two parasitic BJTs and the resulting operation point may results in the
latchup condition.
VDD
RS
B
C
N
E
N
P
E
N
P
C
P
B
RW
VSS
Equivalent circuit (left) and I-V characteristic of the p-n-p-n structure.
45
SEL: n-well
CMOS technology: p-MOSFET in n-well
and n-MOSFET in p substrate
with parasitic pnpn structure
Equivalent circuit for the pnpn structure
Test structure for Single Event
Latchup studies
46
Single Event Latchup
Example of SEL cross section curve induced by ions:
1) the 1/cos() law can be used for SEL;
2) the cross section in saturation is approximatively equal to the well area, i.e. SEL is related to
47
the activation of the vertical parasitic BJT in the pnpn structure.
Single Event Latchup
-Latchup can be induced directly by ions and indirectly by protons and neutrons.
-Latchup induced indirectly by protons and neutrons appear with the technology scaling
down.
-Latch-up sensitivity increases with temperature as a consequence of the bipolar gain
increase with temperature.
What can be deduced from the figure? By increasing the temperature the
SEL threshold . . . . . . . . . and the SEL saturation value . . . . . . . . . .
48
Single Event Latchup
Ions with range higher than 25 m,
ensuring a constant LET through a depth
of 4 to 10 m
Range 12 um
The ion range is an important parameter for Single Event Latchup investigations.
The saturation cross section is sligtly lower than the well area (dashed line)
49
ESA ESCC Basic Specification 25100
50
Single Event Latchup: mitigation techniques
Latch-up mitigation techniques:
-SEL occurs if ßnpn· ßpnp>1: reduce the gain of the parasitic bipolar transistors: for instance
neutron irradiation of the silicon substrate (why neutron irradiation is better than proton
irradiation?);
-minimize the spreading resistance drop in the well and in the substrate (why?);
-minimize the well area;
VDD
N+
VSS
P+
N+
P+
RW
RS
P
P
P
B
N
E
N
C
P
C
E
B
P-Well
N
N-Substrate
51
Single Event Latchup
Latch-up mitigation techniques:
-instead of bulk CMOS technologies, use light doped epitaxial layers on heavily doped
substrates;
-use of n+ deep diffusions around the p-well to connect with the n+ buried layers. This
reduces the parasitic pnp gain to virtually zero and eliminates all active four-layer paths.
VDD
N+
VSS
P+
N+
RW
RS
P
P
P
B
N
E
N
C
P
C
E
Charge collection in diodes fabricated on
bulk and light doped epitaxial layers on
heavily doped substrates
P+
B
P-Well
N
N-Substrate
52
Single Event Latchup
Latch-up mitigation techniques:
-instead of bulk or epitaxial CMOS technologies, use SOI technologies which avoid the pnpn
structure;
-the minimum holding voltage for Latchup is 1 V, so Latchup sensitivity is expected to
vanish for deep submicron CMOS technologies;
-removing the power supply when high current power supply is detected (this does not allow
to avoid latent damage in metal traces on IC, which bring to electromigration failures).
CMOS/epi
Comparison of CMOS technologies:
-on light doped epitaxial layers on heavily doped substrates;
-on insulator.
53
Single Event Drain Current Collapse (SEDC2)
W/L=10µm/0.3µm
10-11
10-11
10-12
10-12
10-13
10-13
10-14
fresh
10-15
10-16
tox=2.5nm
0.5
1
Vg [V]
L
10-14
fresh
10-15
irradiated
0
W/L=0.3µm/10µm
1-2 ions hit the gate oxide
Ig [A]
Ig [A]
tox=2.5nm
Fluence = 65106 I ion/cm2
irradiated
1.5
10-16
0
0.5
1
Vg [V]
1.5
L
W
W
54
Single Event Drain Current Collapse (SEDC2)
Large Aspect Ratio: W/L=10µm/0.3µm
1.0
2.5
fresh
0.8
2.0
0.6
1.5
0.4
Irradiated
0.2
0
Ids [mA]
gm [x10-3 -1]
fresh
Irradiated
1.0
0.5
Vds=100mV
0
0.5
1
Vgs [V]
1.5
0
Vgs=1.2V
0
0.5
1
Vds [V]
1.5
L
W
Transconductance: 10% decrease
Saturation Current: slight variation
55
Single Event Drain Current Collapse (SEDC2)
Small Aspect Ratio: W/L=0.3µm/10µm
1.0
2.5
Vds=100mV
fresh
2.0
fresh
0.6
Ids [µA]
gm [x10-6 -1]
0.8
0.4
0.2
0
0.5
1
Vgs [V]
1.0
0.5
Irradiated
0
Irradiated
1.5
1.5
0
Vgs=1.2V
0
0.5
1
Vds [V]
1.5
L
W
Transconductance: 50% decrease
Saturation Current: 70% decrease
56 2
Single Event Drain Current Collapse (SEDC
)
Origin of the Single Event Drain Current Collapse (SEDC2)
Source
Large Aspect Ratio
Channel
Source
Small
Aspect
Ratio
Drain
The Damaged
region electrically
behaves as a high
impedence region
In small-W transistor SEDC2 may
completely pinch off the channel
Drain Channel
Ion hit
57
Other non-destructive single event effects
-Single Event Upset (SEU): bit flip in a digital element
A SEU is a logic state transaction of a single bit, i.e. the changed of the stored
information from 1 to 0 or from 0 to 1 in a memory cell, induced by the
collections at a sensitive node of the charge generated by a single event. The
SEU is characteristic of the storage memory elements: SRAM (Static Random
Access Memory) and DRAM (Dynamic Random Access Memories)
-Single Event Disturb (SED): bit unstable equilibrium
A SED is an error characteristic of Static Random Access Memories (SRAM)
cells which is initiated or disturbed by a single event, such that it will return to
its original state by itself. The disturb state can last for milliseconds and a
reading of the bit during that time will be erroneous.
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Other non-destructive single event effects
-Single Event Transient (SET): signal transient in digital or analog electronics
The charge collection due to a single event at a location of a digital or analog
circuit may cause a voltage or current transient, which propagates down a path
such that a temporary errors in the circuit functionality occurs at a location at
some distance from the original charge collection site.
-Single Event Functional Interrupt (SEFI): device failure
A SEFI is a single event characteristics of complex digital electronics such as
Filed Gate Programmable Array (FPGA) causing the device to stop from normal
functions, and usually requires a power reset to resume normal operations. It is a
special case of SEU changing an internal control signal.
59
Single Event Transient (SET) in digital electronics
When the transient on a data line occurs during the setup ad hold times for a latch, it can
produce a SET errors (TNS vol.55, n.4, pp.1903-1925)
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CMOS SRAM cell
Schematic of a CMOS SRAM cell: the inverters on each half of the cell are biased in opposite
direction, so that in each case one n-channel transistor and one p-channel transistor is ON and the
other is OFF (up). Layout top view: green regions are the gate polysilicon lines, the blue lines
show the interconnections within the unit cell (left). 3D-view during an ion strike (left).
61
SEU in CMOS SRAM cells
Mesh for the 3D-simulation Davinci.
Evolution of the SEU sensitive area as a function of the ion LET,
including initially only the reverse biased NMOS drain and then also
the reverse biased PMOS drain.
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SEU and SEL charge collection regions in CMOS technologies
Charge collection regions for Single Event Upset (SEU) and Single Event Latchup.
63
Electrical Programmable Read Only Memories (EPROM)
Cross section of a typical EPROM floating gate transistor (left).
Erase mode and programming mode (right)
64
Positive charge Assisted Leakage Current (PALC) in E2PROM
-Failure mechanism in Flash memories irradiated by heavy ions:
charge loss from the floating gate by Positive charge Assisted Leakage Current (PALC)
Threshold voltage distribution of the E2PROM
cells before and after irradiation.
Positive charge assisted 65
leakage current mechanism.
Single event effects (SEE) experience by astronauts
-Apollo 13 is the first space mission leading the man on the moon in 1969.
-Skylab was the first USA space station, launched into orbit in 1973.
-Apollo and Skylab astronauts reported frequent small flashes. These star-like flashes were induced
by cosmic rays and/or individual proton-induced spallation reactions in or near the summation units
of the retina.
Cosmic ray ion traversing the vitreous of the eye
and a spallation reaction at the peripherical retina.
66
Test
67
Test: domande 1-4
1) Dopo aver realizzato lo schema di un MOSFET di potenza a canale n in cui evidenzi la
presenza del BJT parassita, descrivi il meccanismo fisico che porta alla rottura del
dispositivo tramite burn-out (SEB). Quali dati sperimentali vengono considerati per
studiare il burn-out nei MOSFET di potenza a canale n?
2) Quale è la regione più sensibile al burn-out (SEB) di un MOSFET di potenza a causa
dell’impatto da uno ione? Quali sono le tecniche utilizzate per diminuire la sensibilità al
burn-out? Perchè ai fini dello studio del burn-out è rilevante il range dello ione?
3) Dopo aver realizzato lo schema di un MOSFET di potenza a canale n, descrivi il
meccanismo fisico che porta alla rottura del dispositivo per rottura dell’ossido di gate
(SEGR). Quali dati sperimentali vengono considerati per studiare il SEGR nei MOSFET
di potenza a canale n?
4) Al variare del LET dello ione incidente e della Vds del MOSFET di potenza a canale n,
quando diventa predominante il SEB ed il SEGR? Il SEB si può prevenire nei test
sperimentali? Il SEGR si può prevenire nei test sperimentali?
68
Test: domande 5-6
5) Che cos’è il Latch-up (SEL) ed in quali dispositivi è rivelante? Quale è la struttura
parassita la cui attivazione può indurre il Latch-up? Quali tecniche di layout possono
essere utilizzate per prevenire il Latch-up?
6) Che cosa si intende per SEDC2, SET , SEFI, PALC?
69
Note
-Il materiale, la cui raccolta e organizzazione ha richiesto un notevole impegno, può
essere utilizzato liberamente per fini di studio e ricerca, se possibile citandone la
fonte e le referenze.
-Ringrazio tutti coloro che mi segnaleranno parti da correggere/migliorare.
70