Download Introduction to VLSI Design

Introduction to
VLSI Design
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
EE414 VLSI Design
What is this course is about?

Introduction to digital integrated circuits.
» CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay,
noise margins, and power dissipation. Sequential
circuits. Arithmetic, interconnect, and memories.
Programmable logic arrays. Design
methodologies.

What will you learn?
» Understanding, designing, and optimizing digital
circuits with respect to different quality metrics:
cost, speed, power dissipation, and reliability
EE414 VLSI Design
Digital Integrated Circuits
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Introduction: Issues in digital design
The CMOS inverter
Combinational logic structures
Sequential logic gates
Design methodologies
Interconnect: R, L and C
Timing
Arithmetic building blocks
Memories and array structures
EE414 VLSI Design
Digital Integrated Circuits
What is meant by VLSI?
Brief history of evolution
Today’s Chips
Moore’s Law
Machines Making Machines
VLSI Facts of Life

EE414 VLSI Design
What is a VLSI Circuit?
VERY LARGE SCALE
A circuit that has 10k ~
10M transistors on a
single chip
•Still growing as number
of transistors on chip
quadruple every 24
months (Moore’s law!)
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INTEGRATED CIRCUIT
Technique where many
circuit components and
the wiring that connects
them are manufactured
simultaneously on a
compact chip (die)
Brief History
The First Computer: Babbage Difference Engine (1832)
•Executed basic operations
(add, sub, mult, div) in
arbitrary sequences
•Operated in two-cycle
sequence, “Store”, and “Mill”
(execute)
•Included features like
pipelining to make it faster.
•Complexity: 25,000 parts.
•Cost: £17,470 (in 1834!)
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The Electrical Solution
•More cost effective
•Early systems used relays to make simple logic devices
•Still used today in some train safety systems
•The Vacuum Tube
•Originally used for analog processing
•Later, complete digital computers realized
High Point of Tubes: The ENIAC
•18,000 vacuum tubes
•80 ft long, 8.5 ft high, several feet wide
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ENIAC - The first electronic computer
(1946)
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Dawn of the Transistor Age
1947: Bardeen and Brattain
create point-contact transistor
w/two PN junctions. Gain = 18
1951: Shockley develops
junction transistor which can
be manufactured in quantity.
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Early Integration
Jack Kilby, working at Texas Instruments,
invented a monolithic “integrated circuit” in
July 1959.
He had constructed the flip-flop shown in the
patent drawing above.
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Early Integration
In mid 1959, Noyce develops the
first true IC using planar transistors,
back-to-back pn junctions for
isolation, diode-isolated silicon
resistors and SiO2 insulation with
evaporated metal wiring on top
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Practice Makes Perfect
1961: TI and Fairchild introduce first
logic IC’s (cost ~ $50 in quantity!).
This is a dual flip-flop with 4
transistors.
1963: Densities and yields
improve. This circuit has four
flip-flops.
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Practice Makes Perfect
1967: Fairchild markets the first
semi-custom chip. Transistors
(organized in columns) can be easily
rewired to create different circuits.
Circuit has ~150 logic gates.
1968: Noyce and Moore leave Fairchild to form
Intel. They raise $3M in two days and move to
Santa Clara. By 1971 Intel had 500 employees;
by 1983, 21,500 employees and $1.1B in sales.
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The Big Bang
1970: Intel starts selling a 1k bit
RAM, the 1103. Its density and cost
make it the only game in town.
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1971: Ted Hoff at Intel designed the
first microprocessor. The 4004 had
4-bit busses and a clock rate of 108
KHz. It had 2300 transistors and
was built in a 10 um process.
Exponential Growth
1972: 8088 introduced. Had 3,500
transistors supporting a bytewide data path.
1974: Introduction of the 8080. Had
6,000 transistors in a 6 um process.
The clock rate was 2 MHz.
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Today
Many disciplines have contributed to the current state of the
art in VLSI Design:
•Solid State Physics
•Materials Science
•Lithography and fab
•Device modeling
To come up with chips like:
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•Circuit design and
layout
•Architecture design
•Algorithms
•CAD tools
Intel Pentium
•~3.5M
transistors
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Pentium Pro
•Actually a MCM comprising of
microprocessor and L2 cache
Why not make it on
one chip?
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Sun UltraSparc
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Pentium 4

0.18-micron process technology
(2, 1.9, 1.8, 1.7, 1.6, 1.5, and 1.4 GHz)
» Introduction date: August 27, 2001
(2, 1.9 GHz); ...; November 20,
2000 (1.5, 1.4 GHz)
» Level Two cache: 256 KB Advanced
Transfer Cache (Integrated)
» System Bus Speed: 400 MHz
» SSE2 SIMD Extensions
» Transistors: 42 Million
» Typical Use: Desktops and entrylevel workstations
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Pentium 4
0.13-micron
process technology
(2.53, 2.2, 2 GHz)
»Introduction date: January 7, 2002
»Level Two cache: 512 KB Advanced
»Transistors: 55 Million
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Intel’s McKinley
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Introduction date: Mid
2002
Caches: 32KB L1,
256 KB L2, 3MB L3 (onchip)
Clock: 1GHz
Transistors: 221 Million
Area: 464mm2
Typical Use:
High-end servers
Future versions:
5GHz, 0.13-micron
technology
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Evolution of Electronics
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Moore’s Law
IIn
1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 12 months.
HHe made a prediction that
semiconductor technology will double its
effectiveness every 18 months
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1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION
Moore’s Law
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16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Electronics, April 19, 1965.
Evolution in Complexity
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Transistor Counts
1 Billion
Transistors
K
1,000,000
100,000
10,000
1,000
i486
i386
80286
100
10
Pentium® III
Pentium® II
Pentium® Pro
Pentium®
8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
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Courtesy, Intel
Moore’s law in Microprocessors
Transistors (MT)
1000
2X growth in 1.96 years!
100
10
486
1
386
286
0.1
0.01
P6
Pentium® proc
8086
8080
8008
4004
8085
0.001
1970
1980
1990
Year
2000
2010
Transistors on Lead Microprocessors double every 2 years
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Courtesy, Intel
Die Size Growth
Die size (mm)
100
10
8080
8008
4004
1
1970
8086
8085
1980
286
386
P6
Pentium
® proc
486
~7% growth per year
~2X growth in 10 years
1990
Year
2000
2010
Die size grows by 14% to satisfy Moore’s Law
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Courtesy, Intel
Frequency
Frequency (Mhz)
10000
Doubles every
2 years
1000
100
486
10
8085
1
0.1
1970
8086 286
P6
Pentium ® proc
386
8080
8008
4004
1980
1990
Year
2000
2010
Lead Microprocessors frequency doubles every 2 years
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Courtesy, Intel
Power Dissipation
Power (Watts)
100
P6
Pentium ® proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase
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Courtesy, Intel
Power will be a major
problem
100000
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
100
Pentium® proc
286 486
8086
10
386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive
EE414 VLSI Design
Courtesy, Intel
Power density
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low temp
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Courtesy, Intel
Not Only Microprocessors
Cell
Phone
Small
Signal RF
Digital Cellular Market
(Phones Shipped)
1996 1997 1998 1999 2000
Units
48M 86M 162M 260M 435M
(data from Texas Instruments)
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Power
RF
Power
Management
Analog
Baseband
Digital Baseband
(DSP + MCU)
Challenges in Digital Design
“Microscopic Problems”
• Ultra-high speed design
• Interconnect
• Noise, Crosstalk
• Reliability, Manufacturability
• Power Dissipation
• Clock distribution.
Everything Looks a Little Different
EE414 VLSI Design
“Macroscopic Issues”
• Time-to-Market
• Millions of Gates
• High-Level Abstractions
• Reuse & IP: Portability
• Predictability
• etc.
…and There’s a Lot of Them!
10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
1,000
1,000,000
10,000
10,000,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Complexity
Logic Transistor per Chip (M)
Productivity Trends
1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10
10,000
100
100,000
1,0001
10
10,000
x
0.1
100
xx
0.01
10
xx
x
1
1,000
21%/Yr. compound
Productivity growth rate
x
x
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
Source: Sematech
Complexity outpaces design productivity
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Courtesy, ITRS Roadmap
Why Scaling?
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Technology shrinks by 0.7/generation
With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
Cost of a function decreases by 2x
But …
» How to design chips with more and more functions?
» Design engineering population does not double every
two years…

Hence, a need for more efficient design methods
» Exploit different levels of abstraction
EE414 VLSI Design
Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
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D
n+
Design Metrics

How to evaluate performance of a
digital circuit (gate, block, …)?
» Cost
» Reliability
» Scalability
» Speed (delay, operating frequency)
» Power dissipation
» Energy to perform a function
EE414 VLSI Design
Cost of Integrated Circuits

NRE (non-recurrent engineering) costs
» design time and effort, mask generation
» one-time cost factor

Recurrent costs
» silicon processing, packaging, test
» proportional to volume
» proportional to chip area
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NRE Cost is Increasing
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Die Cost
Single die
Wafer
Going up to 12” (30cm)
From http://www.amd.com
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Cost per Transistor
cost:
¢-per-transistor
1
0.1
Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982
1985
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1988
1991
1994
1997
2000
2003
2006
2009
2012
Yield
No. of good chips per wafer
Y
100%
Total number of chips per wafer
Wafer cost
Die cost 
Dies per wafer  Die yield
  wafer diameter/2 2   wafer diameter
Dies per wafer 

die area
2  die area
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Defects
 defects per unit area  die area 
die yield  1 




 is approximately 3
die cost  f (die area) 4
EE414 VLSI Design

Some Examples (1994)
Chip
Metal Line
layers width
Wafer
cost
Def./ Area Dies/ Yield
cm2 mm2 wafer
Die
cost
386DX
2
0.90
$900
1.0
43
360
71%
$4
486 DX2
3
0.80
$1200
1.0
81
181
54%
$12
Power PC
601
4
0.80
$1700
1.3
121
115
28%
$53
HP PA 7100
3
0.80
$1300
1.0
196
66
27%
$73
DEC Alpha
3
0.70
$1500
1.2
234
53
19%
$149
Super Sparc
3
0.70
$1700
1.6
256
48
13%
$272
Pentium
3
0.80
$1500
1.5
296
40
9%
$417
EE414 VLSI Design
Reliability―
Noise in Digital Integrated Circuits
v(t)
VDD
i(t)
(a) Inductive coupling
(b) Capacitive coupling
(c) Power and ground
noise
EE414 VLSI Design
DC Operation
Voltage Transfer Characteristic
V(y)
V
VOH = f(VOL)
VOL = f(VOH)
VM = f(VM)
f
OH
V(y)=V(x)
VM Switching Threshold
VOL
VOL
V
OH
V(x)
Nominal Voltage Levels
EE414 VLSI Design
Mapping between analog and digital signals
"1"
V
OH
V
IH
V(y)
V
OH
Slope = -1
Undefined
Region
V
IL
"0"
V
OL
EE414 VLSI Design
Slope = -1
VOL
V
V
IL IH
V(x)
Definition of Noise Margins
"1"
V
OH
Noise margin high
NMH
V
IH
Undefined
Region
V
OL
NML
V
IL
"0"
Gate Output
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Gate Input
Noise margin low
Noise Budget
Allocates gross noise margin to
expected sources of noise
 Sources: supply noise, cross talk,
interference, offset
 Differentiate between fixed and
proportional noise sources

EE414 VLSI Design
Key Reliability Properties

Absolute noise margin values are deceptive
» a floating node is more easily disturbed than a
node driven by a low impedance (in terms of
voltage)

Noise immunity is the more important metric –
the capability to suppress noise sources
 Key metrics: Noise transfer functions, Output
impedance of the driver and input impedance of the
receiver;
EE414 VLSI Design
Regenerative Property
out
v3
out
finv (v)
f(v)
v1
v1
v3
finv(v)
v2
v0
Regenerative
EE414 VLSI Design
in
f(v)
v0
v2
Non-Regenerative
in
Regenerative Property
…
v0
v1
v2
v3
v4
v5
(a) A chain of inverters
V (Volt)
5
v0
3
v1
1
–1
(b) Simulated response of
chain of MOS inverters
0
2
4
6
t (nsec)
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v2
8
10
v6
Fan-in and Fan-out
(a) Fan-out N
M
N
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(b) Fan-in M
The Ideal Gate
Vout
Ri = 
Ro = 0
g=
Fanout = 
Vin
EE414 VLSI Design
NMH = NML = VDD/2
An Old-time Inverter
5.0
V ou t (V)
4.0
NML
3.0
2.0
VM
NMH
1.0
0.0
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1.0
2.0
3.0
Vi n (V)
4.0
5.0
Delay Definitions
Vin
50%
t
Vout
tpHL
tpLH
90%
50%
10%
tf
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t
tr
Ring Oscillator
v1
v0
v
0
v2
v
1
v3
v4
v5
T = 2  tp N
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v5
A First-Order RC Network
R
vin
vout
C
tp = ln (2) t = 0.69 RC
Important model – matches delay of inverter
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Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
Vsupply t T
1 t T
Pave  
p(t )dt 
isupply t dt

t
T t
T
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Energy and Energy-Delay
Power-Delay Product (PDP) =
E = Energy per operation = Pav  tp
Energy-Delay Product (EDP) =
quality metric of gate = E  tp
EE414 VLSI Design
A First-Order RC Network
Vdd
E0->1 = C LVdd2
A1
AN
vin
R
isupply
PMOS
NETWORKvout
NMOS CL
Vout
CL
NETWORK
Vdd
T
T
E 0 1 =  P  t  dt = V dd  i sup ply t  dt = Vdd  CL dV out = C L  V dd 2

0
0
0
T
T
Vdd
1
2
E ca p =  P cap  t  dt =  V out i ca p t  dt =  C L Vout dVout = --- C  V dd
2 L
0
0
0
EE414 VLSI Design
Summary


Digital integrated circuits have come a long
way and still have quite some potential left for
the coming decades
Some interesting challenges ahead
» Getting a clear perspective on the challenges and
potential solutions is the purpose of this book

Understanding the design metrics that govern
digital design is crucial
» Cost, reliability, speed, power and energy
dissipation
EE414 VLSI Design