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NMOS Inverter (E-MOSFET Driver and Load)
Load
iDS
V
1.2V
Th
2
W
1
m
, L
10
m
2
2
W
1
6 A
2

K

6
.
2
x
10
2
L
10
V2
2
Driver
V
1.0V
Th
1
W
m, L11m
1 5
W
4 A
1
5 K

3
.
1
x
10
1
L
V2
1
Transistor Characteristics
2
Electron
mobility

700
cm
/Vsec
n
vDS

6
Gate
oxide
thicknes
s tox20
nm
2
x
10
cm

7
2
Gate
oxide
capacitanc
e C

ox/tox1.77
x
10
F/cm
ox
1
W1
W

2

7
2
K 
C
700
cm
/Vsec)(
1
.77
x
10
F/cm
) 
n
ox  (
2
L 2
L
W


5
2
6
.2
x
10
A
/V
 
L
ECES 352 Winter 2007
Ch 10 MOS Digital
1
NMOS Inverter (E-MOSFET Load Transistor)
G
*
Load transistor has its gate
connected to its drain so
vDS2 = vGS2 (Always)
*
Triode-saturation boundary at
vDSsat2 = vGS2 - VTh2
*
Since VTh2 > 0, for load transistor
vDS2 > vDSsat2 = vGS2 VTh2
= vDS2 VTh2
*
So load transistor is ALWAYS in
saturation ! It cannot operate in the
triode region !
Load’s drain current is 2
always given


i

K
v

V
2
2 GS
2 Th
2
by D
D
S
iDS2
0.08
*
0.06
V
2

K

v
V
2
DD
o
Th
2
0.04
*
0.02
So load transistor
looks
like a
vDS
vDS
2
2
variable
resistance
R
 of size
2
eff
2
iD2
vDS2
ECES 352 Winter 2007
Ch 10 MOS Digital
K
vDS
V
2
2
Th
2
V
v
DD
o

2
K
V
v
V
2
DD
o
Th
2
2
NMOS Inverter (E-MOSFET Driver and Load)
* Voltage transfer characteristic (Vo vs Vi)
* Region I (A to B)
 0 < Vi < VTh1
 iD1 = 0 since drive transistor Q1 is off,
i.e. in cutoff.
 iD2 = 0 since iD2 = iD1 and iD1= 0
* Output voltage is given by
Vo= VDD-VDS2 = VDD-VGS2
= VDD-VTh2
= 5V - 1.2V = 3.8V
Load
V
.2V
Th
2 1
Driver
C
VTh1 1.0V
vo

5V
I
3.8V A
B


0
0
VTh1
=1.0V
ECES 352 Winter 2007
5V
vi

Why not 5V ? Assuming a capacitance load
on the output, when Q1 (driver) turns off,
then Q2 (load) provides current to charge
up the capacitance C so the output Vo can
rise towards VDD.
As Vo rises, VDS2 (still = VGS2) decreases.
When VGS2 decreases to VTh2, then Q2
turns off and stops supplying the charging
current, so Vo cannot rise further.
So Vo cannot rise above VDD - VTh2 = 3.8V
Ch 10 MOS Digital
3
NMOS Inverter (E-MOSFET Driver and Load)
* Region II (B to C)
 Driver comes on in saturation mode
 Load always in saturation mode.
Load
VTh2 1.2 V
W
m, L2 10
m
2 1
iD1  K1vGS1 VTh1  K1vi VTh1
2
A
K2 6.2x10 2
V
6
iD1 iD2 so
Driver
K1vi VTh1  K2VDDvo VTh2
2
VTh1 1.0 V
W1 5m, L1 1m
K1 3.1x104
2
vo VDDVTh2 
A
V2
2
K1
vi VTh1
K2
So vo 3.8V  50vi 1V
vo
iDS1
5V
Driver
B
3.8V A
I
C
A to B
C
vDS1
ECES 352 Winter 2007
II
0
0
Ch 10 MOS Digital
VTh1
=1.0V
5V
4
vi
NMOS Inverter (E-MOSFET Driver and Load)
* Where is point C?
* Driver transistor operating in saturation mode in
region II, so point C is where it leaves saturation,
i.e. where vDS1 = vo = vDSsat1 = vGS1 - VTh1 = vi - VTh1


K
v
(
at
C
)

V

V
 1v
at
C
)

V
v
(
at
C
)

v
at
C
)

V
o
DD
Th
2
i(
Th
1 and
o
i(
Th
1so
K
2
V

V
5

1
.
2
V
DD
Th
2
v
at
C
)

V


1
.
0
V


1
.
47
V
i(
Th
1
K
1

50
1
1
K
2
so
v
(
at
C
)

v
at
C
)

V

1
.
47
V

1
.
0
V

0
.
47
V
o
i(
Th
1
iDS1
vo
3.8V A
B
I
C A to B
vDS1
ECES 352 Winter 2007
II
C
0.47V
0
0
Ch 10 MOS Digital
VTh1 1.47V
=1.0V
5
5V
vi
NMOS Inverter (E-MOSFET Driver and Load)
*
*
*
Where is the equivalent resistance that the load
transistor provides in region II ?
Recall the load transistor acts like a load resistor with
an effective resistance
v
V

v
5

v
DS
2
DD
o
0
R



2
eff
2
2

62
i




K
V

v

V
6
.
2
x
10
A
/
V
3
.
8

v
D
2
2
DD
o
Th
2
o
At point B, vo = 3.8 V and the load transistor is off so
v
5

3
.
8
DS
2

R
at
B




2
eff
2
6 2
i


6
.
2
x
10
A
/
V
3
.
8

3
.
8
D
2
*
iDS1
At point C, vo = 0.47 V so
v
5

0
.
47
DS
2
R
at
C



67
K
2
eff
2
6 2
i


6
.
2
x
10
A
/
V
3
.
8

0
.
47
D
2

vo
3.8V A
B
I
C A to B
vDS1
ECES 352 Winter 2007
II
C
0.47V
0
0
Ch 10 MOS Digital
VTh1 1.47V
=1.0V
6
5V
vi
NMOS Inverter (E-MOSFET Driver and Load)
* Region III (C to D)
 Driver in triode mode
Load
VTh2 1.2 V


2vV vv and
K
W
m, L2 10
m
2 1
6
K2 6.2x10
2
vGS
iD
K
V
v
v
1
12
1
Th
1
DS
1
DS
1
A
V2
1
i
Th
1 o
2
o
iD
iD2 and
the
load
isstill
in
saturat
so
1
Driver

VTh1 1.0 V

2
vi V
K
v
v
K
V

v
V
12
Th
1
o
o
2
DD
o
Th
2
W1 5m, L1 1m
2
This
gives
v
v
o(
i)
A
K1 3.1x10 2
V
4
vo
iDS1
5V
3.8V A
D
B
I
C
A to B
vDS1
ECES 352 Winter 2007
II
C
0.47V
0
Ch 10 MOS
III
0
VTh1
Digital=1.0V
D
1.47V
7
5V
vi
NMOS Inverter (E-MOSFET Driver and Load)
* Region III (C to D)


2
2
vi V
vovo
V
K
K

v
V
12
Th
1
2
DD
o
Th
2
2
2
K
V
vi V
voK
V
K
K
v
2

V
K

V
0
1
2
o
2
DD
Th
2
1
Th
1
2
DD
Th
2 
Point D

4 2

5

4

5
2.36
3.16
8
x
10
v
2
x
10
3
.1
x
10v
1
.0
V
.95
x
10
0
o
i
v
at
D
)5V so
i(
2
1.81
v

1
.96
v
v
0
.28

0
o
i
o
v
at
D
)4
.00
V
3
.96
V0
.04
V
o(
2
1.81


1
.96
v

1
.81

1
.96
v
4
(0
.28
)
i
i 
v
o
2
When
v
3
.8V
, v
0
.05
V
i
o
vi0
 0.98
20.28
v
.98
v
0
.9
v
0
.9
o
i
i
vo
iDS1
5V
3.8 V A
D
B
I
C
III
0.47 V
A to B
C
vDS1
ECES 352 Winter 2007
II
0.05 V 0
Ch 10 MOS
0
VTh1
Digital=1.0 V
D
1.47 V 3.8 V 5V
8
vi
Noise Margins for NMOS Inverter
(E-MOSFET Driver and Load)
* Noise margin for low state

high
high
low


vo
5V
VOH = 3.8 V
VOL=
0.05V
Vi =VOL
= 0.05V
ECES 352 Winter 2007
NML= VIL - VOL
=1.0V- 0.05V = 0.95V

5V
VIL=VTh1
Vi =VOH
= 1.0V
= 3.8 V
vi

Ch 10 MOS Digital
Measures degree of inverter
sensitivity to noise for the low
state, i.e. how large a noise
signal causes problems.
Assumes identical inverter
providing input signal
Noise Margin =
NML
= VIL - VOL where
 VOL = output voltage
when input set to VOH
 VIL = maximum input
voltage recognized as a
low input
For this inverter design, NML
is much larger than for
resistor load case!
Can change NML by changing
K’s or VTh1.
9
Noise Margins for NMOS Inverter
(E-MOSFET Driver and Load)
*
low
low
high
Noise margin for high state
 Noise Margin = NMH = VOH – VIH where
 VOH = output high voltage when
input set to VOL
 VIH = minimum input voltage
recognized as a high input
 Maybe find VIH by using vo(vi) for
region II (Q1 in saturation). Recall
vo
I
VOH = 3.8 V
Slope
= -1
II
K
 then
v
V

V
 1
v
V
o
DD
Th
2
i
Th
1
K
2
III
dv
K
o

 1

50


1This
is
not
possi
dv
K
i
2
NMH= VOH - VIH
= 3.8 V- 1.53 V
= 2.27 V

vo0.98
vi 0.9 0.98
vi 0.920.28
Vo= 0.32 V
VOL=
0.05V
So must find VIH by using vo(vi) for the
device in region III.
vi
VIH=1.53 V
ECES 352 Winter 2007
Vi =VOH
= 3.8 V
0.98
dv
vi 0.9
o
0.98


1
2
dv
i
0.98
vi 0.9 0.28
vi 1.53
VV
IH
and
vo(vi V
)0.32
V
IH
Ch 10 MOS Digital
10
NMOS Inverter (E-MOSFET Driver and Load)
Load
* Load transistor Q2 acts as a variable
load resistance.
* Since VTh2 > 0 for load transistor
(enhancement type), and vDS2 = vGS2
then
vDS2 > vDSsat2 =
vGS2 - VTh2
= vDS2 VTh2
* So load transistor is ALWAYS in
v
2current is
iD
K

V
saturation
mode,
so
its
2
2
GS
2
Th
2
VTh2 1.2 V
W
m, L2 10
m
2 1
6
K2 6.2x10
A
V2
Driver
VTh1 1.0 V
W1 5m, L1 1m
K1 3.1x104
A
V2
V
2

K

v
V
2
DD
o
Th
2
iDS1
vDS
V
vo
2
DD
* Effective
resistance
ofLoad
QR
is2eff(vo)
R

2eff
2 2
Load line for
variable
load resistance.
iD2
K
V
vo V
2
DD
Th
2
Ex
.
D
C
Atvo 3.5V R
.8M

2eff2
A to B
Atvo 0.5V R
K

2eff60
vDS1
ECES 352 Winter 2007
Atvo 0.05
VR
K

2eff 57
Ch 10 MOS Digital
11
Propagation Delays and Switching Times
for NMOS Inverters
Load
VTh2 1.2 V
iD2
W
m, L2 10
m
2 1
iC
6
K2 6.2x10
A
V2
Driver
C
VTh1 1.0 V
W1 5m, L1 1m
iD1
K1 3.1x104
A
V2
* Output goes from Low to High
 Driver Q1 turns off
 Load Q2 provides current to
charge up C.
dv
iC
C o
iD
2
dt
v
2K
V
2
iD
K
V

V
v
2
2
GS
2
Th
2
2
DD
Th
2
o
dv
o K
2
 2
V

V
v
DD
Th
2
o
dt C
* Output goes from High to Low
* Driver Q1 turns on to discharge C (So vi = VOH = 3.8 V)
* Driver initially in saturation mode, then triode mode
* Load Q2 produces current that must be absorbed by Q1.
iD1iD2iC
dv
2
iCC o andiD2 K2V
V
DD
Th
2v
o
dt
2
2
Saturation iD1K
V
V
V
1v
GS
1
Th
1 K
1
OH
Th
1 or
Triode

K2V

2
vGS1VTh1vDS1vDS
iD1K
12
1
1


dv
2 K
2
o K


2
V

V

v
1
V

V
or
DD
Th
2
o
OH
Th
1
dt C
C
dv
2 K
2
o K
1



2
V

V

v
V

V
v

v
DD
Th
2 o  2
OH
Th
1
o
o
dt C
C
i

i
driver
can
discharge
the
capaci
e
D
1
D
2 so

2
V
OH
Th
1v
o v
o
ECES 352 Winter 2007
These equations
are not as easily
integrated to find
vo (vi ).
Ch 10 MOS Digital
12

Propagation Delay for NMOS Inverter
*
Load
iD2
iC
Driver
C
iD1
Output goes from High (VOH = 3.8V) to Low (VOL = 0.05V)
 Driver Q1 (starts from P R  S  T)
 At outset, Q1 is off (P), and vDS1 = vo = VOH = 3.8V, vi < VTh1
 Driver turns on (P to R) when vGS1 is switched to VOH = 3.8 V.
 Driver initially in saturation mode, then moves into triode
as capacitor discharges and vDS1 decreases as Q1 moves
along constant vGS1 characteristic (R  S  T).
 Q1 ends at (T) , where vGS1 = vi = 3.8V and
vDS1 = vo = VOL = 0.05V.
 Load Q2 (goes from R’  S’  T’) (always in saturation)
Driver
Load
iDS1
iDS2
T’
0.08
vGS2 = vDS2 = VDD-VOL = 4.95V
R
S
0.06
vGS1 = 3.8 V
S’
0.04
0.02
T
P
vo =VOL
vo =VOH = 3.8 V
ECES 352 Winter 2007
= 0.05 V
vDS1
vGS2 = vDS2 = VDD-VOH = 1.2V
vDS2
R’ P’
Ch 10 MOS Digital
13
Approximate Analysis of Propagation Delays
*
*
Load
iD2
iC
Driver
dv
i

Co
i

i

i
C
C
D
2
D
1
dt
where
i

i
discharge
the
C
D
1
D
2 to
C
*
We select point S to be the point where the output
voltage has fallen halfway from its peak value VOH to
its minimum value VOL.
1
1




v
S

V

V

3
.
8
V

0
.
05
V

1
.
93
V
o
OL
OH
2
2
*
We define the high to low propagation time tPHL as the
time it takes for the output to go from vo = vo(R) = VOH =
3.8 V to vo=vo(S) = 1/2(VOH +VOL) = 1.93 V.

v
v(S)vo(R
) C 1

V
V
iCC o Co

V
OL
OH
OH



t
tPHL
tPHL
2

iD1
Driver
iDS1
S
T
Output goes from High (VOH = 3.8V) to Low (VOL = 0.05V)
As an approximation, we use average currents for the
transistors to calculate an average discharge current for
the capacitor.
R
vGS1 = 3.8 V
P
vo =VOL
vo =VOH = 3.8 V
ECES 352 Winter 2007
= 0.05 V
C 1
V


V
0
OL
OH


tPHL
2

C1
C 1

V

tPHL
  V
V

V
OL
OH
OL
OH



iC2
 iD2iD

12
vDS1
C 1
V


V
0
OH
OL


iD
iD22

1
Ch 10 MOS Digital
14
Approximate Analysis of Propagation Delays
Load
iD2
*
*
Output goes from High (VOH = 3.8V) to Low (VOL = 0.05V)
Average current for the DRIVER transistor.
*
At point R, vi = vi(R) = VOH =3.8V and driver is in
saturation region since the output has not fallen so
vo = vo(R) = VOH
2
2




i
(
R
)

K
v

V

K
V

V
D
1
1
GS
1
Th
1
1
OH
Th
1
iC
Driver
C
1


i

i
(
R
)
i
(
S
)
D
1
D
1
D
1
2
2
4A



3
.
1
x
10
3
.
8
V

1
.
0
V

2
.
4
mA
2
V
iD1
*
Driver
At point S,
1
1




v
v
S
V

V
3
.8
V

0
.05
V
1
.93
V
o
o
OL
OH
2
2
But
v

v

V

V

V

3
.8

1
.0

2
.8
V
DSsat
1
GS
1
TH
1
OH
TH
1

so
v

v
S
1
.93
V

v

2
.8
V
DS
1
o
DSsat
1
iDS1
sothe
driver
is
in the
triode
region
at
point
S!
*
S
T
R
vGS1 = 3.8 V
P
vo =VOH = 3.8 V
ECES 352 Winter 2007
*
vDS1



So drain current at point S is2
given by
2






i
S

K
2
v

V
v

v

K
2
V

V
v

v
D
1
1GS
1Th
1
DS
1DS
1
1
OH
Th
1
o
o


A
4
2



3
.
1
x
10
2
3
.
8
V

1
.
0
V
1
.
93
V

(
1
.
93
V
)

2
.
2
m
2
V
So average
drain current for1
the driver is
1



i

i
(
R
)

i
(
S
)

2
.
4
mA

2
.
2
mA

2
.
3
m
D
1
D
1
D
1
2
2
Ch 10 MOS Digital
15
Approximate Analysis of Propagation Delays
*
*
Load
iD2
1

i

i
(
R
')

i
(
S
')
D
2
D
2
D
2
2
iC
*
Driver
C
*
At point S’,
1
1






v

v
S

V

V

3
.
8
V

0
.
05
V

1
.
93
V
o
o
OL
OH
2
2
so


v

V

v
S

5
V

1
.
93
V

3
.
07
V

v
DS
2
DD
o
GS
2
*
So drain current at point S’ is given by
Load
T’
0.08
vGS2 = vDS2 = VDD-VOL
= 4.95V
0.06
vGS1 = 3.8 V
0.04
At point R’, vGS2 = VDD -VOH= 5.0V - 3.8V=1.2V and the
load is in saturation but barely on so
2
2




i
(
R
'
)

K
v

V

K
1
.
2
V

1
.
2
V

0
D
2
2
GS
2
Th
2
2
iD1
iDS2
Output goes from High (VOH = 3.8V) to Low (VOL = 0.05V)
Average current for the LOAD transistor.
A
2
2

6




i
(
S
'
)

K
v

V

6
.
2
x
10
3
.
07
V

1
.
2
V
D
2
2
GS
2
Th
2
2
V

5

2
.
2
x
10
A

0
.
022
mA
S’
*
0.02
vGS2 = vDS2 = VDD-VOH = 1.2V
R’
ECES 352 Winter 2007
vDS2
So average
drain current 1
for the load is
1


i

i
(
R
'
)

i
(
S
'
)

0
mA

0
.
022
mA

0
.
01
m
D
2
D
2
D
2
2
2
Ch 10 MOS Digital

16

Approximate Analysis of Propagation Delays
*
*
Load
iD2
i

i

2
.
3
mA

0
.
011
mA

2
.
289
mA

2
.
3
m
D
1
D
2
iC
Driver
Output goes from High to Low.
Using the average currents for the transistors we get
an average discharge current for the capacitor
*
Defining the high to low propagation time tPHL as the
time it takes for the output to go from vo = VOH =
3.8V to vo = 1/2(VOH +VOL) = 1.93V.
C
1



t

V

V
PHL
OH
OL


i

i
2


D
1
D
2
*
For a capacitance load of 10 pF, we get
C
iD1
Driver
*
iDS1
C 1
VOHVOL
tPHL

iD1 iD2 2


10pF 1



3
.
8
V

0
.
05
V


2.3 mA
2

8
8x10
sec0.8 nsec
S
R
vGS1 = 3.8 V *
*
T
P
vDS1
This propagation delay is small since the driver’s
current is much larger than the load’s current
(since K1 >> K2).
NOTE: The load in this case (high to low) is
delaying (slightly) the transition by supplying current
which tends to charge up the capacitance load.
vo =VOH = 3.8 V
ECES 352 Winter 2007
Ch 10 MOS Digital
17
Propagation Delay for NMOS Inverter
* Output goes from Low (VOL= 0.05V) to High (VOH = 3.8V)
Load

iD2

iC
Driver

C

Driver Q1 turns off and remains off (starts from T  P)
At outset, vo = VOL = 0.05V, vDS2 =VDD - vo = 5V-0.05V = 4.95V
As the load Q2 charges up the capacitor, vo increases and
vDS2 (and vGS2 ) decreases, and the load Q2 goes from
T’
 S’  R’ (Q2 always remains in saturation).
At S’,
1
1






v

v
S

V

V

3
.
8
V

0
.
05
V

1
.
93
V
o
o
OL
OH
2
2
so




v
S
'
V

v
S

5
V

1
.
93
V

3
.
07
V

v
S
'
DS
2
DD
o
GS
2
iD1
Driver
Load
iDS2
iDS1
T’
0.08
vGS2 = vDS2 = VDD-VOL = 4.95V
0.06
S
R
vGS1 = 3.8 V
0.04
S’ vGS2 = vDS2 = 3.07V
0.02
T
P
vo =VOH = 3.8 V
ECES 352 Winter 2007
vGS2 = vDS2 = VDD-VOH = 1.2V
vDS1
vDS2
R’
Ch 10 MOS Digital
18
Approximate Analysis of Propagation Delays
*
*
Load
iD2
iC
Output goes from Low (VOL = 0.05V) to High (VOH = 3.8V).
As an approximation, we use an average current for the
load transistor to calculate an average charging current
for the capacitor.
iC iD2 iD1 iD2 0
so
Driver
C
dv
iC C o iD2
dt
iD1
*
We select point S’ to be the point where the output
voltage has risen halfway from its low value VOL to
its
peak value VOH.
1
1




v
S
'

V

V

3
.
8
V

0
.
05
V

1
.
93
V
o
OL
OH
2
2
*
We define the low to high propagation time tPLH as the
time it takes for the output to go from vo = vo(T’) = VOL
to vo=vo(S’) = 1/2(VOH +VOL).

v
v(
S
')
v
(
T
') C
1

o

i

C o
Co
 
V

V
V
C
OL
OH
OL


t
tPLH tPLH
2


Load
iDS2
T’
0.08
vGS2 = vDS2 =
VDD-VOL = 4.95V
0.06
0.04
C
1

 
V

V

0
OH
OL

tPLH
2


S’
0.02
vGS2 = vDS2 = VDD-VOH = 1.2V
R’
ECES 352 Winter 2007
C
1
1

 C






t

V

V

V

V

0
PLH
OH
OL
OH
OL




vDS2
i
2
i
2




C
D
2
Ch 10 MOS Digital
19
Approximate Analysis of Propagation Delays
*
Load
iD2
*
iC
Driver
C
iDS2
At point T’, vGS2 = VDD -VOL=5.0V - 0.05V = 4.95V
and the load is in saturation so
A
2
2

6




i
(
T
'
)

K
v

V

6
.
2
x
10
4
.
95
V

1
.
2
V
D
2
2
GS
2
Th
2
2
V

5

8
.
7
x
10
A

0
.
087
mA
*
At point S’,
1
1






v

v
S
'

V

V

3
.
8
V

0
.
05
V

1
.
93
V
o
o
OL
OH
2
2


so
v

v

V

v
S
'

5
V

1
.
93
V

3
.
07
V
GS
2
DS
2
DD
o
T’
0.08
1

i

i
(
T
')

i
(
S
')
D
2
D
2
D
2
2
*
iD1
Load
Output goes from Low (VOL = 0.05V) to
High (VOH = 3.8V).
Average current for the load transistor.
vGS2 = vDS2 = VDD-VOL = 4.95V
* So drain current at point S’ is given by
A
2
2

6




i
(
S
'
)

K
v

V

6
.
2
x
10
3
.
07
V

1
.
2
V
D
2
2
GS
2
Th
2
2
V
0.06
0.04
S’

5

2
.
2
x
10
A

0
.
022
mA
vGS2 = vDS2 = 3.07V
*
0.02
vGS2 = vDS2 = VDD-VOH = 1.2V
R’
ECES 352 Winter 2007
vDS2
So average
1drain current for the load is

i

i
(
T
')

i
(
S
')
D
2
D
2
D
2
2
1
0
.
087
mA

0
.
022
mA

0
.
055
mA
2

Ch 10 MOS Digital

20
Approximate Analysis of Propagation Delays
*
*
Load
iD2
dv
iCC o iD2
dt
iC
Driver
*
Defining the low to high propagation time tPLH
as the time it takes for the output to go from
vo = VOL = 0.05V to vo = 1/2(VOH +VOL) = 1.93V.
C
1



t
 
V

V
PLH
OH
OL

i
2


D
2
*
For a capacitance load of 10 pF, we get
C
1
pF
1

 10






t

V

V

3
.
8
V

0
.
05
V
PLH
OH
OL



i
2
.
055
mA
2

0


D
2

6

3
.
4
x
10
sec

340
n
sec
*
This propagation delay is very large since the
load’s current is much smaller than the driver’s
current (since K2 << K1).
The load transistor in this case is causing an
excessive delay in the transition from low to high
output by supplying only a very small current to
charge up the capacitance load.
 Also, as the output voltage rises, vgs2
decreases so the load transistor supplies less
and less current to charge up the capacitor.
C
iD1
Load
iDS2
Output goes from Low to High.
Use the average current for the load transistor
to calculate the charging time.
T’
0.08
vGS2 = vDS2
= VDD-VOL = 4.95V
0.06
vGS1 = 3.8 V
0.04
S’
0.02
vGS2 = vDS2 = VDD-VOH = 1.2V
R’
ECES 352 Winter 2007
vDS2
*
Ch 10 MOS Digital
21
Average Propagation Delay for NMOS Inverter
*
Load
iD2
iC
*
Driver
C
iD1
*
Driver
Output goes from High (VOH = 3.8V) to Low (VOL = 0.05V)
 Driver on, providing discharge current (iD1 = 2.3 mA)
 Load on, (iD2 = 0.011 mA) delaying output fall
 Propagation delay tPHL=0.8 nsec.
Output goes from Low (VOL = 0.05V) to High (VOH = 3.8V).
 Driver off (iD1 = 0).
 Load providing charging current (iD2 = 0.055 mA)
 Propagation delay tPLH = 340 nsec.
Inverter’s average propagation delay is tp
0
.
8
nsec

340
nse
t

t
PHL
PLH
t



17
ns
p
2
2
Load
iDS1
iDS2
T’
0.08
vGS2 = vDS2 = VDD-VOL = 4.95V
R
S
0.06
vGS1 = 3.8 V
S’
0.04
vGS2 = vDS2 = 3.07V
0.02
T
P
vo =VOH = 3.8 V
ECES 352 Winter 2007
vDS1
vGS2 = vDS2 = VDD-VOH = 1.2V
R’
Ch 10 MOS Digital
22
vDS2
Static Power Dissipation for NMOS Inverter
*
Load
iD2
iC
Driver
*
C
*
*
iD1
Driver
Output High (VOH = 3.8 V)
 Driver off (iD1=0), Load on, but iD2= iD1 = 0.
 No power dissipation in static high output mode (PH=0).
Output Low (VOL = 0.05 V).
 Driver on and operating at point T (vo = 0.05 V).
 Load on and operating at point T’ where iD2(T’) = 0.087 mA.
 Power dissipation PL = iD2(T’)VDD = (0.087 mA) 5 V = 0.42 mW.
Inverter’s average power dissipation is PD= 1/2(PL+PH) = 0.21 mW.
Power delay product DP
DP = PD tp
-11
= 0.21 mW (170 nsec) = 3.6x10 J = 36 pJ.
Load
iDS1
iDS2
T’
0.08
vGS2 = vDS2 = VDD-VOL = 4.95V
R
S
0.06
vGS1 = 3.8 V
S’
0.04
0.02
T
P
vo =VOH = 3.8 V
ECES 352 Winter 2007
vDS1
vGS2 = vDS2 = 3.07V
vGS2 = vDS2 = VDD-VOH = 1.2V
vDS2
R’
Ch 10 MOS Digital
23
Comparison of NMOS Inverters
* Noise Margins
 NML = 0.05 V, NMH = 3.17 V
* Propagation Delay


* Noise Margins
NML = 0.95 V, NMH = 2.27 V
* Propagation Delay


1
1
1
1




t

t

t

4
.
5
n
sec

14
n
sec

10
n
sec
t

t

t

0
.
8
n
sec

340
n
sec

17
n
s
PD
PHL
PLH
PD
PHL
PLH
2
2
2
2
* Power Dissipation
* Power Dissipation
* Power-Delay Product
* Power-Delay Product
(
0

10
mW
)
(
0

0
.
42
mW
)
1
1




P

P

P


5
mW
P

P

P


0
.
21
mW
HL
H
L
2
2
2
2
DP

P
t

5
mW
(
10
n
sec)

50
pJ
PD
ECES 352 Winter 2007
DP

P
t

0
.
21
mW
(
170
n
sec

36
p
PD
Ch 10 MOS Digital
24
How to Improve the NMOS Inverter?
* How to reduce the tPLH ?
* Increase the load current by
increasing the load’s W/L ratio.
2
2




i

K
v

V

K
V

v

V
D
2
2
GS
2
Th
2
2
DD
o
Th
2
W
1

m
, L
10

m
2
2
W
1

6A
2

K
6
.2
x
10
2
2
L
V
2 10
* However, that increases the fall time
* Noise Margins
tPHL since the load provides current
NML = 0.95 V, NMH = 2.27 V
that the driver must absorb to
* Propagation Delay
discharge the capacitor. The net effect
1
1
may be some improvement in the tPD.



t
t
t

0
.
8
n
sec

340
n
sec

170
n
sec
PD
PHL
PLH
2
2
* However, there will be an increase
in the power dissipation.
(
0

0
.
42
mW
)
* Power Dissipation
1


P

P

P


0
.
21
mW
H
L
2
2
* Power-Delay Product
* Also, the noise margin for the high
state will be degraded.
DP

P
t

0
.
21
mW
(
170
n
sec)

36
pJ
PD
ECES 352 Winter 2007
Ch 10 MOS Digital
25
A Modified NMOS Inverter
* Increase the load’s W/L ratio from
1/10 to 2 (20 X increase in K2 ).

1 W
A 
A
6
4
K

C

6
.
2
x
10

1
.
2
x
10
2
n
ox
2
2
2 L
V
V
2
2




i

K
v

V

K
V

v

V
D
2
2
GS
2
Th
2
2
DD
o
Th
2
* New tPLH is 17 nsec vs previous 340 nsec.
* New tPHL is 9 nsec vs previous 0.8 nsec.
* New tPD is 13 nsec vs previous 170 nsec.
* Noise Margins
NML = 0.95 V, NMH = 2.27 V
* Propagation Delay
* New power dissipation is 8.4 mW vs
previous 0.21 mW.
* New power-delay product is 109 pJ vs
1
1
previous 36 pJ.



t
t
t

0
.
8
n
sec

340
n
sec

170
n
sec
PD
PHL
PLH
2
2
* New VIH = 3.64 V vs previous 1.53 V.
* New noise margin for the high state
(
0

0
.
42
mW
)
1


P

P

P


0
.
21
mW
H
L
NMH = 3.8 - 3.64 = 0.16 V vs
2
2
previous 2.27 V.
* Power-Delay Product
* Power Dissipation
DP

P
t

0
.
21
mW
(
170
n
sec)

36
pJ
PD
ECES 352 Winter 2007
Ch 10 MOS Digital
26