Download Digital CMOS

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Digital IC Technologies
CMOS & Pass Transistor Logic dominate
Figure 10.1 Digital IC technologies and logic-circuit families.
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Why CMOS
•
•
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Advantages
• Virtually, no DC power consumed
• No DC path between power and ground
• Excellent noise margins (VOL=0, VOH=VDD)
• Inverter has sharp transfer curve
Drawbacks
• Requires more transistors
• Process is more complicated
• pMOS size larger to achieve electrical symmetry
Digital cmos.3
Digital CMOS Inverter
Figure 4.53 The CMOS inverter.
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CMOS Inverter
Operation;
Vin = Hi
Hi
Lo
Equivalent
circuit
Figure 4.54 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD
(logic-1 level, or VOH); (b) graphical construction to determine the operating point; (c)
equivalent circuit.
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CMOS Inverter Operation;
Vin = Lo
Lo
Hi
Figure 4.55 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0
level, or VOL); (b) graphical construction to determine the operating point; (c) equivalent circuit.
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CMOS Inverter
Transfer characteristic
VIL= highest input voltage still
interpreted as an input low (resulting
in out = Hi)
VIH= lowest input voltage still
interpreted as an input Hi (resulting
in out = lo)
NMH
= VOH – VIH
NML
= VIL - VOL
Figure 4.56 The voltage transfer characteristic of the CMOS inverter.
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CMOS Logic gates ?
Pullup(s) &
pulldown(s)
Figure 10.8 Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN
comprises NMOS transistors.
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CMOS Logic gate pulldown
Examples
Figure 10.9 Examples of pull-down networks.
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CMOS Logic gate pullup
Examples
Figure 10.10 Examples of pull-up networks.
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CMOS Transistor Symbols
Figure 10.11 Usual and alternative circuit symbols for MOSFETs.
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CMOS Logic gate
Example 1 ?
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CMOS Logic gate
Example 2 ?
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CMOS Logic gate
Example 3
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CMOS Logic gate
Example 4
Y=?
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CMOS Inverter Representation
Can be represented as
Simple switch
Figure 10.4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary
fashion.
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CMOS Inverter
Dynamic
Operation
Input
Output
Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input
and output waveforms; (c) trajectory of the operating point as the input goes high and C
discharges
through QN; (d) equivalent circuit during the capacitor discharge.
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CMOS Inverter
Current VS voltage
Figure 4.58 The current in the CMOS inverter versus the input voltage.
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CMOS Inverter - Propagation delays
tPHL = Hi to lo
tPLH = lo to Hi
Input
tr = rise time
tf = fall time
Output
Figure 10.3 Definitions of propagation delays and switching times of the logic inverter.
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CMOS Inverter
Source of prop. delays
Figure 10.6 Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving an
identical inverter formed by Q3 and Q4.
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CMOS Inverter
tPHL
Hi to Lo
prop. Delay analysis
tPLH
Lo to Hi
Figure 10.7 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter.
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Music for your ears
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Musique 101
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Pass Transistor Logic
PTL
Figure 10.23 Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C,
when connected in series in the path between the input node to which an input variable A is applied and the output
node (with an implied load to ground) realize the function Y = ABC. (b) When the two switches are connected in
parallel, the function realized is Y = A(B + C).
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PTL
Switch
NMOS switch
CMOS switch
Aka transmission gate
Figure 10.24 Two possible implementations of a voltage-controlled switch connecting nodes A and Y: (a) single
NMOS transistor and (b) CMOS transmission gate.
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PTL – Need path to ground
Or VDD
For proper logic voltage levels
Figure 10.25 A basic design requirement of PTL circuits is that every node have, at all times, a low-resistance
path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided in (b)
through switch S2.
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PTL
Switch closed
Figure 10.26 Operation of the NMOS transistor as a switch in the implementation of PTL circuits. This analysis is for
the case with the switch closed (vC is high) and the input going high (vI = VDD).
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PTL
Switch Open
Figure 10.27 Operation of the NMOS switch as the input goes low (vI = 0 V). Note that the drain of an NMOS
transistor is always higher in voltage than the source; correspondingly, the drain and source terminals interchange roles
comparison to the circuit in Fig. 10.26.
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Transmission gate in action
Figure 10.29 Operation of the transmission gate as a switch in PTL circuits with (a) vI high and (b) vI low.
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Transmission gate in action
Multiplexer ?
Figure 10.30 Realization of a ……??????………….multiplexer using pass-transistor logic.
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Transmission gate in action
Gate ?
Figure 10.31 Realization of the ……. function using pass-transistor logic.
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Transmission gate in action
Gate ?
Figure 10.32 An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore
known as complementary pass-transistor logic or CPL. Note that both the output function and its complement are generated.
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Transmission gate (NMOS) drops Vt
Across switch
PMOS pullup can be used to restore V
Figure 10.28 The use of transistor QR, connected in a feedback loop around the CMOS inverter, to restore the VOH
level, produced by Q1, to VDD.
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Barrel Shifter, used in ICs
Shift ……???…. using one transistor per switch
SR3
SR2
SR1
SR0
D3
D2
A6
D1
A5
D0
A4
A3
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A2
A1
A0
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Barrel Shifter, used in ICs
Shift ……???…. using one transistor per switch
SR3
SR2
SR1
SR0
D3
D2
A6
D1
A5
D0
A4
A3
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A2
A1
A0
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Barrel Shifter, used in ICs
Shift ……Left ???…. Exercise
SR3
SR2
SR1
SR0
SL ?
D3
SL ?
D2
A6
D1
A5
D0
A4
A3
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A2
A1
A0
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Barrel Shifter, used in ICs
Shift ……Left ???…. Exercise
SR2
SR1
SR0
SL ?
D3
SL ?
SL?
D2
A5
D1
A4
D0
A3
A2
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A1
A0
Digital cmos.37
How many transistors in
each gate implementation ?
Figure P10.36
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Other Inverter Implementations
All NMOS - Not very popular -- FYI
(a) pseudo-NMOS logic inverter.
(b) The enhancement-load
NMOS inverter.
© The depletion-load NMOS
inverter.
Figure 10.19 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load NMOS inverter. (c) The depletion-load
NMOS inverter.
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Pspice Simulation example …. later
Figure 10.38 Capture schematic of the CMOS inverter in Example 10.5.
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CMOS Inverter Netlist
generating inverter transfer curve
* here's the inverter netlist declaration
* mosfet: mxx drain gate source substrate model length width
m1 OUT IN VDD VDD CMOSP l=.5u w=2u
m2 OUT IN GND GND CMOSN l=.5u w=2u
* constant voltage source: vxx node1 node2 voltage
VDD VDD GND 5
* Define a voltage source connected to Vin and initialize voltage to 0
Vin IN Gnd 0
* Sweep Vin from 0 to 5 volts in increments of .1 volt
.DC Vin 0 5 .1
* Print the voltage at OUT
.print dc v(OUT)
.end
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