Survey
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
[email protected] TWEPP-2009, Paris, September 2009 Ultra Thin, Fully Depleted MAPS based on 3D Integration of Heterogeneous CMOS Layers Wojciech Dulinski on behalf of: IPHC Strasbourg-IRFU Saclay-University of Pavia-University of Bergamo Collaboration On the way towards fast, high precision, radiation tolerant and ultra thin CMOS sensors, we propose MAPS on fully depleted epitaxial substrate with first stage buffer amplifier on the same wafer, capacitively coupled to the 3D readout electronics implemented on top of each pixel. Fast: frame readout time <<10µs and/or time resolution of ~100 ns High precision: pixel pitch <20 µm, spatial resolution ~2µm Radiation tolerant: > 1014 n/cm2 Ultra thin: ~50 µm (Si equivalent) 1 [email protected] TWEPP-2009, Paris, September 2009 Recipe for our first, on-going exercise: use Tezzaron/Chartered 0.13 µm 2-tiers process available through the HEP-3D Consortium (Fermilab, IN2P3, INFN…) plus XFAB PIN (high-resistive epi) process Bonding pads Bumps TSV From Chartered (2 tiers) plus XFAB and Ziptronix (3 tiers) Wafer view at intermediate and after final stage (chip-to-XFAB wafer bonding) 2 [email protected] TWEPP-2009, Paris, September 2009 Existing “3D integration” technology: hybrid sensors Bump-bonding (indium or solder bumps): minimum pitch ~few tens of microns, limited to integration of two layers, not really industrial (large volume) process Example: ATLAS pixel sensors 3 [email protected] TWEPP-2009, Paris, September 2009 On-going evolution and improvement of bump-bonding: example of micro-bonding from IMEC (credit to Piet De Moor) ZyCube Co. Ltd. (Japan): 5 µm pitch Major disadvantage of bump-bonding persists, plus a new complication (intermetallic compounds formation: variable reliability) 4 [email protected] TWEPP-2009, Paris, September 2009 Our choice: industrial (or close to) 3-D integration process, with a standard use of TSV (through-silicon-vias) and direct metal-metal thermo compression bonding Example from Tezzaron*: two or more stacked wafers (tiers). Typical interconnection pitch < 5 µm, typical TSV Cp < 5 fF, typical TSV Rs < 0.5 Ω, typical interconnecting metal fill factor ~30%. * B.Patti, Proc.IEEE Vol.94, No. 6, June 2006 5 [email protected] TWEPP-2009, Paris, September 2009 3-D integration technology is offered by Tezzaron/Chartered as a standard technology (similar constrains as for VLSI submission), but limited (at least for us as a small user) to one CMOS process (0.13 microns) To bond our wafers from another CMOS supplier (XFAB OPTO PIN, well suited for the sensor layer) we plan to use another 3D-integration semi-industrial process: DBI® (Direct Bond Interconnect) from Ziptronix 6 [email protected] TWEPP-2009, Paris, September 2009 DBI® (Direct Bond Interconnect): Low Temperature CMOS Compatible Direct Oxide Bonding For Highest Density 3D Interconnection (<1 µm pitch possible) - very low mass (>95% of bond is silicon oxide) - mechanically stronger than silicon allowing bonding of thinnest possible CMOS layer (~10 microns) - directly compatible with any modern CMOS BEOL process having W-plugs and CMP planarization steps (but also compatible with Copper Interconnect) Example of 3 µm diameter DBI® ( metal plug via through the oxide) * P. Enquist, Proc. FEE-2009) 7 [email protected] TWEPP-2009, Paris, September 2009 DBI® Process flow (from Paul Enquist talk at FEE-2009) 8 [email protected] TWEPP-2009, Paris, September 2009 Second stage: thinning to <50 µm Bonding pads XFAB and 2xChartered (3 tiers, first stage) Problem: how to handle, interconnect and at the end built a ladder with such a thin device? 9 [email protected] TWEPP-2009, Paris, September 2009 Possible solution: embedding in thin flexible substrate (BCB, silicone, polyamide). Interconnect at bondpad level using electroplated Cu. No wire bonding! Fully functional microprocessor chip in flexible plastic envelope. *Curtsey of Piet De Moor, IMEC, Belgium 10 [email protected] TWEPP-2009, Paris, September 2009 Embedding in flexible substrate process developed end proposed by IMEC. For later this year, we are planning the first exercise using standard, analog readout MAPS (Mimosa18) thinned down to <30 µm, embedded in plastic and interconnected to PCB using flex cable. The goal is to study performance of a “flexible” sensor… Possible solution for a cylindrical vertex detector layer? Piet De Moor, FEE-2009 Proceedings 11 [email protected] TWEPP-2009, Paris, September 2009 1. Self Triggering Pixel Strip-like Tracker (STriPSeT) Collaboration: Strasbourg-Bergamo-Pavia If >1 nA G x1 Cf Cc >100 fF ~10 fF soff <10 mV Dff ~ 40 µm2 Low offset, continuous discriminator Readout logic Cd ~ 10 fF Qmin ~ 200 el Shaperless front-end tpeak ~1µs XFAB 0.6µm PIN (Tier_0) Chartered Tier_1 (analog) and Ziptronix Tier_2 (digital) Tezzaron (Direct Bond Interconnect, DBI®) (metal-metal (Cu) thermo compression) 12 [email protected] TWEPP-2009, Paris, September 2009 Principal arguments for use of XFAB-0.6 PIN - “fully” depleted, 14 µm thick epitaxy - for small pitch, charge fully contained in less than four pixels - fast charge collection (~5ns) should be radiation tolerant - sufficient (rather good) S/N ratio defined by the first stage - “charge amplification” ( >x10) by capacitive coupling to the second stage - first experimental results from our first pixel sensor in this process (Mimosa25) very promising! 20x20 µm pixel layout in XFAB-06. Version: SF+CAPA (150 fF) 13 [email protected] TWEPP-2009, Paris, September 2009 TCAD simulation of a MAPS on high resistivity (1 kΩ cm) epi For comparison: standard CMOS technology, low resistivity P-epi high resistivity P-epi: size of depletion zone size is comparable to the P-epi thickness! 14 [email protected] TWEPP-2009, Paris, September 2009 Mimosa-25 prototypes (XFAB-0.6 PIN, Aug-Dec 2008) 20um 4x4 STD 30um 11.4x11.4 PIN 20um 4x4 um STD_TOX 40um 11.4x11.4 um PIN 20um 5x6.5 SB 30um 5x6.5 SB 20um 5x6.5 um SB_TOX 40um 11.4x11.4um STD 20um 5x6.5 STD 30um 4x4 STD 20um 5x6.5 um STD_TOX 40um 5x6.5 um STD Mimosa 25 A Mimosa 25 B 2 submitted chips 15 [email protected] TWEPP-2009, Paris, September 2009 Mimosa-25 on fully depleted epi substrate (XFAB): first tests results (Ru beta) 20 µm pitch, self-bias [email protected] before and after neutron irradiation Landau MP charge of the cluster versus cluster size before and after neutron irradiation To compare: « standard » (non-depleted epi substrate) before and after ~6*1012 n/cm2 16 [email protected] TWEPP-2009, Paris, September 2009 Mimosa-25 on fully depleted epi substrate : Ru beta spectrum (MIP Landau) seen at the seed pixel, 20 µm pitch, self-bias [email protected] Supposed threshold for ~100% efficiency: ~150 electrons very recently confirmed by our beam tests! 17 [email protected] TWEPP-2009, Paris, September 2009 Principal arguments for “shaperless front-end” (single stage, high gain, folded cascode based charge amplifier, with a current source in the feedback loop) - simple (surface efficient) but very satisfactory approach, in particular when minimum signal charge is of few thousand electrons (after “charge amplification”) - shaping time of ~1 µs very convenient: good time resolution, insensitivity to the irradiation induced leakage current - possible implementation of Time-over-Threshold ADC in the future… - minimum signal at the entrance of comparator few tens of mV, so threshold dispersions of few mV tolerable - structure already studied in details by Pavia&Bergamo group (expertise from several prototypes in another 0.13 µm process): minimum risk for this first 3D-3T exercise! 18 [email protected] TWEPP-2009, Paris, September 2009 Combined simulation XFAB+Charterer (SF+ShaperlessFE) Two versions of SFE: Cf=11 fF (MiM) and 5.5 fF (VPP) Simulation: pulse corresponding to 200 el injected into XFAB diode Results: Peaking time ~400 ns Gain: ~150µV/el (300 µV/el) ENC ~10 electrons! Extra power from SF: <1µW/pixel IF this is correct, we should expect: S/NLandau>40 and Cut~100%eff/Noise>10 19 [email protected] TWEPP-2009, Paris, September 2009 Combined simulation XFAB+Charterer (SF+ShaperlessFE) Linearity: 100-4000 electrons (step 100 e) 20 [email protected] TWEPP-2009, Paris, September 2009 Combined simulation XFAB+Charterer (SF+ShaperlessFE) Comparator output : 100-4000 electrons (step 100 e); threshold ~150 e 21 [email protected] TWEPP-2009, Paris, September 2009 Combined simulation XFAB+Charterer (SF+ShaperlessFE) Time-walk of the comparator output : 100-4000 electrons (step 100 e); thr. ~150 e 22 [email protected] TWEPP-2009, Paris, September 2009 Self Triggering Pixel Strip-like Tracker: analog pixel (SFE) layout SuperVias (Input and GND) Input 23 [email protected] TWEPP-2009, Paris, September 2009 Principal arguments for “only digital” Tier_2 - excellent separation of analog and digital (no common substrate, several metal layers for blinding…): no problems for asynchronous, random logic - flexibility of the readout architecture, possible use of “front-line”, pure digital CMOS process (<60nm) for this layer to increase complexity of processing at lower power budget 24 [email protected] TWEPP-2009, Paris, September 2009 STriPSeT: Data driven (self-triggering), sparsified binary readout. X and Y projection of hit pixels pattern SR TrigOut Example: DELAY SR: hot pixel disable register TrigIn readout clock : 160 MHz 2 output lines ≡ Array readout SR Readout or Reset time: ~2µs Programmable Active Area (through pixel disable SR) Readout compatible with existing IPHC-digital DAQ… 25 [email protected] TWEPP-2009, Paris, September 2009 2. Rolling Shutter Mode MAPS: power efficient solution based on M26 approach for processing. Collaboration: IRFU (Saclay) –IPHC (Strasbourg) In-pixel electronics - Common threshold voltage - Only NMOS transistors in Tier 1 - 20x20 µm pitch, 32x256 pixel array - Low power operation (rolling shutter) Example of a power budget: -100 µW/pixel for 50ns processing -To be compared with 500µW/pixel for 200 ns processing (Mimosa26) -Factor of 20 saving in analog power! This is due to 3D electronics… 26 [email protected] TWEPP-2009, Paris, September 2009 3-Tiers CMOS MAPS status and expected (revised) schedule (May today) Submission (Chartered): ~April (done) mask generation at Chartered just now (?) - Submission (XFAB): ~June/July (building blocks ready) changing to XFAB 035 PIN process, expected submission before end 2009 - - Reception of wafers: ~ September December/January 2009 - 2 Tiers testing: ~September from January 2100 on XFAB Tier bonding (at Ziptronix): October revision of technology compatibility - Final tests (including beam tests): before the end of 2009? second half 2010? Next steps: 1. 2. Power optimization. Power dissipation is a major issue in case of very thin detectors! In addition to STRipSeT and RSPix, a novel, high-gain (1-2 mV/el), low power (<1µW/pixel) test structure has been submitted Thinning down to ~50 µm. Having such thin wafer, we may propose a new approach to solve yield problems in case of large area devices: built-in redundancy (2complete layers) plus powering off of selected areas after in-situ self-tests 27