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CS/EE 3700 : Fundamentals of
Digital System Design
Chris J. Myers
Lecture 11: Testing of Logic Circuits
Chapter 11
Testing of Logic Circuits
• Must test a circuit to check that it meets
required functional and timing specification.
• Manufacturing process can introduce flaws.
• Testing applies a set of inputs, called tests,
and compare with expected outputs.
• Challenge is to derive a small set of tests.
• Exhaustive approach is impractical.
Faults
• Many things can go wrong:
–
–
–
–
–
Transistor may be stuck open or closed.
Wire can be shorted to Vdd or Gnd.
Wire may simply be broken.
Two wires may get shorted together.
Logic gate may produce the wrong output.
Stuck-At Model
• Stuck-at model assumes a fault manifests as
some wire stuck at a logic value of 0 or 1.
• If w is stuck-at-0, it is denoted w/0.
• If w is stuck-at-1, it is denoted w/1.
• While this model does not work for all
types of faults, works reasonably well.
Single and Multiple Faults
• Dealing with multiple faults is difficult.
• Considering single faults only still detects
majority of multiple faults.
• Fault detected when output value of faulty
circuit differs from good circuit for a test.
• Complete set of test is called a test set.
CMOS Circuits
• Transistors may be permanently open or
shorted (closed).
• May or may not appear as a stuck-at fault.
• May also cause permanent path between
Vdd and Gnd giving intermediate voltage.
• May also lead to combinational circuit to
behave like a sequential one.
• Will restrict ourselves to stuck-at model.
Complexity of a Test Set
• Sequential circuits substantially more
complex to test than combinational ones.
• In combinational case, we can apply all
possible input valuations and check outputs.
• This approach is impractical and
unnecessary for large circuits.
a
w1
f
b
w2
w3
d
c
(a) Circuit
Test
w1 w2 w 3
Fault detected
a/0
a/1
000

001

010

b/0
c/0
c/1
d/0



011
b/1

d/1
f /0








100


101


110



111
(b) Faults detected by the various input valuations
Figure 11.1
f /1
Fault detection in a simple circuit
w1
a
b
w2 = 1
c
w3 = 0
w4 = 1
Figure 11.2
A sensitized path
f
w1
c
w2
b
d
w3
w4
Figure 11.3
Circuit for Example 11.1
f
w4
w3
w2
w1
w4
w3
w2
w1
w4
w3
w2
w1
c
b
Figure 11.4
Detection of faults
(c) Detection of g  1 fault
(b) Detection of b  0 fault
(a) Circuit
g
k
h
f
f
f
w1
w3
w4
w2
w3
f
w4
w1
w2
w3
Figure 11.5
Circuit with a tree structure
Product term
Test
No.
w1 w3 w4
w2 w 3 w4
w 1 w2 w3
w1 w2 w3 w4
1
1 1 1
0 1 0
0 0 0
1 0 0 0
2
0 1 0
1 1 1
1 1 0
0 1 0 1
3
0 0 0
1 0 1
1 1 1
0 1 1 1
4
0 1 1
1 1 0
1 1 0
0 1 0 0
5
1 0 1
1 0 0
0 1 1
1 1 1 0
6
1 1 0
0 1 1
0 0 0
1 0 0 1
7
1 0 0
1 0 1
0 1 1
1 1 1 1
8
0 0 0
0 0 1
1 0 1
0 0 1 1
Stuck-at-0
tests
Stuck-at-1
tests
Figure 11.6
Derivation of tests for the circuit in Figure 11.5
f 11
f 12
f 13
f 14
f 15
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
w1 w2
f0
f 1 f 2 f 3 f 4 f 5 f 6 f 7 f 8 f 9 f 10
00
0
0
0
0
0
0
0
0
1
1
01
0
0
0
0
1
1
1
1
0
10
0
0
1
1
0
0
1
1
11
0
1
0
1
0
1
0
1
Figure 11.7
All two-variable functions
h
w1
w2
b
d
f
c
k
Figure 11.8
The XOR circuit
Fault
Circuit implements
b/0
f 5 = w2
b/1
f 10 = w 2
c/0
f 3 = w1
c/1
f 12 = w 1
d/0
f0 = 0
d/1
f 7 = w1 + w2
h/0
f 15 = 1
h/1
f 4 = w 1 w2
k/0
f 15 = 1
k/1
f 2 = w1 w 2
Figure 11.9
The effect of various faults
Percent
faults
detected
Number of tests
Figure 11.10
Effectiveness of random testing
Testing Sequential Circuits
• Response of sequential circuit is dependent
on both current input and present state.
• Could check all state transitions.
• Cannot determine state, not observable.
• Circuits must be designed to be testable.
wn
w1
y1
y2
y3
Figure 11.11
D
D
D
Clock
0
1
0
1
0
1
Scan-in
Y1
Y2
Y3
Scan-path arrangement
Q
Q
Q
Scan-out
Combinational
circuit
zk
z1
Normal Scan
w
Q
Q
Q
Figure 11.12
Resetn
y1
y2
Q
Clock
0
1
0
1
Normal/Scan
Scan-in
Circuit for Example 11.3
D
D
Scan-out
z
Y2
Y1
p
x0
Test
vector
generator
0
Circuit
under
test
x
n–1
Test
result
compressor
p
m– 1
Signature
Figure 11.13
The testing arrangement
f
D
Q
Q
D
Q
D
Q
Q
Q
D
Q
Q
Clock
x2
x3
x1
x0
PRBS
(a) Circuit
x3
1
1
1
1
0
1
0
1
1
0
0
1
0
0
0
1
···
x2
0
1
1
1
1
0
1
0
1
1
0
0
1
0
0
0
···
x1
0
0
1
1
1
1
0
1
0
1
1
0
0
1
0
0
···
x0
0
0
0
1
1
1
1
0
1
0
1
1
0
0
1
0
···
f
1
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
···
(b) Generated sequence
Figure 11.14
Pseudorandom binary sequence generator (PSRG)
Signature
D
p
Q
Q
D
Q
Q
D
Q
Q
Clock
Figure 11.15
Single-input compressor circuit
D
Q
Q
Signature
D
Q
D
Q
Q
D
Q
Q
D
Q
Q
Clock
p
3
p
Figure 11.16
2
p
1
Q
p
0
Multiple-input compressor circuit (MIC)
Z-signature
Normal Test
W
0
X
1
MIC
Z
y
Combinational
circuit
Y
PRBSG-X
Scan-out
Flip-flops
and
multiplexers
Scan-in
PRBSG-y
Figure 11.17
BIST in a sequential circuit
SIC
Y-signature
q3
q2
q1
q0
Clock
G S
Si n
Q
1
0
Q
D Q
Q
D Q
Q
D Q
D Q
M2
M1
p3
p2
p1
p0
Figure 11.18 A four-bit built-in logic block observer (BILBO)
Sout
Combinational
network
CN1
BILBO2
BILBO1
Scan-out
Combinational
network
CN2
Scan-in
Figure 11.19
Using BILBO circuits for testing
Boundary Scan
• Chips soldered into printed circuit boards
do not allow easy access it inputs/outputs.
• Pins can be configured into a shift register
to allow inputs and outputs to be scanned in.
• Now IEEE Standard 1149.1.
Printed Circuit Boards
• Need CAD software to design them.
• Crosstalk – capacitively coupled wires.
– Avoid long parallel wires.
• Power supply noise – power supply spikes.
– Use bypass capacitors between Vdd and Gnd.
• Transmission-line effects
– Use termination component on the line.
Testing of PCBs
• Power Up – check for hot chips and correct
power and ground voltages.
• Reset – put circuit into known start state.
• Low-level functional testing – use divideand-conquer approach.
Testing of PCBs
• Full functional testing – test system.
–
–
–
–
Manufacturing errors.
Incorrect specifications.
Misinterpretation of the data sheets.
Wrong data sheets.
• Timing – start with slow clock and gradually
increase to desired frequency.
• Reliability – affected by timing, noise, crosstalk
issues, and environment.
Instrumentation
• Oscilloscope – displays voltage waveforms
to show problems with delay and noise.
• Logic analyzer – allows examination of
large groups of signals.
Where to go from here . . .
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CS/EE 3710 – Computer Design Laboratory
CS/EE 3720 – Analog and Digital Interfacing
CS/EE 3810 – Computer Architecture
CS/EE 4710 – Senior Project
CS/EE 5710 – Digital IC Design
CS/EE 5720 – Analog IC Design
CS/EE 5740 – CAD for Digital Circuits
CS/EE 5750 – Asynchronous Circuit Design
CS/EE 5810 – Advanced Computer Architecture
CS/EE 5830 – VLSI Architecture
New to the CE Program
• Tracks are no longer required.
– Still must take 15 credits of CS/EE classes.
• New senior thesis option:
– Must take EE 3900 Junior seminar in Fall
and prethesis in Spring (0.5 credits each).
– Senior year must take one year of senior thesis for a
total of 4 credits.
– Do not need to take CS/EE 4710.
– Can lead into a joint BS/EE degree.