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Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Coping with Interconnect Revised from Digital Integrated Circuits, © Jan M. Rabaey © Digital Integrated Circuits2nd Interconnect Impact of Interconnect Parasitics • Reduce Robustness • Affect Performance • Increase delay • Increase power dissipation Classes of Parasitics • Capacitive • Resistive • Inductive © Digital Integrated Circuits2nd Interconnect INTERCONNECT © Digital Integrated Circuits2nd Interconnect Capacitive Cross Talk X CXY VX Y CY © Digital Integrated Circuits2nd Interconnect Capacitive Cross Talk Dynamic Node A non-related signal Y is routed in Metal 1 wire over the polysilicon gate of the inverter gate. V DD CLK CXY Y In 1 In 2 In 3 Assume that CY=6fF and CXY= (3*1*0.057+ CY PDN CLK 3 x 1 mm overlap: 0.19 V disturbance © Digital Integrated Circuits2nd X 2.5 V 2*3*0.054)=0.5fF Combined with charge 0V redistribution and clockfeed through effects, this might cause circuit failure. Interconnect Wiring Capacitances (0.25mm CMOS) Rows represent the top plate, columns the bottom plate. Shaded row for fringing capacitance in aF/µm, unshaded for parallel plate capacitance (area capacitance) in aF/µm^2 40 95 85 85 85 115 © Digital Integrated Circuits2nd smaller Interconnect Capacitive Cross Talk: Driven Node 0.5 0.45 0.4 X VX RY CXY 0.3 Y CY tr↑ 0.35 tXY = RY(CXY+CY) 0.25 0.2 0.15 V (Volt) 0.1 0.05 0 0 0.2 0.4 0.6 0.8 1 t (nsec) If the rise time is comparable or larger than the time constant, the peak value of disturbance is diminished. So we need to Keep time-constant smaller than rise time, that is to decrease either capacitance or resistance (keeper transistor in dynamic design). © Digital Integrated Circuits2nd Interconnect Dealing with Capacitive Cross Talk Avoid floating nodes Protect sensitive nodes Make rise and fall times as large as possible (*?) Do not run wires together for a long distance Use shielding wires Use shielding layers © Digital Integrated Circuits2nd Interconnect Shielding Shielding wire GND V DD Shielding layer GND Substrate (GND ) Interleave every signal layer with a GND or VDD metal plane © Digital Integrated Circuits2nd Interconnect Cross Talk and Performance - When neighboring lines switch in opposite direction of victim line, delay increases Cc DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRES - Both terminals of capacitor are switched in opposite directions (0 Vdd, Vdd 0), Miller Effect - Effective voltage is doubled and additional charge is needed (from Q=CV) © Digital Integrated Circuits2nd Interconnect Impact of Cross Talk on Delay Activity on bus of different bits r is ratio between capacitance to neighbor and to GND © Digital Integrated Circuits2nd Interconnect Encoding Data Avoids Worst-Case In Conditions Encoder Bus Decoder Out It is possible to encode the data in such a way that the transitions that “victimize” delay are eliminated. This requires that the bus interface units include encode/decoder functions. © Digital Integrated Circuits2nd Interconnect Structured Predictable Interconnect V: VDD V S: signal S G S V S S G S V G: GND S V Example: Dense Wire Fabric ([Sunil Kathri]) Trade-off: • Cross-coupling capacitance 40x lower, 2% delay variation • Increase in area and overall capacitance Also widely used in FPGAs © Digital Integrated Circuits2nd Interconnect Interconnect Projections Low-k dielectrics Both delay and power are reduced by dropping interconnect capacitance Types of low-k materials include: inorganic (SiO2), organic (Polyimides) and aerogels (ultra low-k) The numbers below are on the conservative side of the NRTS roadmap Generation Dielectric Constant 0.25 mm 3.3 © Digital Integrated Circuits2nd 0.18 mm 2.7 0.13 mm 2.3 0.1 mm 2.0 0.07 mm 1.8 e 0.05 mm 1.5 Interconnect Driving Large Capacitances V DD V in V out CL • Transistor Sizing • Cascaded Buffers © Digital Integrated Circuits2nd Interconnect Using Cascaded Buffers In Out 1 2 0.25 mm process Cin = 2.5 fF tp0 = 30 ps N CL = 20 pF F = CL/Cin = 8000 fopt = 3.6 N=7 tp = 0.76 ns (See Chapter 5) © Digital Integrated Circuits2nd Interconnect Delay as a Function of F and N 10,000 F = 10,000 tp/tp0 1000 p t/0 tp 100 F = 1000 10 1 3 5 7 F = 100 9 11 Number of buffer stages N © Digital Integrated Circuits2nd Interconnect Output Driver Design Trade off Performance for Area and Energy Given tpmax find N and f Area Energy f 1 F 1 A 1 f f ... f A A A f 1 f 1 2 N N 1 driver min 2 Edriver 1 f f 2 ... f N 1 CiVDD min min F 1 C 2 2 CiVDD L VDD f 1 f 1 To a first order analysis, this simply says that small sizing factor f causes large area and power consumption!!! © Digital Integrated Circuits2nd Interconnect Output Driver Design: design for right speed 0.25 mm process, CL = 20 pF Transistor Sizes for optimally-sized cascaded buffer tp = 0.76 ns fopt = 3.6 Transistor Sizes of redesigned cascaded buffer tp = 1.8 ns fd = 20 Overall area of the later solution is 7 times smaller compared to the first one, while delay is increased by a factor of 2. Also, overall power dissipation of the load and buffer is reduced by 24%. © Digital Integrated Circuits2nd Interconnect How to Design Large Transistors D(rain) Multiple Contacts Reduces diffusion capacitance Reduces gate resistance S(ource) G(ate) small transistors in parallel © Digital Integrated Circuits2nd Interconnect Bonding Pad Design Bonding Pad GND 100 mm Out VDD © Digital Integrated Circuits2nd In GND Guard ring Out Interconnect Guard ring Guard rings are grounded p+ diffusions in a p-well and supply-connected n+ diffusions in an n-well that are used to collect injected minority carriers before they reach the base of the parasitic bipolar transistors. They should be used surrounding the NMOS/PMOS transistors in the final stage of the output pad driver. Used a lot in analog VLSI design. © Digital Integrated Circuits2nd Interconnect Chip Packaging Bonding wire •Bond wires (~25mm) are used to connect the package to the chip Chip L Mounting cavity L´ Lead frame Pin © Digital Integrated Circuits2nd • Pads are arranged in a frame around the chip • Pads are relatively large (~100mm in 0.25mm technology) •Many chips areas are ‘pad limited’ Interconnect Pad Frame Layout © Digital Integrated Circuits2nd Die Photo Interconnect Tristate Buffers Most of the driver circuits have been simple inverters. Tristate buffers is a variant. Suppose that one device is sending information on the bus, all other transmitting devices should be disconnected from the bus. This can be achieved by putting the output buffers of those devices in an high-impedance state Z that effectively disconnects the gate from the output wire. © Digital Integrated Circuits2nd Interconnect Tristate Buffers V DD V DD En En Out Out In En In En Increased output drive Out = In.En + Z.En © Digital Integrated Circuits2nd Interconnect INTERCONNECT © Digital Integrated Circuits2nd Interconnect Impact of Resistance Impact of resistance is commonly seen in power supply distribution: IR drop Voltage variations Delay increases Power supply is distributed to minimize the IR drop and the change in current due to switching of gates © Digital Integrated Circuits2nd Interconnect IR Introduced Noise A 2cm long, 1 µm wide Vdd or Gnd wire with 1mA current and sheet resistance of 0.05 Ohm/□ gives a voltage drop of 1V. V DD f pre I R9 V DD - Δ V X M1 I ΔV ΔV R Ohmic voltage drop on the supply rails reduces the noise margins © Digital Integrated Circuits2nd Interconnect Power Distribution Low-level distribution is in Metal 1 Power is ‘strapped’ in higher layers of metal. The spacing is set by IR drop, electromigration, inductive effects Always use multiple contacts on straps © Digital Integrated Circuits2nd Interconnect Power and Ground Distribution GND VDD Logic Logic VDD GND (a) Finger-shaped network © Digital Integrated Circuits2nd VDD GND (b) Network with multiple supply pins Interconnect 3 Metal Layer Approach (EV4) 3rd “thick” metal layer added to the technology for EV4 design Power supplied from two sides of the die via 3rd metal layer 2nd metal layer used to form power grid 90% of 3rd metal layer used for power/clock routing Metal 3 Metal 2 Metal 1 © Digital Integrated Circuits2nd Courtesy Compaq Interconnect 4 Metal Layers Approach (EV5) 4th “thick” metal layer added to the technology for EV5 design Power supplied from four sides of the die Grid strapping done all in metal 90% of 3rd and 4th metals used for power/clock routing Metal 4 Metal 3 Metal 2 Metal 1 © Digital Integrated Circuits2nd Courtesy Compaq Interconnect 6 Metal Layer Approach – EV6 2 reference plane metal layers added to the technology for EV6 design Solid planes dedicated to Vdd/Vss Significantly lowers resistance of grid Lowers on-chip inductance RP2/Vdd Metal 4 Metal 3 RP1/Vss Metal 2 Metal 1 © Digital Integrated Circuits2nd Courtesy Compaq Interconnect Power Dissipation Trends 160 140 120 100 80 60 40 20 0 3.5 2.5 2 1.5 1 0 EV4 EV5 EV6 EV7 EV8 Supply Current 3.5 120 3 100 2.5 80 2 60 1.5 40 1 20 0.5 0 Better cooling technology needed Supply current is increasing faster! On-chip signal integrity will be a major issue Power and current distribution are critical Opportunities to slow power growth Voltage (V) Current (A) 0.5 140 Power consumption is increasing 3 Voltage (V) Power (W) Power Dissipation Accelerate Vdd scaling Low κ dielectrics & thinner (Cu) interconnect SOI circuit innovations Clock system design micro-architecture 0 EV4 EV5 EV6 EV7 EV8 © Digital Integrated Circuits2nd ASP DAC 2000 19 Interconnect Resistance and the Power Distribution Problem: sizing Before After • Requires fast and accurate peak current prediction • Heavily influenced by packaging technology © Digital Integrated Circuits2nd Source: Cadence Interconnect Electromigration (1) The current density in a metal wire is limited due to an effect called electromigration, which eventually causes the wire to break or to short-circuit to another wire. Line open failure Limits dc-current to 1 mA/mm © Digital Integrated Circuits2nd Interconnect Electromigration (2) Average current density and temperature are two main factors Open failure in contact © Digital Integrated Circuits2nd Interconnect Resistivity and Performance Tr The distributed rc-line R1 C1 RN-1 R2 C2 RN CN-1 CN Vin 2.5 Delay ~ L2 x = L/4 voltage (V) Diffused signal propagation x= L/10 2 1.5 x = L/2 1 x= L 0.5 0 © Digital Integrated Circuits2nd 0 0.5 1 1.5 2 2.5 3 time (nsec) 3.5 4 4.5 5 Interconnect Driving an RC-line Rs (r w,cw,L) Vout V in © Digital Integrated Circuits2nd Interconnect The Global Wire Problem Challenges No further improvements to be expected after the introduction of Copper (superconducting, optical?) Design solutions Use of fat wires Insert repeaters — but might become prohibitive (power, area) Efficient chip floorplanning Towards “communication-based” design How to deal with latency? Is synchronicity an absolute necessity? © Digital Integrated Circuits2nd Interconnect Interconnect Projections: Copper Copper is planned in full sub-0.25 mm process flows and large-scale designs (IBM, Motorola, IEDM97) Cu ~ 2.2 mW-cm vs. 3.5 for Al(Cu) 40% reduction in resistance Electromigration improvement; 100X longer lifetime (IBM, IEDM97) Electromigration is a limiting factor beyond 0.18 mm if Al is used (HP, IEDM95) © Digital Integrated Circuits2nd Vias Interconnect Interconnect: # of Wiring Layers # of metal layers is steadily increasing due to: = 2.2 mW-cm M6 • Increasing die size and device count: we need more wires and longer wires to connect everything Tins • Rising need for a hierarchical wiring network; M5 W local wires with high density and global wires with low RC S M4 H 3.5 Minimum Widths (Relative) 4.0 3.5 3.0 M3 3.0 2.5 2.5 2.0 M2 1.5 M1 1.0 poly 0.5 0.25 mm wiring stack 0.0 M5 M4 M3 M2 substrate © Digital Integrated Circuits2nd Minimum Spacing (Relative) M5 2.0 M4 M3 1.5 M1 1.0 Poly 0.5 M2 M1 Poly 0.0 m m m m m m m m m m Interconnect Diagonal Wiring destination diagonal y source x Manhattan • 20+% Interconnect length reduction • Clock speed Signal integrity Power integrity • 15+% Smaller chips plus 30+% via reduction © Digital Integrated Circuits2nd Courtesy Cadence X-initiative The main problem is that incorporating diagonal design in Design Automation tools is harder Interconnect Reducing RC-delay Optimal number of wire segments for a long wire! Repeater Lcrit=L / M AS inverter chain, the optimum is achieved when the delay of each wire segment is equal to that of a repeater! © Digital Integrated Circuits2nd Interconnect Wire pipelining clk Reg- Reg- Reg- ister ister ister • Even with repeater, wire delay may still be larger than the clock cycle • To accommodate this delay with GHz clock, wire pipelining techniques can be used © Digital Integrated Circuits2nd Interconnect Delay in Transmission Gate Networks 2.5 2.5 V1 In 2.5 Vi V i-1 C 0 2.5 C 0 V n-1 V i+1 C 0 Vn C C 0 (a) R eq R eq V1 In R eq Vi C C R eq V n-1 V i+1 C Vn C C (b) m R eq R eq R eq R eq R eq R eq In C C C C C C C C (c) © Digital Integrated Circuits2nd Interconnect Delay Optimization © Digital Integrated Circuits2nd Interconnect Resistivity and Performance The signal delay in interconnect has been dominated by RC if the signal frequency is not too high. In modern design, average length of global wires has been increasing. At the same time, the average delay of individual gate goes down (since parasitics reduces). This leads to a strange situation that it may take multiple clock cycles to transport a global signal to long distance. Accurate synchronization becomes a big challenge (the timing issues we discussed before). © Digital Integrated Circuits2nd Interconnect