Download multi-valued logic

OPTIMIZATION OF CURRENT MODE
MULTIVALUED LOGIC CIRCUITS
Avni MORGÜL and Fatma SARICA
Boğaziçi University
Electrical&Electronics Engineering Department
Istanbul, TURKEY
Presented By: Avni Morgül
26-28 Apr. 2006
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
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MVL: Multi-Valued Logic
fills the gap between digital&analog
• More than two logic level (r>2)
• Logic functions may be implemented
– Using less number of transistor (smaller chip area)
– Using less number of interconnections
– Faster
• Disadvantages:
– Static power dissipation
– Lower noise margin
• Applications:
– Faster signal processor circuits with reduced chip area and less
interconnections.
26-28 Apr. 2006
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
2
Definitions
Number of discrete values: radix (r )
discrete
out
l
In the current mode implementation
each logic level is represented by a
current level Ij = jIb ,
The base current Ib corresponds to one
step of discrete current variation.
Ij
Ib
y
(j-0.5)Ib
A logic level l corresponds to an interval
of cont. variable, y
y  l : {y|(j-0.5)Ib  y < (j+0.5)Ib }
26-28 Apr. 2006
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
jIb (j+0.5)Ib
continuous
input
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Implementation
By using current-mode CMOS circuit
i. The basic circuit Elements
x
N
z1
...
zn
x
the symbol
z1
the circuit Md
zn
Mm
1:k
n-type current mirror
1:k
z1
x
kx
N
1:k
26-28 Apr. 2006
P
...
zn
Multiplying and
re-directing a
current
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
4
Inverter
zx
r-1
Slope = -1
0
r-1
x
r  1  x
z x
0

if 0  x  r  1
if
r-1
r-1
z
N
x 1:1
26-28 Apr. 2006
x
Md
x  r 1
z
1:1
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
Mm
5
min(x,y) gate
min(x,y) = x y = x • y
1:1 y 1:1
P
N
y
x
N
y
x
y
if x  y
y
Slope = 1
otherwise
N
1:1
y
z
1:1
x
x
z
y
z
y
y
x
IC Layout
vddmin
z
yin
N1
N2 N3
N4
Trans.
N1,N3
N2,N4
(W/L)
1.75/1
1.75/1+
xin
innext
vssmin
35.5µm×19µm
26-28 Apr. 2006
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
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Threshold circuit
 c if a  b
upper threshold, thu : a |  
b  0 otherwise
c
b
a
N1
c
N2 N3
a
b
I
b
c
a
b
zu(a,b,c)
lower threshold, thl :
N1
zu
c
a
Trans. N1,2
W/L
1.75/1
N4
 c if a  b
|a  
b
 0 otherwise
c
zl
c
N3
4/1
N4
1/4
I
b
c
a
b
c
zu(a,b,c)
thu+
thl+
zl (a,b,c)
a
zl (a,b,c)
N2 N3
26-28 Apr. 2006
N4
Trans. N1,2
W/L
1.75/1
N3
4/1
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
N4
1/4
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Comparison with binary FA
3-bit binary-RCA: (84 trans.) 160µm×85µm
MVL- radix-8 adder: (12 trans.) 87µm×24µm
26-28 Apr. 2006
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
8
Level Variation Problem
• The level of the gate output signals may
vary from the predefined discrete levels
due to;
– The non-idealities in the circuit (Mismatch)
– Variation of input signals
– Noise
26-28 Apr. 2006
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
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I D  K (VGS  VT )
2
Statistical Mismatch Analysis
• Mismatch models of MOS transistors include two
terms:
– a size dependent and
– a distance dependent term
• In this study we will concentrate on size
dependent term and we assume that variations in
W/L ratios will be the dominating term
• The drain current may be expressed as follows:
I D  K (VGS  VT )
26-28 Apr. 2006
2
where
K 
1
2
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
 Cox
W
L
10
Statistical Mismatch Analysis
• The variance in z =Iout due to the
dimension mismatches in the
transistors may be defined as
2
I out
 I
  out
 K1
2
 I
 2
        out
 K
K1

 10
M9
M10
M8
y
x
y
2
 2
 
 K10

Calculated output current deviation
26-28 Apr. 2006
Vcc
M1
M2 M3
M4 M5
y LOAD
z
M6 M7
Simulated output current deviation
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
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LEVEL RESTORATION
• Unlike CMOS binary logic circuits, CMOS
MVL circuits are not self restored.
• This causes noise margin to be critical after
a number of stages.
• A level restorer circuit must be used after a
certain number of stages to recover the
signal
26-28 Apr. 2006
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
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Level Restoration
• The maximum number of identical structures that can be
cascaded, without loosing a predefined logic level at the
output, is limited.
• Maximum radix of a given MVL implementation depends on
logic level degradations of basic gates, such as min gate,
min.
• The allowable logic level degradation or a standard
deviation for each m-input gate with radix r can be
determined by
 min, max 
26-28 Apr. 2006
( Ib / 2 )
log2 ( m  1 )  m log2 r 
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
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Level Restoration
• It is necessary to restore the deviated levels after a
certain number of cascaded gates
N
in
Ib
2 min, max
Gate-1
26-28 Apr. 2006
Gate-2
Process
(W/L)n; (W/L)p
%σz/z
%σz/z
z=min(x,y)
z=max(x,y)
1.75/1; 5.5/1
3.1
4.3
2.25/1.5; 8/1.5
2.5
2.7
Gate-3
Restorer
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
Gate-4
out
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Statistical Analysis
Deviation of the output current from the nominal
value, for k cascaded stages
k =1
k =4
k =8
z, A
60
40
y= 30 A
20
0
26-28 Apr. 2006
20
40
x, A
60
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
80
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8-Level Restorer Circuit
26-28 Apr. 2006
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
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Simulations
variation
Simulation result (100 runs) for 6
stages of min circuits with large
transistors
26-28 Apr. 2006
variation
Worst case of 100 Monte Carlo
simulations for 3 cascaded stages of
min circuits with small transistors
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
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Simulations
• Spice simulations indicate that maximum allowable
number of cascaded min circuits using the dimensions of
W/L=40/20µm, is 6
• The output deviation reaches the critical noise margin
(1/2 I0) after the 6th stage for large transistors, and it is
not possible to add one more stage
• The max. number of stages for small transistors
(W/L=20/10µm) is only 3.
• A restorer circuit is necessary after these three stages.
Restoration circuit corrects the deviations at the output
current.
26-28 Apr. 2006
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
18
COMPARISON
• Qestion: ‘Which one of the following situations is
advantageous in the area consumption and noise margin
point of view:
– using a restorer circuit or,
– increasing the dimensions of the active elements?”
• The min circuit is selected as a model circuit. Dimensions of
the model circuit are chosen such that the output current of
the specified number of the cascaded blocks remain within
the critical noise margin.
• Same circuit is built by using minimum size transistors, and a
restoration circuit. Total areas are calculated for both circuit
and compared.
26-28 Apr. 2006
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
19
COMPARISON
• Layouts of the two circuits are drawn using the Magic
Layout program and total areas of the circuits are
calculated. It is found that using a level restoration circuit
reduces the total area consumption nearly 25%, compared
to large sized transistors.
Six stages with W/L=40/20µm,
Total area=497µm×271µm
26-28 Apr. 2006
Six stages with W/L=20/10µm,
plus the restorer circuit.
Total area=439µm×226µm
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
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CONCLUSION
• The number of cascaded stages is limited in the
MVL implementation due to the mismatches and
smaller noise margins compared to binary logic.
• The number of cascaded stages may be increased
either by increasing the sizes of transistors or by
adding a restorer circuit after a certain number of
stages.
• We compare these two solutions and found that
the solution with a restoration circuit saves about
25% in the total chip area.
26-28 Apr. 2006
A. Morgül – GAP’2006, Şanlıurfa, TURKEY
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