Download Diapositive 1 - ESA Microelectronics Section

A systematic procedure for the development
of hardened technology:
application to the I3T80-HR
Karl Grangé – SODERN
[email protected]
Agenda
•
•
•
•
Collaboration
Initial specifications
Initial philosophy: why to harden?
The proposed procedure step by step:
 Technology selection
 Hardening techniques
• Hardening against TID
• Hardening against latch-up
 Design kit development
• First application: the SPADA_RT ASIC
 Total dose evaluation
 Latch-up evaluation
 Analog SET evaluation
• Distribution of the I3T80-HR technology
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Collaboration
• This project is an ESA co-funded contract (TOS-EDP):
 VPC2 project, contract n°18082/04/NL/CB
• All hardening tasks performed have been done with the support of
the CEA (French atomic agency) of Bruyères-Le-Châtel (SEIM)
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Initial specifications
• Specifications are issued from the VPC2 project:
 Develop a multi sensor acquisition board, able to be inserted in a SpaceWire/RMAP
platform
 The heart of this acquisition module is a high accuracy / medium speed ASIC called
SPADA_RT (Signal Processing ASIC for Detector Array – Radiation Tolerant).
• Issued from SPADA_RT specifications, hardening task objectives can be
summarized as follow:
 Latch-up threshold:
 TID hardness:
 Life time:
> 80Mev/mg.cm²
> 60Krad(Si)
> 10-15 years
• Considering strong economic pressure, use only commercial CMOS
technologies
 Hardening By Design (none extra cost allowed)
 European factory
 MPW / MLM facility for space user (low volume)
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Initial philosophy
• Hardening By Design (HBD) seems the ideal approach when dealing with
radiations for space use (moderate environment)…
 Lower cost / higher flexibility compared to dedicated technology
 State of the art performances
• … but in practice, comparison with dedicated technology costs is not
evident:
 Time needed to design test vector (including software)
 Time and set-up costs for testing
 Time needed to exploit test results.
• Conclusion: the following approach has been chosen
 Sub-micron technology + moderate environment = HBD a priori, without test vector.
 To limit risks, all hardening technique used shall be quantified, even roughly.
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Open point #1: why is it necessary to harden?
•
Decision to harden has been taken following 3 criteria:
 High reliability with multi-mission specifications
 Latch-up free
Is it a real issue?
 Degradation due to total dose
Typical dose level for :
With a typical 0.35µm technology
•GEO
Vth ~10mV@100Krad(Si)
• 4mm of Al
Is about ~20Krad(Si)/year, which induces a
dose rate of 2Rad(Si)/h.
Could modern processes be
considered radiation tolerant?
1) Low oxide thickness
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2) Low dose rate
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Open point #2: why is it necessary to consider dose (1)?
• The radiation effect shall not be considered only from the TID
point of view:
 Degradation is time dependent.
 Degradation is temperature dependent.
 Degradation is dose rate dependent.
Transistor threshold voltage variation
The transistor is less conductor:
• Timing failure
Low Dose Rate
TID
High Dose Rate
The transistor is more conductor:
• Leakage failure
• Considering only TID at low dose rate will ignore the leakage
current failure mode:
 Low dose rate naturally increases the reliability by about 5 for the same TID
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Open point #2: why is it necessary to consider dose (2)?
• The conventional NMOS transistor is not hardened against leakage
current failure mode:
 Failure appears in the bird beak zone, side of the transistor itself.
 The bird beak oxide thickness increases from the gate oxide thickness (7nm) up to
field oxide thickness (~500nm): determination of its radiation hardness is very
complex.
 Hardening By Design can address leakage current but not threshold voltage
increasing.
Gate oxide: none relevant degradation up to 100Krad(Si)
Bird beak : Radiation hardness depend of its characteristics
Field oxide: lack of isolation between 3-10Krad(Si)
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Open point #2: why is it necessary to consider dose (3)?
•
Conclusion (0.35µm and lower technology considered):
 Test at low dose rate = only failure related to threshold voltage increasing
addressed.
 Test at high dose rate = both leakage current failure (after radiation) and threshold
voltage increasing failure (after annealing) are addressed.
 To address leakage current failure, it is necessary to harden.
Thermal
failure
XILINX VIRTEX FPGA vs total dose (0.25µm)
Failure level
Strongly FPGA code dependent !!!
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Open point #2: why is it necessary to consider dose (4)?
• In space environment, some TID sources are issued from discrete
events:
• Passage through the trapped particles belts and polar zones for LEO.
• Solar flares for GEO and extra planetary missions.
• It means that the dose rate can be transiently high.
x10000
Measured solar protons flux (10MeV & 30MeV)
between 1965 and 1985 (continuous line = Wolf
law)
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The solar eruption that took place in August 1972 (> 30Mev)
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Open point #2: why is it necessary to consider dose (5)?
•
Practical example: The BEPI-COLOMBO mission
 Mercury: 0.35UA + very low magnetic field = GEO solar flare x 10.
•
In GEO solar flare environment, the worst case for dose rate is an Anomalous
Large (AL) protons solar flare:
Computation with the software “Space
Radiations (v.5.0)” of some protons
solar flares:
1g/cm² -> 4mm
Al
 August 1972: 240rad(Si)/h behind 4mm
of Al
 October 1989: 110rad(Si)/h behind 4mm
of Al
 5Krad(Si) / 1 day -> 200rad(Si)/h behind 4mm of Al
•
It means that the need for the BEPI-COLOMBO mission considering only large
solar protons flares behind 4mm of Al without margins is:
 50Krad(Si) for 1 large protons flare with 2Krad(Si)/h of dose rate.
 100Krad(Si) for 2 larges protons flares with 2Krad(Si)/h of dose rate…
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Open point #2: why is it necessary to consider dose (6)?
•
Are large protons flares rare?
In red: maximum solar cycle
Table 2. Probability that <=n AL events will occur in t years at solar maximum
Mission duration t (years)
Number of events n
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1
3
5
7
0
76.56
49.00
34.03
25.00
1
95.70
78.40
62.38
50.00
2
99.29
91.63
80.11
68.75
3
99.89
96.92
89.95
81.25
4
99.98
98.91
95.08
89.06
5
99.99
99.62
97.65
93.75
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Open point #2: why is it necessary to consider dose (7) ?
• Thus, it is necessary to harden against TID because:
 It’s bringing reliability margin.
 All failure modes are addressed.
 High level of total dose and dose rate tolerance is also minimizing shielding requirement
(low mass / volume) and simplify ray tracing consideration.
 Low level of high dose rate tolerance need a refined mission analysis.
• Where is the frontier between high and low dose rate?
 Technology dependent (oxide thickness, quality…)
 Complex simulations needed
 Only some certitudes:
• 10Krad(Si)/h -> high dose rate
• 100Rad(Si)/h -> low dose rate
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Open point #2: why is it necessary to consider dose (8) ?
• How to apply standards?
 Low dose rate windows:
• Earth missions
• Worst case for bipolar transistors
– ECSS 22900: 36-360rad(Si)/h
– MIL.STD.883F method 1019.6: < 0.1rad(Si)/s
 High dose rate
• Extra-planetary mission
• Worst case for MOS transistors:
– ECSS 22900: 3-30Krad(Si)/h
– MIL.STD.883F method 1019.6: 50-300rad(Si)/s
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Hardening procedure: general guidelines
• Used approach
 Use a systematic approach:
• Prevent any marginal cases
• Reaction against technology disappearance
• None local optimization, taking into account biasing current, function…
 Use all known hardening measures, with a « light » approach:
• None test vector
• None new techniques
• Risk management about the light approach





Limit the temperature range (latch-up).
None memory point (SEU).
None bipolar structure.
Choice of the technology is part of the hardening procedure
« Light » environmental specifications (60KRad / 80MeV/mg.cm²)
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Technology selection criterion (1)
• Economic consideration




Exclusive supplier of a « big » customer
Market (HV, OPTO, OTP… options)
Second source, introduction year
Distribution (MPW ? Number of run per year ?)
• Electrical performances
 Simulate some representative cases
 Identify and quantify critical parameters (channel length, current density…)
 Specific needs (analog capacitors…)
• Intrinsic radiation level estimation
 Intrinsic total dose level estimation:
• Gate oxide thickness, voltage threshold, kind of isolation...
 Intrinsic latch-up level estimation
• EPI characteristic, isolation, Twin Tub, temperature range, diffusion
depth, retrograde wells…
 Technological characteristics allowing usual efficient countermeasures:
• Buried layer, Shottky module, number of metal tracks
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Technology selection criterion (2)
• Subjective approach shall be avoided (the smallest, the fashion
technology…)
 Ex: XFAB 1µm  certainly the best choice for latch-up, life time and reliability but
incompatible with the electrical need.
• Point attribution procedure concerning 21 criterion in the previous 3
categories has been established:
 Elimination:
 Negative point:
 Null:
 Positive point:
incompatibility with the application.
hypothesis done in the initial analysis were optimistic on
this point.
conform to the initial analysis
Real advantage compared to the initial analysis.
for each criteria, an “ideal” response shall be prepared.
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Technology selection criterion (3)
Economic section
Introduction year
Specific market identified (exclusive supplier…)
Specific devices (HV, OTP, EEPROM…)
Second source identified
Product costs section
MPW program
Independent MPW agency
Nb of MPW run per year
Price (10mm²)
CAD tools
Electrical performances section
Power supply capability
Capacitor quality (voltage dependence)
Minimum feature length
Maximum MOS threshold voltage
Radiation section
Gate oxide thickness
Devices isolation
Number of metal layers
Burried layer
EPI layer
Retrograde wells
Specific customer section
Founder nationality
Foundry location
Red = parameters with elimination condition
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Issued from economic analysis
on life time
Issued from economic analysis
of project costs.
Issued from initial analysis + simulations
Extensive bibliography of well known
hardening techniques
Customer request
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Technology selection criterion (4)
• This systematic procedure help to formalize the need.
•
All proposed parameters are accessible with a simple NDA.
• The selected technology is the I3T80 CMOS 0.35µm from AMIS (ex
ALCATEL).
 The I3T80 is a hetero epitaxy process, which allow HV devices thanks to electrically
isolated pocket
 This kind of process is growing due to SoC applications.
NEPI
NEPI
Deep P-plugs allow electrical isolation
N-epitaxy
P-substrate
(80V) of adjacent N-EPI pockets
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Hardening technique: TID (1)
•
The following failure modes are addressed:
 Device to device leakage current (NMOS):
LOCOS
n+
n+
n+
n+
LOCOS
Leakage current
PWELL
 Intra device leakage current (NMOS)
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Hardening technique: TID (2)
• NMOS device to device leakage current is easily cancelled
via systematic guard rings
p+
n+
n+
p+
p+
n+
n+
p+
None parasitic path
PWELL
NEPI
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Hardening technique: TID (3)
• For the intra device leakage current, a modified NMOS geometry is
needed:
 Classical circular geometry is not adopted because accurate electrical
model can not be obtained without tests.
• The geometry chosen is electrically 80% compatible with the
classical geometry and its hardening level is compliant with
100Krad(Si).
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Hardening technique: TID (4)
Geometry
T1 & T2
Tm
POLY extension
Tox
C1
Main transistor
(finger type)
Leakage path
Tox = C2, C3 and C4
regions.
Electrical model
Thanks to its great similitude with
the classical geometry, an high
accuracy is obtained on the
electrical modeling “a priori”.
Field oxide.
P+ active area (bulk strap)
N+ active area (drain source diffusion)
POLY:
o POLY on active = thin oxide
o POLY on field oxide = thick oxide.
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The leakage path still to exist but connect
two diffusion at the same potential :
o None electrical effect.
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Hardening technique: Latch-up (1)
• As baseline, the proposed technology increases the latch-up
hardening by a factor 6 if NMOS and PMOS transistors are
manufactured in separated pockets.
²
VDD
VDD
N+
VDD
P+
PMOS
NWELL
VSS
T1
RNWELL
VSS
N+
RPWELL
RNEPI
T2
N+
RPWELL
T4
PWELL
P+
NMOS
PMOS pocket
VDD
T3
P+ diffusion
NEPI
RNWELL
T1
NWELL/NEPI
RNEPI
PWELL (sinker part)
T2
I(heavy ion)
RPWELL
NEPI
T3
T4
Parasitic SCR circuit
PWELL
RPWELL
N+
NMOS pocket
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Isolation wall
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Hardening technique: Latch-up (2)
• In addition to the previous rule (NMOS & PMOS shall be manufactured
in separated EPI pocket), others hardening rules are added (see initial
philosophy):




Systematic guard ring around PMOS and NMOS
PMOS and NMOS above buried layer
Limit the transistor size
Limit the wells (buried layer) size
• Purpose of size limiting rules is to prevent:
 S/D junction turn ON for transistor sizing limitation
 Wells junction turn ON for NWELL or PWELL sizing limitation
In case of ion strike.
• Sizing limitation is computed with analytical models.
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Hardening technique: Latch-up (3)
• Cross-section with hardening rules:




NMOS
NMOS
NMOS
NMOS
and
and
and
and
PMOS
PMOS
PMOS
PMOS
in separated N-EPI pocket
wells above buried layer
have maximum dimension
wells have maximum dimension
NEPI
NMOS
PMOS
NPLUG
P
PWELL
+
NWE
LL
PSINKER
BLP
PWELL
P
+
NWE
LL
BLN
P
+
NWE
LL
NWELL
BLN
PSUB
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Hardening technique: Latch-up (4)
• Sub-model 1: Layer isolated by junction is used to fix the
maximum transistor size.
• Sub-model 2: layer above a low impedance buried layer with the
same polarity (N or P) used to fix the maximum wells dimension:
2.R1max
S/D diffusion
POLY gate
Guard ring
Charges (ion)
Sub-model1: Transistor size
Buried layer
NPLUG
NEPI
2.R2max
Wells (N or P)
Sub-model1: Wells size
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Practical implementation of hardening rules
•
Practically and to prevent weak points, a new design kit has been coded with all
hardening rules (ESD pads included)
•
Compared to the original one, the following modifications have been done:







•
Unused elements removed (front and back end)
MOS electrical models modified
MOS geometries modified
DRC rules modified (latch-up rules + detection of removed elements)
Extraction rules modified (mainly for NMOS extraction)
Basic library modified (ESD pads)
Digital gates redesigned
17 months have been necessary for:




Technology selection
Hardening rules
Design kit coding
SPADA_RT chip design and test
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First application: the SPADA_RT
•
The proposed flow have been validated with the development of an
mixed ASIC.
 SPADA_RT = Signal Processing ASIC for Detector Array _ Radiation Tolerant.
 Multi sensor chip: CCD, APS, HgCdTe
 Include all necessary circuitry for sensor / house keeping conditioning (ADC excluded)
•
Both electrical and environmental specifications have been met at the
first run.
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Input dynamic
4Vpp
Output dynamic
4Vpp
Functionality
CLAMP
CDS or single sampling.
Offset injection
Output analog three state
ENOB (with a theoretical ADC)
12 (gain independent)
Pixel frequency
100KHz / 3MHz
HK chains
4 (multiplexed)
Number of clocks
2
Power supply
3.3V
Power consumption
30mW (typical)
Temperature range
-20°C / +80°C
© EADS SODERN
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SPADA_RT TID results (1)
• TID evaluation of the SPADA_RT has been done at PAGURE
(France) facility.
• Method used is the ESCC.22900 method:
 Standard windows
 10Krad(Si)/h
 5 steps: 0Krad(Si), 30Krad(Si), 60Krad(Si), 120Krad(Si) and annealing.
• 5 dies
• None functional or specification failure has been measured.
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SPADA_RT TID results (2)
TID power current drift
TID offset drift
1.004
1.01
1
0.99
0.998
OFFSET SPADA1
OFFSET SPADA2
0.98
OFFSET SPADA3
0.97
OFFSET SPADA4
OFFSET SPADA8
0.96
Drift (arbitrary unit)
Drift (arbitrary unit)
1.002
1
CURRENT SPADA1
0.996
CURRENT SPADA2
0.994
CURRENT SPADA3
0.992
CURRENT SPADA4
0.99
CURRENT SPADA8
0.988
0.986
0.95
0.984
0.94
0.982
0
30
60
120
Burn in
0
30
TID (KRad(Si))
120
TID (KRad(Si))
TID NOISE drift
TID INL drift
1.04
1.6
1.02
1.4
1
NOISE SPADA1
0.98
NOISE SPADA2
0.96
NOISE SPADA3
NOISE SPADA4
0.94
NOISE SPADA8
Drift (arbitrary unit)
Drift (arbitrary unit)
60
1.2
INL SPADA2
0.8
INL SPADA3
INL SPADA4
0.6
0.92
0.4
0.9
0.2
0.88
INL SPADA1
1
INL SPADA8
0
0
30
60
120
Burn in
0
TID (KRad(Si))
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60
120
Burn in
TID (KRad(Si))
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SPADA_RT latch-up results
•
Test set-up:






Specie
C
Ne
Ar
Ni
Kr
Kr
•
Power supplies:
Number of DUT:
Temperature:
Die pixel frequency:
Location:
Heavy ions cocktail:
Angle
0°
0°
0°
0°
0°
60°
+3.3V +/-2%
5
+25°C +/- 2°C
120KHz
LOUVAIN (CYCLONE)
See the next table.
Flux (p/(cm².s))
1E7
1E7
1E7
1E7
1E7
1E7
LET (Si)
1.2 Mev/mg.cm²
3.3 Mev/mg.cm²
10.1 Mev/mg.cm²
21.9 Mev/mg.cm²
32.4 Mev/mg.cm²
64.8 Mev/mg.cm²
Penetration (µm)
266
199
120
85
92
46
None latch-up detected.
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SPADA_RT analog SET results
A complete characterization of analog Single Effect Transient (Analog
SET) have been done:
 Event = upset of +/-25mV around the steady state value (better accuracy is not possible
due to the noisy environment)
SPADA_RT cross-section
1.00E-05
1.00E-06
Orbit : SPOT5 800 km
Image shoot: 15 mn
Quiet period
6.36E-07 upset/device/15'
Solar Flare period
1.21E-04 upset/device/15'
event.cm²
•
1.00E-07
1.00E-08
0
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10
20
30
40
LET (Mev/mg.cm²)
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50
60
70
© EADS SODERN
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I3T80-HR distribution (1)
• In accordance with ESA, this technology is now available for all
potential ESA users:
 MPW facilities always accessible
 SODERN / EUROPRACTICE kit distribution (under analysis)
• The nominal kit is available under HyperSilicon software suite
(TANNER)
 Low cost
 New verification suite include is compatible with CALIBRE
 Digital & analog library accessible (including the SPADA_RT)
• In addition of this nominal kit, an innovative distribution flow called
Netlist-to-layout is also accessible:
 From our library, the user develops the front end, SODERN make the back end, up to
the tape out,
 User do not need any specific software or competences: he simply uses a low cost
simulator (PSPICE, HSPICE…).
 Similar digital flow in 2007.
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I3T80-HR distribution (2)
CUSTOMER
SODERN
Netlist to layout design kit
Front end develomement
(schematic)
Netlist (*)
Floor plan:
 Power supplies
 Package
 Critical nets
Floor plan specification
Feedback to correct parasitic
elements effects
Layout
Extracted netlist (included
parasitic elements)
Extraction
Final netlist
Validation simulations
Manufacturing order
Tape out (GDSII)
Manufacturing



Packaging
Foundry DRC checking
Naked and packaged dies
PVM (wafer lot measurement)
(*) Netlist can be issued from schematic (analog) or digital synthesis (limited to 50K gates)
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End
• Thank you for your attention.
Karl Grangé – SODERN
[email protected]
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