Download Concept and Proposal Augmenting the Design Flow with

Physical & Timing Verification
of Subwavelength-Scale Designs
using Physical Simulation
Robert Pack (formerly of Cadence Berkeley Labs)
Valery Axelrad, Andrei Shibkov, Victor Boksha
(Sequoia Design Integration, Inc.)
Judy Huckabay, Rachid Salik, Wolf Staud
(Cadence Design Systems, Inc.)
Ruoping Wang, Warren Grobman (Motorola Inc.)
SEQUOIA
Outline
Introduction
 Problem Statement
 OPE Impact on Device Performance
 OPE and RET effects
 Timing Analysis
 Multi-partioning of critical devices
 Summary

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Introduction


DPI closure is key for successful <130nm designs
Current state-of-art EDA tools insufficient


insufficient in predicting performance
insufficient in predicting yield/reliability

Timing , SI, Race Conditions, Power… +/- %100

These factors are responsible for costly fabrication yield
re-spins – >%30 ! . Failure Costs are high!

Residual design-to-silicon distortions

Design and verification must account for increased process and
device physics entanglement

Novel verification approach
unique new adjunct to DFM and MSO flows

SEQUOIA
60%
Number of Silicon Spins in Current IC/ASIC Designs
n=329
53%



Percent of Teams
Problem statement
Excessive Re-spins
Large % of flaws
due to SI and Power
Parametric and Catastrophic Yield
Loss
45%
28%
30%
15%
15%
3%
0%
First Silicon
2
3
4
Spins of Silicon


Logical or Functional
43%
Slow Path
Feature Limited
Reliability Issue
14%
9%
Yield
7%
Race Condition
6%
Mixed-Signal Interface
5%
Other Flaws
5%
IR Drops
Proximity Effects
4%
Clocking
3%
Power
3%
0%


Device
LITHOGRAHIC


5 or More
Percent of Total Flaws Fixed in
IC/ASIC Designs Having Two or More Silicon Spins
Noise

2%
Source: Collett International Research 2000
10%
20%
30%
40%
50%
Percent of Flaws
Product Yield
100%
Mitigation: OPC/PSM
90%
Design Tools lack ability
to capture complex physical effects
80%
70%
Traditional defect-limited yield
Feature-limited yield
60%
0.8 µm 0.5 µm 0.35 µm 0.25 µm 0.18 µm 0.13 µm 0.1 µm
Technology Node
Note:
SEQUOIA
Featurelimited yield assumes the feature failure rate improves by appro
ximately 50% each
generation
Source: Kibarian/PDF Solutions & Collet
“Silicon Verification” must be performed
before committing a SubWavelength design to
silicon.
Silicon Level
Verification
Physical
Verification
Design
Layout - DRC

Silicon - DRC
X
Layout - LVS

Silicon - LVS
X
Layout - Timing

Silicon - Timing
X
Layout
Compares silicon to layout
SEQUOIA
Specific Problem: Silicon-Level Verification
Industry focusing on Interconnects
-
Contact pullback can
result in high resistance
OPE
Impact on Device
or opens
Parasitics from
silicon-level layout
are different from
those extracted from
drawn layout
DVt, Ileakage
Performance
DCp
SEQUOIA
Distributed
Gate length
Devices from siliconlevel layout have
different device
properties than from
drawn layout.
Verification of Process Proximity Effects
- through physical simulation



OPE
affects
Contactdistortion
pullback can
result in highperformance
resistance
transistor
and
or opens
matching
OPE distortion affects
parasitics extraction accuracy
OPE is the major deterministic
source of device variability
DVt, Ileakage
Distributed
Gate length
electrical impact of image
quality
 gate length variation
 line end pullback
Parasitics from

silicon-level layout
DCp
 Complicates
performance
are different from
estimation
/ bin
sort yield
those extracted
from
drawn layout
SEQUOIA
Devices from siliconlevel layout have
different device
properties than from
drawn layout.
OPE is the major deterministic source of
device variability
Tdelay ~ CV / I drive
Tdelay ~ CaverageV / I average_ drive
OPE impacts
• device performance characteristics
• Vth
• Idsat
• Ioff
t
Hea
• Power (leakage)
• Yield/Reliability
Leakage/
Shorts
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Vds
Additional Complexity
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Experimental Simulation Conditions



248nm
NA=0.7
Source:

Binary and OPC


altPSM






Pillbox; Sigma=0.6
Binary: Sigma=0.6
PS: Sigma=0.35
OPC Style: Aggressive Simulation-Based OPC
PSM Style: NTI Double Exposure altPSM
NOT A Motorola process
Not lithographically refined or RET optimized
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Experimental Structure

32-bit Adder scaled to 150nm
4285 MOSFETs / CMOS technology
 Lithography simulation performed fullstructure

K-T/Finle -Prolith
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Defocus Effect
BIM – 0.1um steps
BIM 0-Def
0.2-Def
0.1-Def
0.1-Def
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0.3-Def
0.2-Def
0.4-Def
0.3-Def
0.4-Def
RET Effects
BIM,BIM+OPC,PSM+OPC
BIM, 0-Def
BIM, 0.3-Def
BIM+OPC, 0.3-Def
PSM+OPC, 0.3-Def
BIM, 0.4-Def
BIM+OPC, 0.4-Def
PSM+OPC, 0.4-Def
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Timing Results
• First Technique – (Rachid’s gate averaging)
• Primarily a catastrophic Yield issue
• Leakage from line end shortening not considered
• Some transistors are outside of the model bounds
1.60E-09
1.40E-09
1.40E-09
SPICE Results
1.20E-09
1.20E-09
1.00E-09
1.00E-09
0
.
0
Ideal
8.00E-10
8.00E-10
0.0um
psm_Defocus_1
0.1um
psm_Defocus_2
6.00E-10
6.00E-10
4.00E-10
4.00E-10
2.00E-10
2.00E-10
0.00E+00
0.00E+00
0.2um
psm_Defocus_3
0.3um
psm_Defocus_4
Net31
•BIM
OPC
Net27 Net28 Net29Net27
Net30Net28
Net31Net29 Net30 PSM
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Electrical Analysis of Proximity Effects



Active devices
(MOSFETs)
responsible for circuit
variability
Root cause of
variability in sub130nm mosfets is
MOSFET geometry
(CD control)
Geometry is the result
of mostly deterministic
effects and
predictable
Line-end pullback causes MOSFET leakage -> Yield Problem
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Impact of Process Variation




Process variation causes
image degradation
Defocus process window
is important for
manufacturability
Shown is the aerial
image of the poly layer at
increasing defocus
Gate length variation and
line-end pullback cause
MOSFET parameter
variation and failure
0.2um defocus
Defocus
degrades image
No defocus
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Electrical Impact of Proximity Effects




Proximity effects cause
distortion depending on
shape and environment
of features
Short poly segments
(small mosfet W) print
differently from long ones
Proximity of other gates
impacts gate shape and
electrical performance
Context of a mosfet must
be considered when
predicting its properties
SEQUOIA
0.15um defocus
0.2um defocus
Defocus
degrades image
MOSFET Variability and Yield



Defocus causes the
gate length
distribution to widen
and shift to shorter
gates
Circuit failure
results from strong
MOSFET parameter
variation
In extreme cases
Source/Drain shorts
(=very short gates)
cause functional
failure
SEQUOIA
MOSFET Gate
Lengths
MOSFET
Idsat
0.1um defocus
0 defocus
0.1um defocus
0 defocus
Failure Outside Process Window



Failure is observed
as zero-length
MOSFET by the
verification tool
SPICE timing
analysis confirms
circuit failure in this
case
Statistical analysis of
MOSFET distribution
across process
window can be used
to predict
manufacturability
SEQUOIA
Zero-length gates: Failures
0.2um defocus
MOSFET Gate
Lengths
Conclusions
 Current state-of-art EDA design and verification tools have
insufficient predictive performance capability in the Nanometer Era
– Timing , SI, Race Conditions… +/- %100
 These factors are also responsible in great part for costly
fabrication re-spins – >%30 ! . Failure Costs are high!
 Residual design-to-silicon distortions are a fact of life and must be
accounted for in Nanometer Era
 Design and verification tools must account for increased process
and device physics entanglement. Verification must consider the
impact of process proximity and process variation on circuit
performance
 Continuation of historical cycle, impact however is greater now than
ever before
 A novel verification methodology is proposed as a unique new
adjunct to DFM and MSO flows to reduce costly re-spins and
improve inherent design quality and manufacturability.
Catch Potential Re-Spin Failures Before Mask and Silicon !
SEQUOIA
Acknowledgements


Thank you Chris and Ed at KLA-Tencor/Finle for RC
Pack use of Prolith for ‘Gold-Standard’ confirmation and
future work
Thank you Vinod and Fabio at Numerical Technologies
for RC Pack use of IC Workbench for confirmation and
future work
SEQUOIA
Additional Supportive Materials
SEQUOIA

‘Naive’ Simulation-based OPC


Can make ‘pretty pictures’ on silicon but impact the real process
window
At some level of k1, the context of the circuit and the device must
be considered carefully





Many digital circuits are very forgiving of some levels of distortion..
but unforgiving of others
Analog circuits/devices have their own special consideration
Increased design-process integration care must be taken … it’s
not just about making ‘pretty pictures’ on silicon
Judicious and minimal usage of OPC
Optimization target must be performance & Yield across
Process-window.
SEQUOIA
Important issues for Designers, EDA,
Maskmakers, lithographers, device designers,
manufacturing…





Entanglement of traditionally separable entities.
The determination of which features are
dimensionally and visually good enough must be
done on the basis of the feature function and IC
operational and manufacturing requirements.
Visual metrics are no longer sufficient
This era require new tools, new standards, new
infrastructure…..
For EDA…It’s not just about wire RLC and
parasitics
SEQUOIA
Acknowledgements


Thank you Chris and Ed at KLA-Tencor/Finle for RC
Pack use of Prolith for ‘Gold-Standard’ confirmation and
future work
Thank you Vinod and Fabio at Numerical Technologies
for RC Pack use of IC Workbench for confirmation and
future work
SEQUOIA