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1 Visibility Enhancement for Silicon Debug Yu-Chin Hsu, Furshing (Kevin) Tsai, Wells Jong, Ying-Tsai Chang Outline Motivation Design for Debug methodology Challenges in debug using silicon data Visibility Enhancement techniques Experimental results Summary 3 Bottleneck in Prototype-to-Volume Time Concept Volume Silicon Prototype Design Test/Debug 7 to 8 months Decreasing 6 to 7 months Increasing! Data Quest (2002, 2004) report Smaller design margins – increasing chance of performance failures Unmodeled defects – higher tester escapes More transistors – increasing time to isolate physical defects Greater device complexity – requiring more time and vectors to validate 4 Silicon Testing Issues Test APP × × Functional design errors not detected pre-silicon due to constraints Structured tests (ATPG, BIST, etc.) do not replicate real-world conditions, resulting in “over-testing” and “under-testing”, examples: – High power consumption - voltage drops - change in VTH: chip rejected – Crosstalk effects - pattern sensitive – not targeted: chip passed Defects difficult to model escape detection by testers System-level testing is the ultimate environment where defects are found 5 On-chip Hardware - Design-for-Debug Debugging silicon in situ easier when designed with “visibility” into internal nodes Logic which brings out data from the silicon while in the system is known as “design-for-debug” (DFD) logic – IJTAG – on top of DFT – On chip trace buffer Most DFD today is proprietary, although DFD commercial offerings are increasing DFD utilized when failures occur during system validation 6 Design-for-Debug (DFD) on the Chip - Example DFD DFD is not the same as DFT: Debug logic must function during system-level operation Many DFD implementations Real-time Scan& clock control reset control leverage DFT circuitry: – IEEE 1149.1 controller (boundary scan) – Internal scan chains (full scan) Combinational logic DFD is the access mechanism that provides insitu scan register visibility DFT 7 Complete System for Silicon Debug pod scan data APP Visibility enhancement Debug On-chip DFD typically hooks up to a pod and is activated by a separate software-based control program The pod is a device that makes the electrical characteristics between the DFD port and the PC port compatible The DFD control program accesses data such as the internal register The limited data is then processed to maximize visibility into design operation 8 Challenges in DFD Data Analysis Limited resource available – only a subset of signals can be probed Limited visibility – only a subset of signals can be extracted from silicon Low level of abstraction – unfamiliar design to designer 9 Visibility Enhancement -- Overview Visibility Planning – Analyze design (RTL, gate) and provide optimal (minimal and sufficient) set of signals to be observed – Provide visibility tradeoff information – “expansion potential” of candidate signals Data Expansion – Process limited data and expand (regenerate) missing signal information for exploration and debug – On-the-fly operation for optimal performance Abstraction Correlation – Map gate-level signals and instances back to RTL origin – Translate gate-level signal information (waveform data) to match RTL design for designer-level debug 10 Silicon debug with DFD and Visibility Enhancement Visibility Planning Data Expansion & Abstraction Correlation 11 Visibility Analysis and Planning Visibility Analysis (VA) engine determines which set of signals are essential for data expansion A signal value can be made visible if its parent (preceding gate) is visible Primary inputs are considered visible 12 Data Expansion 0 1 1 0 0 1 ? ? ? ? ? ? 1 1 1 ? ? Data expansion 0 1 1 0 0 0 0 1 0 1 1 0 ? ? ? 0 1 ? ? 1 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 Data expansion (DE) engine makes limited data useful – more visibility Boolean calculation of unobserved combinational network values Maximize value computation thru use of “Don’t Care” truth table results DE metric: signals-with-values/total-number-of-signals Performance optimized by expanding only the logic under investigation and no simulation-like timing wheel 13 Data Expansion - Requirements Raw signal data obtained from chip is stream of 0’s and 1’s Control application must make the data usable for analysis applications Steps for the control application: – Assign temporal information – relative cycle time must be associated with each scan dump – Map each value to an HDL signal – Output the results in a usable format - VCD (IEEE 1364-2001) or FSDB (Novas) 14 On-the-fly Data Expansion Large volume of data to be generated if computed in bath mode. HDL Source Gate Netlist Silicon w/DFD Data expansion Netlist Register Values Gate/RTL Signal Values Debug On-demand value request FSDB 15 Debug at Higher Level of Abstraction To Transaction To RTL Systems RTL Gate Gates Gate level design is unfamiliar to designer Silicon 0100101110010110 1101011000110110 1000011111000000 16 Abstraction Correlation Silicon signal data is usually easy to assign to gate-level signals Gate-level netlist and values are difficult for RTL designers to understand and debug Correlation Data must be mapped to the “designers world” for efficient debug and collaboration One-to-one correspondence is not always the case after synthesis transformations 17 Abstraction Correlation - Mapping Name-based mapping – Predefined rule mapping (delimiters, escaped name, naming convention for register, etc.) – Regular-expression-based user-defined renaming rule Structural dependency analysis – Find structural bounding mappable signal set of nameunmappable signal. – Find structural fanin/fanout intersect of the mapped signal set for related circuit part. – Important concept: granularity (fundamental limitation) and relevance (heuristic). – Name-based mapping should provide a certain percentage of mapped signals for this to work. This could often be achieved after setting some user-defined renaming rules because synthesis tools typically preserve/transform quite well some of the signal naming, especially registers 18 Abstraction Correlation - Mapping 19 Abstracting Signal Data to Transactions A1 A2 A3 A… Addresses sent S1 M1 D11 D12 Data Extraction D13 M2 Transaction visualization eases understanding of communication protocols 3X4 2X4 … S2 S3 D22 D31 Signal Data AMBA AXI, AMBA AHB, PCI Express, OCPIP,UART, DDR, MPEG Data Extraction M3 S4 Data Extraction Open Transactor Interface D21 nTX 20 Results - Correlation Case #1 Case #2 total 990 952 Can be mapped 1 statement 207 21% 180 19% 684 69% 307 32% 2-3 statements More than 3 statements Cannot be mapped 54 5.4% 194 20% 21 2.1% 213 22% 24 2.5% 58 6% 21 Results - Data Expansion # of signals # of % essential/ essential % visible total signals Case #1 138842 13190 Case #2 6808801 992248 14.6% 100% Case #3 4560874 173544 3.8% 100% 9.5% 100% 22 Summary Silicon debug/diagnosis is a bottleneck to time-to-volume Emerging DFD techniques make data accessible Silicon data must be expanded and HDL Debug correlated in order for the designer to debug The proposed method leverage DFD data and make it System Validation possible to effectively use HDL-oriented tools for silicon debug 23